CN102446884A - 封装单元及其堆叠结构与制造方法 - Google Patents

封装单元及其堆叠结构与制造方法 Download PDF

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CN102446884A
CN102446884A CN2011102629245A CN201110262924A CN102446884A CN 102446884 A CN102446884 A CN 102446884A CN 2011102629245 A CN2011102629245 A CN 2011102629245A CN 201110262924 A CN201110262924 A CN 201110262924A CN 102446884 A CN102446884 A CN 102446884A
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conductive pole
semiconductor element
substrate
encapsulation unit
insulating barrier
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洪英博
张道智
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Industrial Technology Research Institute ITRI
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Industrial Technology Research Institute ITRI
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Abstract

本发明公开一种封装单元及其堆叠结构与制造方法，其包括提供一基板；形成一第一图案化线路层及一第一导电柱，第一图案化线路层设置于基板的一表面，第一导电柱贯穿基板并连接第一图案线路层；设置一半导体元件于基板上，半导体元件包括至少一芯片；形成一绝缘层于半导体元件及基板上；形成一第二导电柱、一第三导电柱及一第二图案化线路，第二导电柱贯穿绝缘层并电连接第一导电柱，第三导电柱贯穿绝缘层并连接半导体元件，第二图案化线路层设置于绝缘层上并连接第二导电柱及第三导电柱。

Description

封装单元及其堆叠结构与制造方法
技术领域
本发明涉及一种封装单元及其堆叠结构与制造方法，且特别是涉及一种内埋式封装单元及其堆叠结构与制造方法。
背景技术
随着科技的发展，各式电子装置不断推陈出新。其中电子装置内最重要的电子元件莫过于半导体芯片。半导体芯片经过封装后，形成一封装单元。此封装单元可以利用插件(DIP)或表面粘着技术(SMT)设置于电路板上，以提供各种运算与处理功能。
封装单元的制造过程可能包括电镀通孔、连接两个金属层、打线焊接及封胶等步骤。然而，封装单元的设计不良，容易在制作工艺步骤中或成品产生一些可靠度的品质问题。
发明内容
本发明的目的在于提供一种封装单元及其堆叠结构与制造方法。
为达上述目的，根据本发明的第一方面，提出一种封装单元。封装单元包括一基板、一第一图案化线路层、一第一导电柱、一半导体元件、一绝缘层、一第二导电柱、一第三导电柱、一第二图案化线路层及一导电凸块。第一图案化线路层位于基板的一表面。第一导电柱贯穿基板，并连接第一图案化线路层。半导体元件设置于基板上。半导体元件包括至少一芯片。绝缘层覆盖半导体元件及基板。第二导电柱贯穿绝缘层，并电连接第一导电柱。第三导电柱贯穿绝缘层，并连接半导体元件。第二图案化线路层位于绝缘层上，并连接第二导电柱及第三导电柱。导电凸块设置于第二图案化金属层上。
根据本发明的第二方面，提出一种封装单元的堆叠结构。封装单元的堆叠结构包括二封装单元。各个封装单元包括一基板、一第一图案化线路层、一第一导电柱、一半导体元件、一绝缘层、一第二导电柱、一第三导电柱、一第二图案化线路层及一导电凸块。第一图案化线路层位于基板的一表面。第一导电柱贯穿基板，并连接第一图案化线路层。半导体元件设置于基板上。半导体元件包括至少一芯片。绝缘层覆盖半导体元件及基板。第二导电柱贯穿绝缘层，并电连接第一导电柱。第三导电柱贯穿绝缘层，并连接半导体元件。第二图案化线路层位于绝缘层上，并连接第二导电柱及第三导电柱。导电凸块设置于第二图案化金属层上。其中，此些封装单元的其中之一的第一图案化线路设置于此些封装单元的其中之另一的导电凸块上。
根据本发明的一第三方面，提出一种封装单元的制造方法。封装单元的制造方法包括下列步骤。提供一基板。形成一第一图案化线路层及一第一导电柱。第一图案化线路层设置于基板的一表面。第一导电柱贯穿基板并连接第一图案线路层。设置一半导体元件于基板上。半导体元件包括至少一芯片。形成一绝缘层于半导体元件及基板上。形成一第二导电柱、一第三导电柱及一第二图案化线路。第二导电柱贯穿绝缘层并电连接第一导电柱。第三导电柱贯穿绝缘层并连接半导体元件。第二图案化线路层设置于绝缘层上并连接第二导电柱及第三导电柱。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合所附附图，作详细说明如下：
附图说明
图1为本实施例的封装单元的制造方法的流程图；
图2A～图2G为图1的各步骤的流程图；
图3为第一实施例的封装结构的示意图；
图4为第一实施例的封装单元的堆叠结构的示意图；
图5为第二实施例的封装单元的制造方法的流程图；
图6A～图6G为图5的各步骤的流程图；
图7为第二实施例的封装单元的堆叠结构的示意图。
主要元件符号说明
100、200：封装单元
110：基板
110a：上表面
110b：侧表面
121：第一图案化线路层
121a：第一接垫
122：第二图案化线路层
122a：第二接垫
131：第一导电柱
132：第二导电柱
133：第三导电柱
141：第一防焊层
141a：第一开口
142：第一防焊层
142a：第二开口
150：半导体元件
160：绝缘层
170：导电凸块
281：第一金属材料
280：介金属层
1000、2000：堆叠结构
D150、D160：厚度
L131、L132：长度
S101、S102、S104、S105、S106、S107、S108、S203、S207、S208：
W131、W132：最小宽度
具体实施方式
第一实施例
请参照图1及图2A～图2H，图1绘示本实施例的封装单元100(完整的封装单元100绘示于图2G)的制造方法的流程图，图2A～图2G绘示图1的各步骤的流程图。首先，如图2A所示，在步骤S101中，提供一基板110。基板110例如是一有机基板、一软性基板或一硅基板。
接着，同样如图2A所示，在步骤S102中，形成一第一图案化线路层121及至少一第一导电柱131。第一导电柱131的数量可以是一个、两个或两个以上。在本实施例中，第一导电柱131以两个为例做说明。第一图案化线路层121设置于基板110的一表面110a。第一导电柱131则贯穿基板110并连接第一图案线路层121。
在此步骤中，可以先进行激光钻孔、机械钻孔或蚀刻钻孔，再利用电镀制作工艺同时形成第一导电柱131及第一图案化线路层121。其中，本实施例的第一导电柱131的材质包含铜(Cu)。第一导电柱131可以被填满铜或高分子材料(例如树脂)而成为紧密的实心柱体，或仅有内壁被铺设铜而成为空心柱体。
在一实施例中，形成第一图案化线路层121后，也可再铺设一第一防焊层141，并以第一开口141a暴露部分的第一图案化线路层121，以形成第一接垫121a。
然后，如图2B所示，在步骤S104中，设置一半导体元件150于基板110上。在此步骤中，半导体元件150可以一具粘晶作用的胶粘剂(adhesive)粘置于基板110上，且半导体元件150可以是一芯片或者是包含一个芯片或多个芯片的封装单元。在本实施例中，半导体元件150以一芯片为例做说明。
接着，如图2C所示，在步骤S105中，形成一绝缘层160于半导体元件150及基板110上。在此步骤中，绝缘层160为紫外线(UV)固化材料、热固化材料或是紫外线固化材料与热固化材料的混合。绝缘层160覆盖了第一导电柱131的表面，且绝缘层160覆盖了半导体元件150的上表面150a及侧面150b。也就是说，半导体元件150完全被绝缘层160及基板110所包覆。
然后，如图2D～图2E所示，在步骤S106中，形成至少一第二导电柱132、至少一第三导电柱133及一第二图案化线路122。第二导电柱132贯穿绝缘层160并电连接第一导电柱131，第三导电柱133贯穿绝缘层160并连接半导体元件150，第二图案化线路122于绝缘层160上并连接第二导电柱132及第三导电柱133。第二导电柱132及第三导电柱133的数量可以是分别是一个、两个或两个以上。在本实施例中，第二导电柱132及第三导电柱133的数量分别以两个为例做说明。
在此步骤中，可以先进行激光钻孔、机械钻孔或蚀刻钻孔(如图2D所示)，再利用电镀制作工艺同时形成第二导电柱132、第三导电柱133及第二图案化线路层122。其中，本实施例的第二导电柱体132及第三导电柱体133的材质包含铜，第二导电柱132及第三导电柱133可以被填满铜而成为实心柱体，或仅有内壁被铺设铜而成为空心柱体。
接着，如图2F所示，形成第二图案化线路层122后，也可再铺设一第二防焊层142，并以第二开口142a暴露部分的第二图案化线路层122，以形成第二接垫122a。
然后，如图2G所示，在步骤S107及步骤S108中，形成金属材料(金属材料为制作工艺中的半成品材料，故未绘示于图2G)于第二图案化线路122的第二接垫122a上，并回焊金属材料，以使金属材料回焊为一导电凸块170。其中本实施例的金属材料的材质包含锡。
如图3所示，其绘示第一实施例的封装单元100的示意图。通过上述步骤即可完成一个封装单元100。此封装单元100包括基板110、第一图案化线路层121、第一导电柱131、半导体元件150、绝缘层160、第二导电柱132、第三导电柱133、第二图案化线路层122及导电凸块170。第一图案化线路层121位于基板110的表面110a。第一导电柱131贯穿基板110，并连接第一图案化线路层121。半导体元件150设置于基板110上。绝缘层160覆盖半导体元件150及基板110。第二导电柱132贯穿绝缘层160，并电连接第一导电柱131。第三导电柱131贯穿绝缘层160，并连接半导体元件150。第二图案化线路层122位于绝缘层160上，并连接第二导电柱132及第三导电柱133。
就绝缘层160与半导体元件150的关系而言，绝缘层160的厚度D160大于半导体元件150的厚度D150，并且绝缘层160包覆半导体元件150的上表面150a及侧面150b，以使半导体元件150的上表面150a被绝缘层160包覆并内埋于封装元件100的内部。
内埋于封装单元100内的半导体元件150可以通过第三导电柱133电连接到第二图案化线路层122。内埋于封装单元100内的半导体元件150更可以通过第三导电柱133、第二图案化线路层122、第二导电柱132及第一导电柱131电连接到第一图案化线路层121。
其中，虽然第一导电柱131及第二导电柱132位于同一直线上，但第一导电柱131及第二导电柱132分别于步骤S102及S106的两阶段步骤形成，而不是同时形成。因此，第一导电柱131的长度L131与第一导电柱131的最小宽度W131的比值(一般称为深宽比)可以缩减至10以下(甚至低于2)，第二导电柱132的长度L132与第二导电柱132的最小宽度W132的比值(一般称为深宽比)也可以缩减至10以下(甚至低于2)。在深宽比大幅缩减的情况下，电镀制作工艺变得容易许多，良率也提高许多。
就第一导电柱131、第二导电柱132、第三导电柱133与半导体元件150的关系而言，第一导电柱131及第二导电柱132位于半导体元件150的外围，第三导电柱133的位置则与半导体元件150的位置重叠。并且，第二导电柱132的长度L132大于半导体元件150的厚度D150。
另外，就半导体元件150与基板110的关系而言，半导体元件150设置于基板110之外，而不是设置于基板110的任何凹槽内。
接着，请参照图4，其绘示第一实施例的封装单元100的堆叠结构1000的示意图。位于上方的封装单元100的第一图案化线路121设置于位于下方的封装单元100的导电凸块171上，使得两个封装单元100可以通过导电凸块170上下堆叠成一堆叠结构1000。依此类推，两个以上的封装单元100均可上下堆叠成堆叠结构1000。
第二实施例
请参照图5及图6A～图6H，图5绘示第二实施例的封装单元200(完整的封装单元绘示于图6G)的制造方法的流程图，图6A～图6H绘示图5的各步骤的流程图。本实施例的封装单元200的制造方法与第一实施例的封装单元100的制造方法不同之处在于本实施例的制造方法更包括步骤S203，并以步骤S207及S208取代步骤S107及S108，其余相同之处不再重复叙述。此外，如图6G所示，本实施例的封装单元200与第一实施例的封装单元100不同之处在于本实施例的封装单元200更包括一介金属层280，其余相同之处不再重复叙述。
如图6A所示，在步骤S101及S102之后，进入步骤S203。在步骤S203中，形成第一金属材料281于第一导电柱131上。其中，本实施例的第一金属材料281的材质包括锡。
接着，如图6B～图6F所示，进入步骤S104、S105及S106。在步骤S106中，第二导电柱132形成于第一金属材料281上。
然后，如图6G所示，在步骤S207及步骤S208中，形成第二金属材料(第二金属材料为制作工艺中的半成品，未绘示于图6G中)于第二图案化线路122的第二接垫122a上，并回焊第一金属材料281(绘示于图6A～图6F)及第二金属材料(未绘示)，以使第一金属材料281回焊为介金属层280，并使第二金属材料(未绘示)回焊为导电凸块170。其中本实施例的第一金属材料281(绘示于图6A～图6F)的材质包含锡，而第一导电柱131及第二导电柱132的材质皆包含铜。相互接触的锡与铜经过回焊后，将会产生化学变化而形成Cu6Sn5或Cu3Sn等锡-铜介金属化合物。所以，第一导电柱131及第二导电柱132在回焊后将通过介金属层280来连结而大幅提升连接强度。
接着，请参照图7，其绘示第二实施例的封装单元200的堆叠结构2000的示意图。如同第一实施例，本实施例的两个封装单元200也可以通过导电凸块170上下堆叠成一堆叠结构200。依此类推，两个以上的封装单元200均可上下堆叠成堆叠结构2000。
综上所述，虽然结合以上较佳实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (15)

1.一种封装单元，至少包括：
基板；
第一图案化线路层，位于该基板的一表面；
第一导电柱，贯穿该基板，并连接该第一图案化线路层；
半导体元件，设置于该基板上，该半导体元件包括至少一芯片；
绝缘层，覆盖该半导体元件及该基板；
第二导电柱，贯穿该绝缘层，并电连接该第一导电柱；
第三导电柱，贯穿该绝缘层，并连接该半导体元件；
第二图案化线路层，位于该绝缘层上，并连接该第二导电柱及该第三导电柱；以及
导电凸块，设置于该第二图案化金属层上。
2.如权利要求1所述的封装单元，还至少包括：
介金属层，设置于该第一导电柱及该第二导电柱之间，该第一导电柱的材质及该第二导电柱的材质皆包含铜，该介金属层的材质包含锡-铜介金属化合物。
3.如权利要求1所述的封装单元，其中该第一导电柱及该第二导电柱位于同一直线上。
4.如权利要求1所述的封装单元，其中该第一导电柱及该第二导电柱位于该半导体元件的外围。
5.如权利要求1所述的封装单元，其中该第三导电柱的位置与该半导体元件的位置重叠。
6.如权利要求1所述的封装单元，其中该第二导电柱的长度大于该半导体元件的厚度。
7.如权利要求1所述的封装单元，其中该绝缘层的厚度大于该半导体元件的厚度。
8.如权利要求1项所述的封装单元，其中该半导体元件设置于该基板之外。
9.如权利要求1所述的封装单元，其中该绝缘层至少包覆该半导体元件的一上表面及一侧面。
10.一种封装单元的堆叠结构，至少包括：
至少两个封装单元，各该封装单元至少包括：
基板；
第一图案化线路层，位于该基板的一表面；
第一导电柱，贯穿该基板，并连接该第一图案化线路层；
半导体元件，设置于该基板上，该半导体元件包括至少一芯片；
绝缘层，覆盖该半导体元件及该基板；
第二导电柱，贯穿该绝缘层，并电连接该第一导电柱；
第三导电柱，贯穿该绝缘层，并连接该半导体元件；
第二图案化线路层，位于该绝缘层上，并连接该第二导电柱及该第三导电柱；及
导电凸块，设置于该第二图案化金属层上；
其中，该些封装单元的其中之一的该第一图案化线路设置于该些封装单元的其中之另一的该导电凸块上。
11.一种封装单元的制造方法，至少包括：
提供一基板；
形成一第一图案化线路层及一第一导电柱，该第一图案化线路层设置于该基板的一表面，该第一导电柱贯穿该基板并连接该第一图案线路层；
设置一半导体元件于该基板上，该半导体元件包括至少一芯片；
形成一绝缘层于该半导体元件及该基板上；以及
形成一第二导电柱、一第三导电柱及一第二图案化线路，该第二导电柱贯穿该绝缘层并电连接该第一导电柱，该第三导电柱贯穿该绝缘层并连接该半导体元件，该第二图案化线路层设置于该绝缘层上并连接该第二导电柱及该第三导电柱。
12.如权利要求11所述的封装单元的制造方法，还至少包括：
形成一第一金属材料于该第一导电柱上，其中在形成该第二导电柱的步骤中，该第二导电柱形成于该第一金属材料上，且该第一导电柱的材质及该第二导电柱的材质皆包含铜，该第一金属材料的材质包含锡。
13.如权利要求12所述的封装单元的制造方法，还至少包括：
形成一第二金属材料于该第二图案化线路上；以及
回焊该第一金属材料及该第二金属材料，以使该第一金属材料回焊为一介金属层，并使该第二金属材料回焊为一导电凸块。
14.如权利要求13所述的封装单元的制造方法，其中第一导电柱及该第二导电柱的材质包含铜，该第一金属材料的材质包含锡，该介电金属层的材质包含锡-铜介金属化合物。
15.如权利要求11所述的封装单元的制造方法，其中形成该绝缘层、该第二导电柱、该第三导电柱及该第二图案化线路的该些步骤执行于形成该第一图案化线路及该第一导电柱的该些步骤之后。
CN2011102629245A 2010-10-13 2011-09-07 封装单元及其堆叠结构与制造方法 Pending CN102446884A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766844A (zh) * 2014-01-07 2015-07-08 日月光半导体制造股份有限公司 半导体结构及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150053775A (ko) * 2012-09-07 2015-05-18 어플라이드 머티어리얼스, 인코포레이티드 얇은 기판들을 위한 포터블 정전 척 캐리어
TWI609468B (zh) 2017-01-16 2017-12-21 欣興電子股份有限公司 封裝體裝置及其製造方法
CN114245597A (zh) * 2020-09-09 2022-03-25 鹏鼎控股(深圳)股份有限公司 内埋导电线路的线路板的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1714609A (zh) * 2002-11-27 2005-12-28 住友电木株式会社 电路板、多层布线板及其制造方法
US20060019484A1 (en) * 2004-07-23 2006-01-26 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US7671457B1 (en) * 2002-05-01 2010-03-02 Amkor Technology, Inc. Semiconductor package including top-surface terminals for mounting another semiconductor package
US20100127374A1 (en) * 2008-11-24 2010-05-27 Samsung Electronics Co., Ltd. Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
TWI221327B (en) * 2003-08-08 2004-09-21 Via Tech Inc Multi-chip package and process for forming the same
US7459781B2 (en) * 2003-12-03 2008-12-02 Wen-Kun Yang Fan out type wafer level package structure and method of the same
TWI225670B (en) * 2003-12-09 2004-12-21 Advanced Semiconductor Eng Packaging method of multi-chip module
KR100629498B1 (ko) * 2005-07-15 2006-09-28 삼성전자주식회사 마이크로 패키지, 멀티―스택 마이크로 패키지 및 이들의제조방법
US8174119B2 (en) * 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US20080136002A1 (en) * 2006-12-07 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
KR20100084684A (ko) * 2007-11-01 2010-07-27 다이니폰 인사츠 가부시키가이샤 부품 내장 배선판, 부품 내장 배선판의 제조 방법
TWI431755B (zh) * 2008-08-27 2014-03-21 Advanced Semiconductor Eng 堆疊式封裝構造及其基板製造方法
TW201019441A (en) * 2008-11-10 2010-05-16 Phoenix Prec Technology Corp Package substrate and package structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671457B1 (en) * 2002-05-01 2010-03-02 Amkor Technology, Inc. Semiconductor package including top-surface terminals for mounting another semiconductor package
CN1714609A (zh) * 2002-11-27 2005-12-28 住友电木株式会社 电路板、多层布线板及其制造方法
US20060019484A1 (en) * 2004-07-23 2006-01-26 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US20100127374A1 (en) * 2008-11-24 2010-05-27 Samsung Electronics Co., Ltd. Multi-stack semiconductor package, semiconductor module and electronic signal processing system including thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766844A (zh) * 2014-01-07 2015-07-08 日月光半导体制造股份有限公司 半导体结构及其制造方法
CN104766844B (zh) * 2014-01-07 2017-12-19 日月光半导体制造股份有限公司 半导体结构及其制造方法

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