CN102446769A - 一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法 - Google Patents

一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法 Download PDF

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CN102446769A
CN102446769A CN201110265267XA CN201110265267A CN102446769A CN 102446769 A CN102446769 A CN 102446769A CN 201110265267X A CN201110265267X A CN 201110265267XA CN 201110265267 A CN201110265267 A CN 201110265267A CN 102446769 A CN102446769 A CN 102446769A
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俞柳江
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Abstract

本发明公开了一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法，包括：在MOS器件已形成的栅极上沉积第一硅化物掩膜并刻蚀形成栅极侧壁的第一侧墙；进行P型重掺杂硼注入以及热退火处理，使得多晶硅栅的电阻得以降低；移除第一侧墙，进行轻掺杂漏极工艺，同时进行碳离子辅助注入，在栅极下方的基体与源漏极区域的交界处形成超浅结；在栅极上再次沉积第二硅化物掩模，刻蚀后形成第二侧墙；在MOS器件表面形成自对准硅化物。本发明通过调整碳辅助注入工艺流程的工艺顺序，将P型重掺杂硼注入工艺，提前到轻掺杂漏极工艺之前，从而防止了由于碳注入引起的P型多晶硅栅中，P型重掺杂硼原子不能充分扩散的问题，降低了P型多晶硅栅的电阻。

Description

一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法
技术领域
本发明涉及半导体制备技术领域，尤其涉及一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法。
背景技术
在半导体器件的制备工艺过程中，芯片是批量进行处理的，在同一晶圆上形成大量复杂器件，随着超大规模集成电路的迅速发展，在芯片的集成度越来越高的同时，芯片尺寸也愈来愈小。
当MOS管沟道缩短到一定程度，就会出现短沟道效应（Short Channel Effects）。沟道长度减小到一定程度后，源、漏结的耗尽区在整个沟道中所占的比重增大，栅下面的硅表面形成反型层所需的电荷量减小，因而阈值电压（Vt）减小，同时截止电流（Ioff）上升，短沟道效应使得器件的阈值电压对沟道的长度变化非常敏感，使得半导体器件工艺上的控制难度加大。
在65纳米以下的半导体工艺技术中，通常会采用超浅结（Ultra-Shallow Junction）工艺来降低CMOS器件的短沟道效应，对于PMOS器件，由于轻掺杂漏极工艺（Lightly Doped Drain，缩写为LDD）中采用的是低能量硼离子注入工艺，为了降低硼原子在硅衬底中的扩散，实现超浅结，可以在LDD注入的时候，采用碳辅助注入（Carbon Co-implantation）工艺，由于碳原子可以降低硼原子在硅衬底中的扩散，所以碳辅助注入工艺有利于形成超浅结。
但是，由于在进行LDD注入的时候，多晶硅栅同样会进行碳辅助注入，在之后进行的P型重掺杂硼注入（P Plus Implantation）以及热退火工艺中，LDD注入的碳原子，同样会降低P型重掺杂注入的硼原子在多晶硅栅中的扩散行为，其结果会导致多晶硅栅中的硼原子不能充分扩散，P型多晶硅栅的电阻偏大。
发明内容
针对上述存在的问题，本发明的目的是提供一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法，通过调整碳辅助注入工艺流程，防止注入的碳对P型重掺杂注入硼原子的扩散的抑制作用，使得重掺杂注入的硼原子在多晶硅栅中得到充分扩散，从而降低多晶硅栅的电阻。
本发明的目的是通过下述技术方案实现的：
一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其中，包括下列步骤：
在MOS器件已形成的栅极上沉积第一硅化物掩膜，刻蚀第一硅化物掩膜，形成MOS器件栅极侧壁的第一侧墙；
进行P型重掺杂硼注入以及热退火处理，使得多晶硅栅的电阻得以降低；
移除第一侧墙，进行轻掺杂漏极工艺，同时进行碳离子辅助注入，在栅极下方的基体与源漏极区域的交界处形成超浅结；
在栅极上再次沉积第二硅化物掩模，刻蚀后形成第二侧墙；
自对准硅化物工艺，在MOS器件表面形成自对准硅化物。
上述降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其中，所述在MOS器件已形成的栅极上沉积的第一硅化物掩膜为SiN。
上述降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其中，所述轻掺杂漏极工艺为采用低能量硼离子注入工艺。
上述降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其中，所述刻蚀硅化物掩膜形成所述第一侧墙和所述第二侧墙均采用干法刻蚀。
与已有技术相比，本发明的有益效果在于：本发明通过调整碳辅助注入工艺流程的工艺顺序，将P型重掺杂硼注入工艺，提前到轻掺杂漏极工艺之前，从而防止了由于碳注入引起的P型多晶硅栅中，P型重掺杂硼原子不能充分扩散的问题，降低了P型多晶硅栅的电阻。
附图说明
图1是本发明降低碳辅助注入工艺流程中多晶硅栅电阻的方法的流程示意框图；
图2a~图2e是本发明降低碳辅助注入工艺流程中多晶硅栅电阻的方法各个流程步骤的效果示意图。
具体实施方式
下面结合原理图和具体操作实施例对本发明作进一步说明。
本发明降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其中，如图1所示，包括下列步骤：
在MOS器件已形成的栅极上沉积第一硅化物掩膜，刻蚀第一硅化物掩膜，形成MOS器件栅极侧壁的第一侧墙1，完成后效果示意如图2a所示；
如图2b所示，进行P型重掺杂硼注入以及热退火处理，由于没有碳原子存在，多晶硅栅中的硼原子得以充分扩散；
如图2c所示，移除第一侧墙1后，进行轻掺杂漏极工艺（LDD），同时进行碳离子辅助注入，由于碳原子的存在，抑制了LDD注入的硼原子的扩散，在栅极下方的基体，即衬底与源漏极区域的交界处形成超浅结。但多晶硅栅中的重掺杂硼原子，由于在之前的退火工艺中已经充分扩散，所以不会受辅助注入碳的影响，因此，多晶硅栅的电阻得以降低；
如图2d所示，在栅极上再次沉积第二硅化物掩模，刻蚀后形成第二侧墙2；
如图2e所示，进行自对准硅化物工艺，在MOS器件表面形成自对准硅化物3。
进一步地，在MOS器件已形成的栅极上沉积的第一硅化物掩膜为SiN。
进一步地，轻掺杂漏极工艺为采用低能量硼离子注入工艺。
进一步地，刻蚀硅化物掩膜形成第一侧墙1和第二侧墙2均是采用干法刻蚀。
综上，本发明降低碳辅助注入工艺流程中多晶硅栅电阻的方法可以有效防止由于碳注入引起的P型多晶硅栅中，P型重掺杂硼原子不能充分扩散的问题，降低了P型多晶硅栅的电阻，比如，在55纳米工艺中，改进后的工艺使得P型多晶硅栅电阻的电阻值从相对较高的700欧姆/方，减小到300欧姆/方。
以上对本发明的具体实施例进行了详细描述，但本发明并不限制于以上描述的具体实施例，其只是作为范例。对于本领域技术人员而言，任何对该降低碳辅助注入工艺流程中多晶硅栅电阻的方法进行的等同修改和替代也都在本发明的范畴之中。因此，在不脱离本发明的精神和范围下所作出的均等变换和修改，都应涵盖在本发明的范围内。

Claims (4)

1.一种降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其特征在于，包括下列步骤：
在MOS器件已形成的栅极上沉积第一硅化物掩膜，刻蚀第一硅化物掩膜，形成MOS器件栅极侧壁的第一侧墙；
进行P型重掺杂硼注入以及热退火处理，使得多晶硅栅的电阻得以降低；
移除第一侧墙，进行轻掺杂漏极工艺，同时进行碳离子辅助注入，在栅极下方的基体与源漏极区域的交界处形成超浅结；
在栅极上再次沉积第二硅化物掩模，刻蚀后形成第二侧墙；
自对准硅化物工艺，在MOS器件表面形成自对准硅化物。
2.根据权利要求1所述的降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其特征在于，所述在MOS器件已形成的栅极上沉积的第一硅化物掩膜为SiN。
3.根据权利要求1所述的降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其特征在于，所述轻掺杂漏极工艺为采用低能量硼离子注入工艺。
4.根据权利要求1所述的降低碳辅助注入工艺流程中多晶硅栅电阻的方法，其特征在于，所述刻蚀硅化物掩膜形成所述第一侧墙和所述第二侧墙均采用干法刻蚀。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990142A (zh) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
CN108695240A (zh) * 2017-04-07 2018-10-23 台湾积体电路制造股份有限公司 低阻抗接触窗插塞的形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577222A (zh) * 2008-05-05 2009-11-11 中芯国际集成电路制造(北京)有限公司 掺杂方法及ldd掺杂区的形成方法
CN101661886A (zh) * 2008-08-25 2010-03-03 上海华虹Nec电子有限公司 半导体制备中源漏注入结构的制备方法
CN101996885A (zh) * 2009-08-11 2011-03-30 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
US20110111571A1 (en) * 2009-11-11 2011-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for obtaining quality ultra-shallow doped regions and device having same
CN102097379A (zh) * 2009-12-10 2011-06-15 中芯国际集成电路制造(上海)有限公司 制造半导体器件层的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5998272A (en) * 1996-11-12 1999-12-07 Advanced Micro Devices, Inc. Silicidation and deep source-drain formation prior to source-drain extension formation
US6518136B2 (en) * 2000-12-14 2003-02-11 International Business Machines Corporation Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication
US6777298B2 (en) * 2002-06-14 2004-08-17 International Business Machines Corporation Elevated source drain disposable spacer CMOS
CN101621006B (zh) * 2008-07-03 2011-01-12 中芯国际集成电路制造(上海)有限公司 利用锗预非晶处理来形成p-型轻度掺杂的漏极区的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101577222A (zh) * 2008-05-05 2009-11-11 中芯国际集成电路制造(北京)有限公司 掺杂方法及ldd掺杂区的形成方法
CN101661886A (zh) * 2008-08-25 2010-03-03 上海华虹Nec电子有限公司 半导体制备中源漏注入结构的制备方法
CN101996885A (zh) * 2009-08-11 2011-03-30 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
US20110111571A1 (en) * 2009-11-11 2011-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method for obtaining quality ultra-shallow doped regions and device having same
CN102097379A (zh) * 2009-12-10 2011-06-15 中芯国际集成电路制造(上海)有限公司 制造半导体器件层的方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990142A (zh) * 2015-02-03 2016-10-05 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其制作方法
CN108695240A (zh) * 2017-04-07 2018-10-23 台湾积体电路制造股份有限公司 低阻抗接触窗插塞的形成方法
CN108695240B (zh) * 2017-04-07 2020-12-01 台湾积体电路制造股份有限公司 低阻抗接触窗插塞的形成方法

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