CN102420524A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN102420524A
CN102420524A CN2011102835172A CN201110283517A CN102420524A CN 102420524 A CN102420524 A CN 102420524A CN 2011102835172 A CN2011102835172 A CN 2011102835172A CN 201110283517 A CN201110283517 A CN 201110283517A CN 102420524 A CN102420524 A CN 102420524A
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松冈彻
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Mitsubishi Electric Corp
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Abstract

本发明提供能够低成本地在用户侧选择期望的电路(降压电路(或升降压电路)和升压电路)的半导体装置。在本发明涉及的半导体装置中，具备二极管元件(10)和开关元件(IGBT)(20)。二极管元件(10)的正极端子(T2)和开关元件(20)的一个主电极端子(T1)隔开既定距离而邻接地配设。另外，二极管元件(10)的负极端子(T4)和开关元件(20)的另一个主电极端子(T3)隔开既定距离而邻接地配设。

Description

半导体装置
技术领域
本发明涉及半导体装置，例如涉及能形成斩波电路(choppercircuit)的半导体装置。
背景技术
一直以来，作为DC-DC变换电路，存在降压电路、升压电路及升降压电路。降压电路、升压电路及升降压电路各自是包含二极管元件和作为开关元件的IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极性晶体管)的电路结构。
降压电路及升降压电路包含例如二极管元件的负极端子和IGBT的发射极端子相连接的结构(第一类型电路：参照图2)。另一方面，升压电路包含例如二极管元件的正极端子和IGBT的集电极端子相连接的结构(第二类型电路：参照图3)。
此外，具有上述第一类型电路的斩波电路及具有上述第二类型电路的斩波电路，是众所周知的电路结构。例如，专利文献1公开了具有第一类型电路的升压斩波电路。与此相对，专利文献2公开了具有第二类型电路的降压斩波电路/升降压斩波电路。
专利文献1：日本特开平11-113253号公报
专利文献2：日本特开平09-322531号公报
发明内容
然而，在以往需要根据使用用途准备具有第一类型电路的半导体装置和具有第二类型电路的半导体装置。因而，需要准备两种半导体装置，因此需要配设较多电路元件，导致成本升高。另外，在用户侧，希望能够根据该用户的要求简便地进行降压电路(或升降压电路)和升压电路的选择。
因此，本发明的目的在于，提供一种能够以低成本在用户侧选择期望的电路(降压电路(或升降压电路)和升压电路)的半导体装置。
为了达到上述目的，本发明涉及的半导体装置具备：外壳；二极管元件，个别地配设于所述外壳内；开关元件，个别地配设于所述外壳内；正极端子，配设于所述外壳外，并与所述二极管元件的正极电极电连接；一个主电极端子，配设于所述外壳外，并与开关元件的一个主电极电连接；负极端子，配设于所述外壳外，并与所述二极管元件的负极电极电连接；以及另一个主电极端子，配设于所述外壳外，并与所述开关元件的另一个主电极电连接。所述正极端子和所述一个主电极端子隔开既定距离而邻接地配设，所述负极端子和所述另一个主电极端子隔开既定距离而邻接地配设。
本发明具备：外壳；二极管元件，个别地配设于所述外壳内；开关元件，个别地配设于所述外壳内；正极端子，配置于所述外壳外，并与所述二极管元件的正极电极电连接；一个主电极端子，配设于所述外壳外，并与开关元件的一个主电极电连接；负极端子，配设于所述外壳外，并与所述二极管元件的负极电极电连接；以及另一个主电极端子，配设于所述外壳外，并与所述开关元件的另一个主电极电连接。所述正极端子和所述一个主电极端子隔开既定距离而邻接地配设，所述负极端子和所述另一个主电极端子隔开既定距离而邻接地配设。
因而，能够在半导体装置简便且低成本地形成用户侧负担有所减轻的、与用户的用途相应的斩波电路。
附图说明
图1是示出本发明涉及的半导体装置的重点结构的电路图。
图2是示出用IGBT作为半导体开关器件的情况下的升压斩波电路的主要结构的电路图。
图3是示出用IGBT作为半导体开关器件的情况下的降压/升降压斩波电路的主要结构的电路图。
图4是示出用双极晶体管作为半导体开关器件的情况下的升压斩波电路的主要结构的电路图。
图5是示出用双极晶体管作为半导体开关器件的情况下的降压/升降压斩波电路的主要结构的电路图。
图6是示出用MOSFET作为半导体开关器件的情况下的升压斩波电路的主要结构的电路图。
图7是示出用MOSFET作为半导体开关器件的情况下的降压/升降压斩波电路的主要结构的电路图。
标号说明：
1外壳；10二极管元件；20开关元件(IGBT)；30续流二极管；T1、T2、T3、T4端子。
具体实施方式
以下基于示出其实施方式的附图，对本发明进行具体说明。
图1是示出本发明涉及的半导体装置的重点结构的电路图。如图1所示，半导体装置包含外壳1，在电路配设工序中，在该外壳1内至少配设二极管元件10和作为开关元件20的IGBT20。另外，在该电路配设工序中，在外壳1外至少配设端子T1、T2、T3、T4。这里，如图1所示，二极管元件10及开关元件20各自作为个别元件而配设。
在二极管元件10的正极侧(正极电极侧)电连接端子T2，在二极管元件10的负极侧(负极电极侧)电连接端子T4。与该正极电极电连接的外部端子T2被视为正极端子。另一方面，与该负极电极电连接的外部端子T4被视为负极端子。
另一方面，在IGBT20的集电极侧(集电极电极侧)电连接端子T1，在IGBT20的发射极侧(发射极电极侧)电连接端子T3。端子T1能够视为与集电极电极电连接的一个主电极端子，端子T3能够视为与发射极电极侧电连接的另一个主电极端子。
在上述电路配设工序后，如图1所示，在外壳1内并排设有二极管元件10和IGBT20(沿图1的上下方向并排配设)。具体而言，二极管元件10和IGBT20在俯视下隔开既定间隔而并行。换言之，在外壳1内配设有二极管元件10和IGBT20，使得经由二极管元件10在端子T2-端子T4之间流动的电流的方向、和经由IGBT20在端子T1-端子T3之间流动的电流的方向是平行的(两个方向都是图1的左右方向)。
如图1所示，端子T2和端子T1在图1的上下方向中隔开既定距离而邻接地配设于基板1外。另外，端子T4和端子T3在图1的上下方向中隔开所述既定距离而邻接地配设于外壳1外。例如，端子T2的中心和端子T1的中心的距离、及端子T4的中心和端子T3的中心的距离为2～3cm左右。另外，端子T2的中心和端子T4的中心的距离、及端子T1的中心和端子T3的中心的距离为8～9cm左右。
另外，端子T1、T2一同配设于外壳1的一端的边缘部(图1的外壳1的左侧的一边)，端子T3、T4一同配设于与外壳1的一端的边缘部相向的另一端的边缘部(图1的外壳1的右侧的一边)。
此外，在外壳1内也实施其他布线处理等。例如，与IGBT20并列地配设续流二极管(flywheel diode)30，还在外壳1内实施IGBT20的控制电极的布线。
于是，向用户侧供给具有如图1所示的结构的半导体装置，用户继续该半导体装置的制造，即执行与用户侧的用途相应的对该半导体装置的接线处理。
例如，在用户期望构成升压斩波电路的情况下，用户在图1所示的半导体装置中使用布线等电连接端子T1和端子T2。通过该连接处理，在半导体装置中形成具有图2所示的结构的升压斩波电路。
这里，在图2中，端子t1与接地(或负电位)侧连接，端子t3与输入(正电位)侧连接，端子t2是输出端子。
与此相对，在用户期望构成降压斩波电路/升降压斩波电路的情况下，用户在图1所示的半导体装置中使用布线等电连接端子T3和端子T4。通过该连接处理，在半导体装置中形成具有图3所示的结构的降压斩波电路/升降压斩波电路。
这里，在图3中，端子t11与接地(或负电位)侧连接，端子t13与输入(正电位)侧连接，端子t12是输出端子。
如以上那样，在本发明涉及的半导体装置中，如图1所示，并排地设有二极管元件10和开关元件(IGBT)20，且相邻配设端子T1和端子T2，并相邻配设端子T3和端子T4。
因而，仅通过电连接端子T1和端子T2的简单的操作，就能够在半导体装置中形成具有图2所示的结构的升压斩波电路。另一方面，仅通过电连接端子T3和端子T4的简单的操作，就能够在半导体装置中形成具有图3所示的结构的降压斩波电路/升降压斩波电路。即，能够在半导体装置简单且低成本地形成用户侧负担有所减轻的、与用户的用途相应的斩波电路。
此外，通过选择性切换端子T1和端子T2的电连接、以及端子T3和端子T4的电连接，用户能够简便地进行升压斩波电路和降压斩波电路/升降压斩波电路的选择性切换。即，能够在图1所示的半导体装置简单且低成本地选择性切换并形成用户侧负担有所减轻的、与用户的用途相应的斩波电路。
此外，在上述内容中，举出IGBT作为开关元件20的一个例子。然而，也可以采用双极晶体管或MOSFET(Metal Oxide Semiconductor-Field Effect Transistor：金属氧化物半导体场效应晶体管)作为相对二极管元件10并排设置的开关元件20。
这里，在图1中，在采用双极晶体管作为开关元件20的情况下，将二极管元件10的端子(正极端子)T2与如图1所示那样和该端子T2相邻的端子(双极晶体管的集电极端子)T1连接。通过该连接，在半导体装置中形成包含图4所示的结构的升压斩波电路。
这里，在图4中，端子t1与接地(或负电位)侧连接，端子t3与输入(正电位)侧连接，端子t2是输出端子。
另外，在图1中，在采用双极晶体管作为开关元件20的情况下，将二极管元件10的端子(负极端子)T4与如图1所示那样和端子T4相邻的端子(双极晶体管的发射极端子)T3连接。通过该连接，在半导体装置中形成包含如图5所示的结构的降压斩波电路/升降压斩波电路。
这里，在图5中，端子t11与接地(或负电位)侧连接，端子t13与输入(正电位)侧连接，端子t12是输出端子。
另外，在图1中，在采用MOSFET作为开关元件的情况下，将二极管元件10的端子(正极端子)T2与如图1所示那样和端子T2相邻的端子(MOSFET的漏极端子)T1连接。通过该连接，在半导体装置中形成包含图6所示的结构的升压斩波电路。
这里，在图6中，端子t1与接地(或负电位)侧连接，端子t3与输入(正电位)侧连接，端子t2是输出端子。
另外，在图1中，在采用MOSFET作为开关元件的情况下，将二极管元件10的端子(负极端子)T4与如图1所示那样和端子T1相邻的端子(MOSFET的源极端子)T3连接。通过该连接，在半导体装置中形成包含图7所示的结构的降压斩波电路/升降压斩波电路。
这里，在图7中，端子t11与接地(或负电位)侧连接，端子t13与输入(正电位)侧连接，端子t12是输出端子。

Claims (4)

1.一种半导体装置，其特征在于，包括：
外壳；
二极管元件，个别地配设于所述外壳内；
开关元件，个别地配设于所述外壳内；
正极端子，配设于所述外壳外，并与所述二极管元件的正极电极电连接；
一个主电极端子，配设于所述外壳外，并与开关元件的一个主电极电连接；
负极端子，配设于所述外壳外，并与所述二极管元件的负极电极电连接；以及
另一个主电极端子，配设于所述外壳外，并与所述开关元件的另一个主电极电连接，
所述正极端子和所述一个主电极端子隔开既定距离而邻接地配设，
所述负极端子和所述另一个主电极端子隔开另一既定距离而邻接地配设。
2.根据权利要求1所述的半导体装置，其特征在于，
在所述外壳的一端的边缘部配设有所述正极端子和所述一个主电极端子，
在与所述一端的边缘部相向的、所述外壳的另一端的边缘部，配设有所述负极端子和所述另一个主电极端子。
3.根据权利要求1所述的半导体装置，其特征在于，
所述开关元件是双极晶体管或绝缘栅双极性晶体管，
所述一个主电极端子是集电极端子，
所述另一个主电极端子是发射极端子。
4.根据权利要求1所述的半导体装置，其特征在于，
所述开关元件是金属氧化物半导体场效应晶体管，
所述一个主电极端子是漏极端子，
所述另一个主电极端子是源极端子。
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