CN102386159B - 具有柔性的连接装置的功率组件 - Google Patents

具有柔性的连接装置的功率组件 Download PDF

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CN102386159B
CN102386159B CN201110251416.7A CN201110251416A CN102386159B CN 102386159 B CN102386159 B CN 102386159B CN 201110251416 A CN201110251416 A CN 201110251416A CN 102386159 B CN102386159 B CN 102386159B
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film
contact
point
making surface
semiconductor component
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CN102386159A (zh
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汤姆斯·施托克迈尔
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Semikron GmbH and Co KG
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Abstract

一种具有柔性的连接装置的功率组件，具有衬底、至少一个第一和第二功率半导体构件和连接装置，衬底具有用于布置功率半导体构件的导体轨迹。功率半导体构件具有第一接触面，而连接装置由导电膜和绝缘膜的层序组成，这些膜本身结构化以便构成分膜。第一导电膜的第一分膜具有第一接触面，第一接触面与功率半导体构件的第一主面所配属的第一接触面直接机械连接。分膜与第二导电膜的第二分膜借助镀通孔穿过在其间布置的绝缘膜导电连接。第二功率半导体构件的第一接触面与第二分膜导电连接，和/或衬底的与第一导体轨迹电绝缘的第二导体轨迹的第二接触面机械间接或直接与第二分膜导电地连接并通过该第二分膜与第一功率半导体构件的第一接触面导电连接。

Description

具有柔性的连接装置的功率组件
技术领域
本发明涉及一种功率组件，如同从功率半导体模块中所公知的那样并在那里形成例如半桥电路的功能单元。这种功率组件由具有功率半导体构件和必要的连接元件的衬底构成。基本上这些连接元件被公知为打线接合连接件。
背景技术
作为这种打线接合连接件的至少部分、但是优选全部的替代品，例如由DE102007006706A1公开了机械的柔性的连接装置，该连接装置由导电的膜和绝缘的膜所制成的膜复合物组成。这里优选，导电的膜本身是结构化的并由此构成分膜，由此为所要实现的连接拓扑结构实现了必要的灵活性。但这种设计方案的缺点是，例如DE102007044620A1中所公开的那样，连接装置与衬底之间部分必需有电绝缘的填料。
发明内容
本发明的任务在于，提供一种被公知的功率组件，其中连接装置如下地改进，从而使得连接装置与衬底之间的电绝缘填料的局部的设计，特别在功率半导体构件的边缘区域内可以被取消。
该任务依据本发明通过依据权利要求1的功率组件得以实现。优选的实施方式在从属权利要求中予以说明。
本发明的出发点是一种功率半导体模块，其由壳体、外部的接线元件和至少一个功能功率组件组成。该功率组件具有衬底、至少一个第一和第二功率半导体构件和至少一个机械柔性的连接装置。衬底在它那方面具有第一主面，该第一主面包括多个彼此电绝缘的第一和第二导体轨迹用于依据电路布置功率半导体构件。这些功率半导体构件优选与在朝向衬底的主面上的第二接触面导电地并且机械地与那里的在第一接触面上的被配属的导体轨迹连接。在各个功率半导体构件的背离衬底的主面上分别布置至少一个第一接触面。
功率组件的柔性的连接装置由导电膜和至少一个电绝缘膜的交替的层序制成，由此基本上产生了由至少三个膜组成的堆叠。至少一个导电膜本身是结构化的以便构成分膜，由此，由在堆叠内获得从该膜留空的区域。
依据本发明，第一导电膜具有包括所配属的第一接触面的至少一个第一分膜，该第一接触面机械直接地并且导电地与在所配属的功率半导体构件的第一主面上的所配属的第一接触面连接。在这里，第一导电膜的该第一分膜与第二导电膜的第二分膜借助至少一个第一镀通孔穿过在其间所布置的绝缘膜导电地连接。
该第一镀通孔优选布置在绝缘膜的与功率半导体构件的第一主面邻近的那些第一区段内，由此获得某种程度上由功率半导体构件的接触面、第一分膜的接触面、该第一分膜本身、镀通孔和第二分膜的一部分所组成的垂直层序。
此外优选的是，绝缘膜的第一区段在其水平扩展中在所有侧向上足够宽地叠盖各个功率半导体构件并由此相对于第二膜或至少一个第二分膜电绝缘。
与此相反优选的是，第一导电膜的第一分膜水平地扩展直至最大到所配属的功率半导体构件的边缘并由此水平地不叠盖功率半导体构件。在这种情况下，该第一分膜仅用作第二导电膜的连接辅助件，该第二导电膜然后在它那方面形成功率半导体构件的其它内部、或者还有外部的导电连接。此外，在该设计方案中有意义的是第一导电膜尽可能薄地构造，因为第一导电膜的载流能力在截面上相对于第二导电膜很少会发生故障。
此外，第二功率半导体构件的第一接触面同样借助第一分膜和第一镀通孔与第二分膜并由此与第一功率半导体构件的第一接触面导电地连接，由此两个功率半导体构件的第一主面、或在那里布置的接触面借助第二分膜产生导电连接。
作为对此的替代或补充，衬底的与第一导体轨迹电绝缘的第二导体轨迹的第二接触面间接地或直接地与第二分膜机械地连接，由此获得该第二接触面与功率半导体构件或功率半导体构件的第一接触面的导电的连接。在这里，直接的机械连接优选通过衬底的第二导体轨迹的第二接触面与第二导电膜的第二分膜的接触面的材料锁合的或力锁合的连接构成。
替代的间接机械连接在这里优选通过第一导电膜的第三分膜(400c)的材料锁合的或力锁合的连接构成，该第一导电膜借助第二镀通孔穿过绝缘膜与第二导电膜连接。
直接的机械连接因此被理解为两个连接伙伴的连接，这两个连接伙伴最大仅通过连接材料例如粘合材料彼此间隔。与此相反，间接的机械连接具有其它的布置在连接伙伴之间的部件。
附图说明
现借助依据图1-4的实施例对本发明的解决方案做进一步阐述。
图1示出半桥电路布置方案的电路图；
图2示出依据本发明的功率组件的第一设计方案的截面图；
图3示出该功率组件的俯视图；
图4示出依据本发明的功率组件第二设计方案的截面图。
具体实施方式
图1示出了半桥电路布置方案的电路图。该半桥电路由串联电路中的第一和第二功率开关组成，包括该串联电路的直流电压输入端和在该串联电路的中间接头上的交流电压输出端。典型的是，每个这种功率开关通过作为功率半导体构件3的多个包括反并联地连接的功率二极管的功率晶体管构成。
这种半桥电路布置方案形成了功率电子电路的具有重要意义的基本类型，实现了大量不同的功率半导体模块。依据本发明的功率组件包括例如刚好这种的、作为功率半导体模块的功能单元的半桥电路布置方案。不言而喻，依据本发明的功率组件并不局限于这种拓扑结构。
图2示出了依据本发明的功率组件第一设计方案的截面图。所示为具有第一22和第二24彼此电绝缘的导体轨迹的衬底2。在这种设计方案中，衬底2为了构成这种绝缘功能具有由绝缘材料例如绝缘陶瓷制成的基体20。此外，所示出功率半导体构件3a，在这里为具有两个主面30a、32以及布置在这些主面上的接触面310a、320的功率二极管。第二接触面320在这里与衬底2的第一导体轨迹22导电地并且机械地固定连接。
为了将布置在功率半导体构件3的背离衬底2的第一侧面上的第一接触面310a与第二导体轨迹24导电地连接，设置了连接装置4。该连接装置4在这里是具有第一40和第二44导电膜以及在其间布置的绝缘膜42的膜复合物。优选的是，为了获得该膜复合物4的机械的柔性，导电膜40、44具有的厚度在50μm和500μm之间并且绝缘膜42具有的厚度在10μm和100μm之间。
此外，在这里该膜复合物4的两个导电膜40、44本身是结构化的，以便将配属于这些导电膜的单个的分膜400a、440构造为这些导电膜的一部分。同样的，绝缘膜42可以是结构化的。由此，三个膜的复合体4仅是区段方式地完整地构成。例如，朝向衬底2的第一导电膜40构成了第一主面30a上方的，也就是与第一主面30a直接邻近并仅限于功率半导体构件3那里的第一接触面310a区域上的第一分膜400a。作为用于导电连接的连接技术，适用例如所有公知的材料锁合的连接，特别是也适用烧结连接。基本上同样可以应用力锁合的连接。
在该区域内，还设置有由膜复合物4的多个缺口组成的第一镀通孔48a，以便将第一导电膜40的第一分膜400a与第二导电膜44的第二分膜440导电连接。
该第二分膜440直接通过本身所配属的接触面444与第二导体轨迹24的接触面244导电地并且直接机械地连接。为了构成这种连接，材料锁合的或力锁合的连接技术同样适用。
作为用于直接的机械连接的替代方案，此外，显示了第二分膜440与衬底2的第二导体轨迹24的间接的机械连接。为此，连接装置4具有第一导电膜40的第三分膜400c，该第三分膜借助优选相同于第一镀通孔构成的第二镀通孔48b。该第三分膜400c不仅是出于经济制造的原因优选以相同的连接技术与第二导体轨迹24或第二导体轨迹的接触面244连接，正如第一分膜400a与功率半导体构件3的接触面310a连接那样。
基本上在功率组件的内部可行的是，第二分膜440与第二导体轨迹24既可以直接地，也可以间接地机械连接，这一点取决于位置要求和周围的组件可以任意地选取。例如，当第二导电膜44由于高载流能力必须特别厚地选择，因为由此连接装置4的机械柔性较小，在功率半导体构件3的接触位置与第二导体轨迹的距离非常小的情况下，可以优选间接连接。通过连接装置4引导的其它电位的类型和数量在特殊的应用情况下同样影响这种选取。
在两个导电膜40、44之间布置的绝缘膜42为此在第二分膜440与第二导体轨迹24的第二接触面244直接连接的区域内被留空。在功率半导体构件3的第一主面310a与第二导体轨迹24连接的区域内，绝缘层42由此在功率半导体构件3的边缘区域上，直至第二导体轨迹244与第二分膜440连接的边缘454叠盖功率半导体构件3。优选功率半导体构件3的这种叠盖通过绝缘膜42在边缘区域在所有侧向上进行。
这种设计方案的重要的优点基于，在这里，绝缘膜42用作第二分膜440与第一导体轨迹22的电绝缘部分并且由此可以取消使用用于构成这种绝缘部分的额外的装置。
图3以俯视图差异地示出刚才所描述的功率组件，在这里，功率晶体管被设置为功率半导体构件3a。该功率晶体管3a在其第一主面30a上具有两个第一接触面310a、312，其中，较大的第一接触面310a用于负载连接以及较小的第一接触面312用于控制连接。所示的衬底2具有三个导体轨迹22、24、26，其中，第一导体轨迹22和第二导体轨迹24用于负载电流引导以及另外的第二导体轨迹26用于引导控制电流。
第二导体轨迹24、26分别具有接触面244、246，用于与第二导电膜44的各个第二、但彼此电绝缘的分膜440、442直接机械地并且导电地连接。第二分膜440亦如图2中所示那样，将功率半导体构件3的负载接触面310a与第二导体轨迹24连接，而另外的第二分膜442则将功率半导体构件3的控制接触面312与另外的第二导体轨迹26连接。
第一导电膜40的各个第一分膜400a进而第一分膜所配属的接触面410a的在俯视图中的、与图2中的水平扩展对应的侧面扩展，在这里，分别小于功率半导体构件的所配属的接触面310a的侧面扩展。
但这里未示出的绝缘膜的在俯视图中与图2中的水平扩展对应的侧面扩展，在这种设计方案中，在所有侧向上在功率半导体构件3上一直达到第二导体轨迹24、26与第二分膜440、442之间的接触面244、444、246、446的各个边缘454、456。
图4以截面图示出依据本发明的功率组件的第二设计方案。在这里示出了两个相同的被并联连接的功率半导体构件3a/3b的导电连接，正如技术上实现半桥电路经常需要的那样。以相同的方式构成了功率晶体管和功率二极管的反并联电路。
在基本上与那些依据图2相同地构成的衬底2的共用第一导体轨迹22上，在这里，两个功率半导体构件3a/3b利用它们的第二接触面320进行布置并导电地连接。在第一主面30a/30b上的第一接触面310a/310b分别与第一导电膜40的第一分膜400a/400b连接，其中，依据本发明该第一导电膜40不构成在各个功率半导体构件3a/3b之间的导电连接。因此，用于构成这种连接足够的是，第一分膜400a/400b的水平扩展小于功率半导体构件3a/3b的水平扩展。此外，甚至优选第一分膜400a/400b的水平扩展小于各个功率半导体构件3a/3b的所配属的接触面310a/310b的水平扩展。
为了连接两个功率半导体构件3a/3b，每个第一分膜400a/400b借助第一镀通孔48a与第二导电膜44的共用第二分膜440导电地连接，由此，该第二分膜440也构成了功率半导体构件3a/3b之间的导电连接。
在这种设计方案中，与第二导电膜44相比，第一导电膜40也可以特别薄地构成，因为第一导电膜40在截面上无需具有高载流能力。因为绝缘膜42在适当选择的情况下典型的也可以非常薄地构成并且由此仅第二导电膜44是重要的，所以整个连接装置4具有高的机械的柔性。这种柔性在这里与已经提到的优点相配合，从而可以取消功率组件内部的额外的绝缘装置。
此外，详细地示出了第一镀通孔48a的构成，其中，有利的是依据图2的第二镀通孔48b以正是这样的方式构成。镀通孔48a由多个、优选大量的、对齐地穿过连接装置4的所有膜40、42、44的圆形缺口480组成。这些缺口480和导电膜40、44的整个暴露的表面由理想的统一厚度的金属化部482覆盖。该金属化部482的厚度有利地处于1μm的数量级。

Claims (10)

1.功率组件(1)，具有衬底(2)、至少一个第一功率半导体构件和至少一个第二功率半导体构件(3a/3b)以及至少一个机械柔性的连接装置(4)，
其中，所述衬底(2)具有第一主面，所述第一主面具有多个彼此绝缘的导体轨迹(22、24、26)用于依据电路布置所述功率半导体构件(3a/3b)，
其中，各个功率半导体构件(3a/3b)的分别背离所述衬底的第一主面(30)分别具有至少一个第一接触面(310a/310b、312)，
柔性的所述连接装置(4)由导电膜(40、44)和至少一个电绝缘膜(42)的交替层序制成并且至少一个导电膜(40、44)本身是结构化的以便构成分膜(400a/400b/400c、402、440、442)，
其中，第一导电膜(40)具有至少一个包括第一接触面(410a/410b、412)的第一分膜(400a/400b/400c、402)并且所述第一接触面导电地并且直接机械地与各个所述功率半导体构件(3)的第一主面(30a/30b)的所配属的第一接触面(310a/310b、312)连接，其中，
所述第一导电膜(40)的至少一个所述第一分膜(400a/400b、402)与第二导电膜(44)的第二分膜(440)借助至少一个第一镀通孔(48a)穿过在其间所布置的所述绝缘膜(42)导电地连接，以及
第二功率半导体构件(3b)的第一接触面(310b)同样与所述第二分膜(440)导电地连接并通过所述第二分膜与所述第一功率半导体构件(3a)的所述第一接触面(310a)导电地连接，和/或所述衬底(2)的与第一导体轨迹(22)电绝缘的第二导体轨迹(24、26)的第二接触面(244、246)机械地间接或直接与所述第二分膜导电地连接并通过所述第二分膜与所述第一功率半导体构件(3a)的第一接触面(310a)导电地连接。
2.根据权利要求1所述的功率组件，其中，所述第一导电膜(40)的第一分膜(400a/400b、402)的第一接触面(410a/410b、412)与各个功率半导体构件(3a/3b)的第一接触面(310a/310b、312)的直接机械的连接被构成为材料锁合的或力锁合的连接。
3.根据权利要求1所述的功率组件，其中，所述第二分膜(440、442)具有与所述第二导体轨迹(24、26)的第二接触面(244、246)导电地并且直接机械地连接的第二接触面(444、446)，所述第二分膜(440、442)的第二接触面(444、446)与所述衬底(2)的第二导体轨迹(24、26)的第二接触面(244、246)的直接机械的连接被构成为材料锁合的或力锁合的连接。
4.根据权利要求1所述的功率组件，其中，所述第二分膜(440、442)与所述衬底(2)的第二导体轨迹(24、26)的第二接触面(244、246)的间接机械的连接借助第二镀通孔(48b)穿过所述绝缘膜(42)到所述第一导电膜(40)的第三分膜(400c)构成，所述第三分膜(400c)与第二导体轨迹(24、26)的第二接触面(244、246)材料锁合地或力锁合地连接。
5.根据权利要求1所述的功率组件，其中，至少一个所述第一镀通孔(48a)布置在所述绝缘膜(42)的位于所述功率半导体构件(3a/3b)的第一主面(30a/30b)上方的第一区段中。
6.根据权利要求5所述的功率组件，其中，所述绝缘膜(42)的第一区段在所述第一区段的水平扩展中在所有侧向上叠盖各个功率半导体构件(3a/3b)。
7.根据权利要求6所述的功率组件，其中，所述绝缘膜(42)的第一区段一直达到所述第二导体轨迹(44)的第二接触面(444、446)的朝向所配属的所述功率半导体构件(3a/3b)的边缘(454、456)。
8.根据权利要求1所述的功率组件，其中，第一导电膜(40)的各个第一分膜(400a/400b、402)水平扩展最大至所配属的所述功率半导体构件的边缘并且由此水平地不叠盖所述功率半导体构件(3a/3b)。
9.根据权利要求1所述的功率组件，其中，所述导电膜(40、44)具有的厚度在50μm和500μm之间并且至少一个所述绝缘膜(42)具有的厚度在10μm和100μm之间。
10.根据权利要求9所述的功率组件，其中，所述第一导电膜(40)比所述第二导电膜(44)构造得更薄。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102011080153A1 (de) * 2011-07-29 2013-01-31 Infineon Technologies Ag Flexible verbindung von substraten in leistungshalbleitermodulen
DE102012218868B3 (de) * 2012-10-17 2013-11-07 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul
DE102013102828B4 (de) * 2013-03-20 2018-04-12 Semikron Elektronik Gmbh & Co. Kg Leistungsbaugruppe mit einer als Folienverbund ausgebildeten Verbindungseinrichtung
JP6274019B2 (ja) * 2014-06-03 2018-02-07 三菱電機株式会社 半導体装置及びその製造方法
EP3273470A1 (de) 2016-07-22 2018-01-24 SEMIKRON Elektronik GmbH & Co. KG Leistungselektronische schalteinrichtung, anordnung hiermit und verfahren zur herstellung der schalteinrichtung
EP3273474A1 (de) 2016-07-22 2018-01-24 SEMIKRON Elektronik GmbH & Co. KG Leistungselektronische schalteinrichtung, anordnung hiermit und verfahren zur herstellung der schalteinrichtung
EP3343600A1 (de) * 2016-12-28 2018-07-04 Siemens Aktiengesellschaft Halbleitermodul mit einem ersten und einem zweiten verbindungselement zum verbinden eines halbleiterchips sowie herstellungsverfahren
CN109545773B (zh) * 2018-11-21 2020-09-18 北京卫星制造厂有限公司 一种大功率芯片柔性互连模块及加工方法
DE102019112477B4 (de) * 2019-05-13 2024-03-14 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleiterbauelement mit einer Kontakteinrichtung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552255A (zh) * 2008-04-05 2009-10-07 赛米控电子股份有限公司 具有紧密密封的电路布置的功率半导体模块及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2382101A1 (fr) 1977-02-28 1978-09-22 Labo Electronique Physique Dispositif a semi-conducteur, comportant des pattes metalliques isolees
JPS61129835A (ja) * 1984-11-22 1986-06-17 Fujitsu Ltd 半導体装置
DE10121970B4 (de) * 2001-05-05 2004-05-27 Semikron Elektronik Gmbh Leistungshalbleitermodul in Druckkontaktierung
DE10355925B4 (de) 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und Verfahren seiner Herstellung
US7829386B2 (en) 2005-08-17 2010-11-09 General Electric Company Power semiconductor packaging method and structure
DE102007006706B4 (de) 2007-02-10 2011-05-26 Semikron Elektronik Gmbh & Co. Kg Schaltungsanordnung mit Verbindungseinrichtung sowie Herstellungsverfahren hierzu
JP5241177B2 (ja) * 2007-09-05 2013-07-17 株式会社オクテック 半導体装置及び半導体装置の製造方法
DE102007044620A1 (de) 2007-09-19 2009-04-16 Semikron Elektronik Gmbh & Co. Kg Anordnung mit einer Verbindungseinrichtung und mindestens einem Halbleiterbauelement
DE102007057346B3 (de) 2007-11-28 2009-06-10 Fachhochschule Kiel Laminierte Leistungselektronikbaugruppe
TW200945530A (en) * 2008-04-24 2009-11-01 Chipmos Technologies Inc Chip package structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552255A (zh) * 2008-04-05 2009-10-07 赛米控电子股份有限公司 具有紧密密封的电路布置的功率半导体模块及其制造方法

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