CN102339783B - 半导体装置的元件隔离结构及其形成方法 - Google Patents
半导体装置的元件隔离结构及其形成方法 Download PDFInfo
- Publication number
- CN102339783B CN102339783B CN201110208332.5A CN201110208332A CN102339783B CN 102339783 B CN102339783 B CN 102339783B CN 201110208332 A CN201110208332 A CN 201110208332A CN 102339783 B CN102339783 B CN 102339783B
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- Prior art keywords
- film
- hard mask
- deep trench
- shallow trench
- oxide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000000034 method Methods 0.000 title claims abstract description 93
- 238000002955 isolation Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 47
- 238000005229 chemical vapour deposition Methods 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 22
- 238000000926 separation method Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 26
- 239000011248 coating agent Substances 0.000 description 23
- 238000000576 coating method Methods 0.000 description 23
- 230000002950 deficient Effects 0.000 description 21
- 238000000151 deposition Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000000565 sealant Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 210000005069 ears Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (16)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2010-0070198 | 2010-07-20 | ||
KR1020100070198A KR101201903B1 (ko) | 2010-07-20 | 2010-07-20 | 반도체소자의 소자분리 구조 및 그 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102339783A CN102339783A (zh) | 2012-02-01 |
CN102339783B true CN102339783B (zh) | 2015-08-12 |
Family
ID=45492906
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110208332.5A Active CN102339783B (zh) | 2010-07-20 | 2011-07-20 | 半导体装置的元件隔离结构及其形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9396985B2 (zh) |
KR (1) | KR101201903B1 (zh) |
CN (1) | CN102339783B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9343538B2 (en) * | 2011-05-13 | 2016-05-17 | Richtek Technology Corporation | High voltage device with additional isolation region under gate and manufacturing method thereof |
CN103296039B (zh) * | 2013-01-14 | 2015-08-12 | 武汉新芯集成电路制造有限公司 | 一种背照式影像传感器深沟槽刻蚀方法 |
KR102398862B1 (ko) | 2015-05-13 | 2022-05-16 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
FR3060201B1 (fr) * | 2016-12-12 | 2019-05-17 | Aledia | Dispositif electronique comprenant une tranchee d'isolation electrique et son procede de fabrication |
US10879106B2 (en) * | 2018-02-21 | 2020-12-29 | Texas Instruments Incorporated | Apparatus with overlapping deep trench and shallow trench and method of fabricating the same with low defect density |
KR102633398B1 (ko) * | 2021-05-27 | 2024-02-06 | 에스케이키파운드리 주식회사 | 반도체 소자를 위한 딥 트렌치 마스크 레이아웃 설계 방법 |
CN117976607A (zh) * | 2024-03-27 | 2024-05-03 | 粤芯半导体技术股份有限公司 | 半导体器件的沟槽隔离制备方法以及半导体器件 |
Citations (2)
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US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
US6137152A (en) * | 1998-04-22 | 2000-10-24 | Texas Instruments - Acer Incorporated | Planarized deep-shallow trench isolation for CMOS/bipolar devices |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0018487B1 (en) * | 1979-03-22 | 1983-06-29 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JPH0665225B2 (ja) * | 1984-01-13 | 1994-08-22 | 株式会社東芝 | 半導体記憶装置の製造方法 |
US4579812A (en) * | 1984-02-03 | 1986-04-01 | Advanced Micro Devices, Inc. | Process for forming slots of different types in self-aligned relationship using a latent image mask |
FR2610141B1 (fr) * | 1987-01-26 | 1990-01-19 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit |
US6383899B1 (en) * | 1996-04-05 | 2002-05-07 | Sharp Laboratories Of America, Inc. | Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation |
US6187685B1 (en) * | 1997-08-01 | 2001-02-13 | Surface Technology Systems Limited | Method and apparatus for etching a substrate |
US6175147B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology Inc. | Device isolation for semiconductor devices |
US6144086A (en) * | 1999-04-30 | 2000-11-07 | International Business Machines Corporation | Structure for improved latch-up using dual depth STI with impurity implant |
KR100338766B1 (ko) * | 1999-05-20 | 2002-05-30 | 윤종용 | 티(t)형 소자분리막 형성방법을 이용한 엘리베이티드 샐리사이드 소오스/드레인 영역 형성방법 및 이를 이용한 반도체 소자 |
US6110797A (en) | 1999-12-06 | 2000-08-29 | National Semiconductor Corporation | Process for fabricating trench isolation structure for integrated circuits |
US6642607B2 (en) * | 2001-02-05 | 2003-11-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
DE10345346B4 (de) * | 2003-09-19 | 2010-09-16 | Atmel Automotive Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements mit aktiven Bereichen, die durch Isolationsstrukturen voneinander getrennt sind |
US7323379B2 (en) * | 2005-02-03 | 2008-01-29 | Mosys, Inc. | Fabrication process for increased capacitance in an embedded DRAM memory |
US7679130B2 (en) * | 2005-05-10 | 2010-03-16 | Infineon Technologies Ag | Deep trench isolation structures and methods of formation thereof |
US7648869B2 (en) * | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
US7491618B2 (en) * | 2006-01-26 | 2009-02-17 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
KR20070093535A (ko) | 2006-03-14 | 2007-09-19 | 주식회사 하이닉스반도체 | 반도체 소자의 제조 방법 |
KR101035595B1 (ko) | 2008-08-13 | 2011-05-19 | 매그나칩 반도체 유한회사 | 반도체장치의 트렌치 갭필 방법 |
CN101710575B (zh) | 2009-12-04 | 2015-05-20 | 上海集成电路研发中心有限公司 | 一种防止深沟绝缘工艺中产生空洞的方法 |
-
2010
- 2010-07-20 KR KR1020100070198A patent/KR101201903B1/ko active IP Right Grant
-
2011
- 2011-03-02 US US13/039,211 patent/US9396985B2/en active Active
- 2011-07-20 CN CN201110208332.5A patent/CN102339783B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472240A (en) * | 1981-08-21 | 1984-09-18 | Tokyo Shibaura Denki Kabushiki Kaisha | Method for manufacturing semiconductor device |
US6137152A (en) * | 1998-04-22 | 2000-10-24 | Texas Instruments - Acer Incorporated | Planarized deep-shallow trench isolation for CMOS/bipolar devices |
Also Published As
Publication number | Publication date |
---|---|
KR20120015368A (ko) | 2012-02-21 |
US9396985B2 (en) | 2016-07-19 |
US20120018840A1 (en) | 2012-01-26 |
CN102339783A (zh) | 2012-02-01 |
KR101201903B1 (ko) | 2012-11-16 |
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TR01 | Transfer of patent right |
Effective date of registration: 20201021 Address after: Han Guozhongqingbeidao Patentee after: Key Foundry Co.,Ltd. Address before: Cheongju Chungbuk Korea Patentee before: Magnachip Semiconductor, Ltd. |
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TR01 | Transfer of patent right | ||
CP03 | Change of name, title or address |
Address after: Republic of Korea Patentee after: Aisi Kaifang Semiconductor Co.,Ltd. Country or region after: Republic of Korea Address before: Han Guozhongqingbeidao Patentee before: Key Foundry Co.,Ltd. Country or region before: Republic of Korea |
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CP03 | Change of name, title or address |