CN102222611B - 闸栅极介电层的制造方法 - Google Patents

闸栅极介电层的制造方法 Download PDF

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CN102222611B
CN102222611B CN201010250775.6A CN201010250775A CN102222611B CN 102222611 B CN102222611 B CN 102222611B CN 201010250775 A CN201010250775 A CN 201010250775A CN 102222611 B CN102222611 B CN 102222611B
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layer
dielectric constant
oxygenous
high dielectric
dielectric layer
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CN102222611A (zh
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李威养
于雄飞
陈建豪
侯承浩
李达元
许光源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种栅极介电层的制造方法，该方法包含：形成一高介电常数介电层于一基材上；以原子层沉积工艺形成一含氧层于此高介电常数介电层上；及在此含氧层上进行一惰性等离子体处理。本发明可避免在基材顶部表面生成不欲形成的氧化硅，因此可保持装置效能特性。

Description

闸栅极介电层的制造方法
技术领域
本发明涉及集成电路制造，且尤其涉及一种具有栅极介电层的半导体装置。
背景技术
半导体集成电路(IC)产业已经历过快速的成长。IC材料和设计的技术进步使得IC的生产世代不停地推新，每个世代都较前个世代有更小及更复杂的电路。随着晶体管尺寸的微缩，栅极介电层厚度须随着栅极沟道长度的缩减而变薄，以维持效能。然而，为了降低栅极漏电流，需使用高介电常数栅极介电层作为未来先进节点所使用的栅极介电层，其可在维持相同的等效厚度下具有较厚的物理厚度。
图1A及图1B显示传统半导体装置100的高介电常数栅极介电层112在各种制造阶段的剖面图。图1A显示高介电常数栅极介电层112形成于基材102上。高介电常数栅极介电层112可使用原子层沉积(ALD)工艺形成。原子层沉积工艺包含连续的原子层沉积循环(ALD cycles)，其中每一循环包含导入金属源(source metal)以在基材102表面形成化学吸附层的步骤；净化剩余金属源的步骤；导入氧源化学品(oxygen source chemical)以在适当温度及压力下与化学吸附层反应形成部分的高介电常数栅极介电层的步骤：以及净化剩余氧源化学品的步骤。在沉积工艺后，空穴112a及两种化学品来源中的杂质112b即会嵌在高介电常数栅极介电层112中。
接着，在高介电常数栅极介电层112上进行含氧等离子体处理180(如图1B所示)。在含氧等离子体处理180的过程中，含氧等离子体中的氧自由基可穿透高介电常数栅极介电层112以填补及取代高介电常数栅极介电层112中的空穴112a及杂质112b。
然而，上述方法所面临的问题为，如氧自由基过多而穿透高介电常数栅极介电层112到达基材102的顶部表面，即会生成不欲形成的氧化硅于基材102顶部表面，因而使高介电常数栅极介电层112的等效厚度增加。因此，装置效能特性，例如临界电压，即会降低。
因此，业界需要的是一种制造无不欲形成的氧化硅的高介电常数栅极介电层的制造方法。
发明内容
为克服上述现有技术的缺陷，本发明提供一种高介电常数介电层的制造方法，包括：形成一高介电常数介电层于一基材上；以一原子层沉积工艺形成一含氧层于该高介电常数介电层上；以及于该含氧层上进行一惰性等离子体处理。
本发明也提供一种半导体装置的栅极介电层的制造方法，包括：以一第一原子层沉积工艺在一基材上形成一氧化铪层，作为一栅极介电层；以一第二原子层沉积工艺形成一不含金属元素的含氧层于该氧化铪层上；以及于该含氧层上进行一惰性等离子体工艺。
本发明可避免在基材顶部表面生成不欲形成的氧化硅，因此，可保持装置效能特性，例如临界电压。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下：
附图说明
图1A～图1B显示为传统半导体装置的高介电常数栅极介电层于各种制造阶段的剖面图。
图2显示为依照本发明实施例的高介电常数栅极介电层的制造方法的流程图。
图3A～图3H显示为依照本发明实施例的半导体装置于各种制造阶段的剖面图。
其中，附图标记说明如下：
100～半导体装置102～基材
112～高介电常数栅极介电层
112a～空穴112b～杂质
112c～氧化硅180～含氧等离子体处理
300～半导体装置302～基材
304～有源区306～隔离区域
312～高介电常数介电层
312a～空穴312b～杂质
314～含氧层316～虚置栅极电极层
322～轻掺杂源极/漏极区324～栅极间隔物
326～源极/漏极区328～接触蚀刻停止层
330～层间介电层332～开口
380～惰性等离子体处理
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本发明。这些为实施例并非用于限定本发明。此外，一第一元件形成于一第二元件“上方”、“之上”、“之下”或“上”可包含实施例中的该第一元件与第二元件直接接触，或也可包含该第一元件与第二元件之间更有其他额外元件使该第一元件与第二元件无直接接触。各种元件可能以任意不同比例显示以使图示清晰简洁。
图2显示为依照本发明实施例制造高介电常数栅极介电层312(如第3图所示)的方法200。图3A-图3H显示依照本发明实施例的半导体装置300于各种制造阶段的剖面图。可知的是，半导体装置300的其他元件可由普通的互补式金属氧化物半导体(CMOS)技术工艺制造，因而在此某些互补式金属氧化物半导体(CMOS)的范例仅简短描述。同理，图2至图3H也已经简化以使本发明的发明概念易于了解。例如，虽然图示中仅显示用于半导体装置300的高介电常数栅极介电层312，可知的是，使用本发明揭示的方法所制造的半导体装置可为集成电路的一部分，此集成电路尚可包含其他例如电阻、电容、电感或熔丝等元件。
参见图2至图3A，方法200起始于步骤202，其为提供具有有源区304及隔离区306部分的基材302。在一实施例中，基材302包含结晶硅基材(例如晶片)。基材302可依据设计需求包含各种掺杂浓度(例如p型基材或n型基材)。或者，基材302可由其他合适的元素半导体(例如钻石或锗)、合适的化合物半导体(例如砷化镓、碳化硅、砷化铟、磷化铟)或合适的合金半导体(例如碳锗化硅、砷磷化镓、铟磷化镓)形成。再者，基材302可包含外延层、应变以增进效能、和/或包含绝缘层上覆硅(SOI)结构。
有源区304可依照公知技术的各种需求包含各种掺杂浓度。在某些实施例中，有源区304可掺杂p型或n型掺质。例如，有源区304可掺杂p型掺质(例如硼或BF2)、n型掺质(例如磷或砷)和/或前述的组合。有源区304可设计为N型金属氧化物半晶体管元件(称为NMOS)或P型金属氧化物半晶体管元件(称为PMOS)。
隔离区306可形成在基材302上以隔离各种有源区304。隔离区306可利用例如硅区域氧化法(LOCOS)或浅沟槽隔离(STI)的隔离技术来定义及电性隔离各有源区304。在本实施例中，隔离区306包含浅沟槽隔离。隔离区306可包含氧化硅、氮化硅、氮氧化硅、氟掺杂玻璃(FSG)、低介电常数介电材料、其他合适材料和/或前述的组合。隔离区306及本实施例中的浅沟槽隔离，可由任何合适工艺形成。在一实施例中，浅沟槽隔离的形成可包含以传统光学微影工艺图案化半导体基材302，在基材302中蚀刻一沟槽(例如使用干蚀刻、湿蚀刻和/或等离子体蚀刻工艺)，及以介电材料填满沟槽(例如使用化学气相沉积)。在某些实施例中，此填满的沟槽可具有多层结构，例如具有一热氧化衬层并填满氮化硅或氧化硅。
继续参见图2及图3A，接着进行步骤204，其为形成高介电常数介电层312于基材302上。高介电常数介电层定义为介电常数大于二氧化硅的介电材料。高介电常数介电层312可包含金属氧化物。金属氧化物择自下列氧化物所组成的群组：Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu及前述的混合物。高介电常数介电层312的厚度为约1至4nm。在本实施例中，高介电常数介电层312包含氧化铪层，且在此后称为氧化铪层312。
高介电常数栅极介电层312可由任何合适工艺形成，包含在此所述的工艺。在本实施例中，使用原子层沉积工艺沉积高介电常数栅极介电层312于基材302上。在此原子层沉积工艺中，提供交替的金属源化学品及氧源化学品的脉冲(pulse)至反应腔室中。每个反应物的脉冲以自限制(self-limiting)方式使表面饱和。
在原子层工艺的一实施例中，氧化铪层312组成的高介电常数栅极介电层312的形成包含下列步骤。首先，将半导体基材302载入反应腔室。接着，在250至350℃下将铪源化学品脉冲注入已具有半导体基材302的反应腔室一第一周期时间。在此，铪源化学品可择自四氯化铪(HfCl4)、四-(乙基甲基胺基酸)-铪(TEMAH，tetra-ethyl-methyl amino hafnium)、四-(1-甲氧基2-甲基2丙氧基)-铪(Hf(MMP)4，tetra(1-methoxy2-methyl 2-propoxy)Hf)及前述的混合物。当铪源化学品注入至反应腔室中，即会在半导体基材302顶部表面上形成铪源化学品的化学吸附层。接着，排除所有的铪源化学品至反应腔室外一第二周期时间。为了更有效地自反应腔室排除剩余的铪源化学品，可在第一净化周期中注入净化气体(purge gas)至反应腔室中，其中净化气体可包含实质上的惰性气体，例如氮气、氩气、氦气或类似的惰性气体。
自反应腔室排除剩余的铪源化学品后，在250至350℃下将氧源化学品脉冲注入已具有半导体基材302的反应腔室一第三周期时间。在此，氧源化学品可择自下列材料组成的群组：氧气、臭氧、水、过氧化氢及前述的组合。氧源化学品在250至350℃下与铪源化学品的化学吸附层混合。因此，在半导体基材302上形成氧化铪的原子层。接着，排除所有的氧源化学品至反应腔室外一第四周期时间。为了更有效地自反应腔室排除剩余的氧源化学品，可在第二净化周期中注入例如氮气、氩气、氦气或类似的惰性气体的净化气体(purge gas)至反应腔室中。
正常情况下，原子层沉积工艺包含连续的原子层沉积循环，也即将前述的第一至第四周期(将铪源化学品及氧源化学品交替注入反应腔室内，且随后将其排除至反应腔室外)合起来即为一次的沉积或膜层的循环。随着重复上述循环多次，即可形成所欲厚度的氧化铪层312。氧化铪层312的厚度为约1至4nm。在沉积工艺后，空穴312a及来自两种化学品的杂质312b皆嵌在氧化铪层312中。
参见图2及图3B，继续进行步骤206，其为以原子层沉积工艺形成不含金属元素的含氧层314于高介电常数介电层312上。在本实施例中，将氧源化学品脉冲注入反应腔室中一第五周期时间。在此，氧源化学品可择自下列材料组成的群组：氧气、臭氧、水、过氧化氢及前述的组合。当氧源化学品注入至反应腔室后，含氧层314即附着于氧化铪层312的顶部表面上。接着，自反应腔室中排除所有剩余的氧源化学品一第六周期时间。为了更有效地自反应腔室排除剩余的氧源化学品，可在此第三净化周期中注入例如氮气、氩气、氦气或类似的惰性气体的净化气体(purge gas)至反应腔室中。
此原子层沉积工艺可包含连续的原子层沉积循环，也即，如将前述的第五至第六周期(注入氧源化学品及随后将其排除至反应腔室外)合起来即为一次的含氧层314的形成循环。随着重复上述循环多次，即可形成所欲厚度的含氧层314。值得注意的是，于基材302上形成高介电常数介电层312的步骤及在高介电常数介电层312上形成含氧层312的步骤可使用不同的氧源化学品。例如，先使用水作为氧源化学品以形成高介电常数介电层312，但随后使用氧气作为氧源化学品以形成含氧层314。
参见图2及图3C，继续进行步骤208，其为在含氧层314上进行惰性等离子体处理380。在本实施例中，为在约20至500W的电源功率及约100mTorr至10Torr的压力下使用氮气、氩气或氦气为气体源，在含氧层314上进行惰性等离子体处理308。在进行惰性等离子体处理的期间，氧自由基可进入氧化铪层中312以填满空穴312a及取代氧化铪层312中的杂质312b。既然氧自由基的供应是自限制于含氧层314的厚度，因此可调整氧自由基的数量，而不会有过多能穿透氧化铪层312到达基材302顶部表面的氧自由基，因而可避免在基材302顶部表面生成不欲形成的氧化硅，此不欲形成的氧化硅会增加栅极介电层的等效厚度。因此，在此所揭示的方法可保持装置效能特性，例如临界电压。
高介电常数栅极介电层312可更包含界面层(未显示)，以将高介电常数栅极介电层312及基材302之间的应力最小化。界面层可由热氧化工艺生长的氧化硅或氮氧化硅形成。例如，界面层可由快速热退火(RTO)工艺或传统包含氧气的退火工艺形成。或者，界面层可由原子层沉积工艺或由一系列的湿和/或干表面处理形成。界面层的厚度约介于0.2至0.8nm之间。
在进行如图3A至图3C所示的步骤之后，接着使用标准的互补式金属氧化物半导体工艺完成晶体管的制造。例如，图3D至图3H显示进一步使用“后栅极”CMOS工艺制造半导体装置300。参见图3D，可形成虚置栅极电极层316于高介电常数栅极介电层312上。在某些实施例中，虚置栅极电极层316可包含单层或多层结构。在本实施例中，虚置栅极电极层316可包含多晶硅。再者，虚置栅极电极层316可包含均匀或梯度掺杂的多晶硅。虚置栅极电极层316的厚度可为约30至60nm。虚置栅极电极层316可由低压化学气相沉积(LPCVD)形成。在一实施中，低压化学气相沉积可在约580至650℃、200mTorr至1Torr的压力下使用硅烷(SiH4)或二氯硅烷(SiCl2H2)为气体源，于标准低压化学气相沉积加热炉中进行。
接着，以例如光致抗蚀剂涂布的适当工艺形成光致抗蚀剂于虚置栅极电极层结构316上，及以光学微影方法将光致抗蚀剂图案化以形成图案化光致抗蚀剂元件。可使用干蚀刻工艺将图案化光致抗蚀剂元件转移至底下的膜层
(也即高介电常数栅极介电层312及虚置栅极电极层316)以形成栅极结构320。随后，可将光致抗蚀剂剥除。在另一实施例中，可形成硬掩模层320于栅极结构320上；形成图案化光致抗蚀剂层于硬掩模层上；转移光致抗蚀剂层的图案至硬掩模层上，并接着转移至虚置栅极电极层316及高介电常数栅极介电层312，以形成栅极结构320。可知的是，上述实施例并非用以限制可用于形成栅极结构320的工艺步骤。更可知的是，栅极结构320可包含额外的介电层和/或导电层。例如，栅极结构320可包含界面层、盖层、扩散/阻挡层、其他合适膜层和/或前述的组合。
继续参见图3D，可形成轻掺杂源极/漏极区(LDD)322于基材302的有源区304中。轻掺杂源极/漏极区322可由一或多次的离子注入工艺形成于有源区304中。掺杂物质可依据装置型态来决定，例如NMOS或PMOS装置。例如，轻掺杂源极/漏极区322可掺杂p型掺质(例如硼或二氟化硼)、n型掺质(例如磷或砷)和/或前述的组合。轻掺杂源极/漏极区322可包含各种掺杂轮廓。在离子注入工艺后，轻掺杂源极/漏极区322可与栅极结构210的外部边缘对齐。
参见图3E，形成例如氮化硅层或氮氧化硅层的含氮介电层于栅极结构320周围。含氮介电层可由温度低于400℃、压力低于200mTorr至1Torr，使用硅烷、氨气和/或一氧化二氮为气体源的等离子体沉积形成。接着，在含氮介电层上进行各向异性蚀刻以形成栅极间隔物230于栅极结构320的两侧。栅极间隔物324的厚度可为约7至15nm。栅极侧壁324可包含多层结构。
继续参见图3E，可使用栅极间隔物324使源极/漏极区326偏移(offset)。源极/漏极区326可由一或多次离子注入工艺形成于基材302的有源区304中。掺质可依据装置型态来决定，例如NMOS或PMOS装置。源极/漏极区326可掺杂p型掺质(例如硼或二氟化硼)、n型掺质(例如磷或砷)和/或前述的组合。源极/漏极区326可包含各种掺杂轮廓，且在离子注入工艺后与栅极间隔物324的外部边缘对齐。在某些实施例中，源极/漏极区326可更包含增高式源极/漏极区。同样地，可由自对准硅化工艺形成一或多个接触点元件(例如硅化区)于源极/漏极区326上。
参见图3F，可形成接触蚀刻停止层(CESL)328于基材上，包含形成在栅极结构320上。接触蚀刻停止层328可由氧化硅、氮化硅或前述的组合形成。在本实施例中，接触蚀刻停止层328由等离子体辅助式化学气相沉积(PECVD)混频工艺所形成的氮化硅(例如SiN)形成。例如，混频方法包供应如(1)硅烷和/或(2)六氯二硅甲烷(Si2Cl6)与氨气的源化学品，在约300至600℃的温度、约50mTorr至5Torr的压力、约70W至300W的高频功率及约5W至60W的低频功率下。在本实施例中，接触蚀刻停止层328的厚度约在某些实施例中，不使用接触蚀刻停止层328。
可形成层间介电层(ILD)330于接触蚀刻停止层(CESL)328上。层间介电层(ILD)330可包含介电材料。介电材料可包含氧化硅、旋涂式玻璃、氟掺杂玻璃、碳掺杂氧化硅(例如SiCOH)、Black(AppliedMaterials of Santa Clara，California)、其他介电材料和/或前述的组合。在某些实施例中，层间介电层(ILD)330可包含高密度等离子体(HDP)介电材料和/或高深宽比工艺(HARP)介电材料。在本实施例中，层间介电层(ILD)330的厚度为约至可知的是，层间介电层(ILD)330可包含一或多种介电材料和/或一或多层介电层。
随后，可以化学机械研磨(CMP)工艺平坦化接触蚀刻停止层328和/或层间介电层330，直至暴露出一部分的虚置栅极电极层316。化学机械研磨工艺可具有高选择性以提供虚置栅极电极层316、栅极间隔物324、接触蚀刻停止层328及层间介电层330实质上平坦的表面。在本实施例中，栅极结构320可被栅极间隔物324、接触蚀刻停止层328及层间介电层330等介电材料所围绕。
参见图3G，可由任何合适工艺自栅极结构320移除虚置栅极电极层316，以于栅极间隔物324中形成开口332。可使用湿蚀刻和/或干蚀刻工艺移除虚置栅极电极层316。在一实施例中，用于虚置多晶硅栅极电极层316的湿蚀刻工艺包含暴露于含氢氧化铵、稀氢氟酸、去离子水的氢氧化物溶液和/或其他合适蚀刻溶液中。在其他实施例中，用于虚置多晶硅栅极电极层316的干蚀刻工艺可在约650至800W的电源功率、约100至120W的偏压功率、及约60至200mTorr的压力下，使用氯气、溴化氢及氦气作为蚀刻气体进行。
参见图3H，可沉积金属栅极电极层318完全填满开口332以形成栅极结构320。在某些实施例中，金属栅极电极层318可包含下列材料，例如Al、Cu、TiN、TiAlN、TiCN、TaN、TaCN、WN及WCN。在某些实施例中，金属栅极电极层318在开口中具有小于32nm的栅极长度。接着，进行化学机械研磨工艺以平坦化金属栅极电极层318。化学机械研磨工艺可移除部分的金属栅极电极层318，直至到达层间介电层330的顶部表面。接着，于随后工艺中，包含内连线工艺，需在形成栅极结构320的金属栅极电极层318后形成，以完成半导体装置300的制造。
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，反而，任何本领域技术人员可知，上述优选实施例意指包括各种润饰及相似的排列。因此，本发明的保护范围当视为包括所有润饰及相似的排列。例如，本发明可用于形成或制造鳍式场效应晶体管的高介电常数栅极介电层。在此应用中，无不欲形成的氧化硅形成在基材顶部表面上以影响高介电常数栅极介电层的等效厚度。

Claims (8)

1.一种高介电常数介电层的制造方法，包括：
形成一高介电常数介电层于一基材上，该高介电常数介电层包括多个空穴与多个杂质；
以一原子层沉积工艺形成一不含金属元素的含氧层于该高介电常数介电层上，其中该含氧层的沉积源仅包含氧源化学品，该氧源化学品择自下列材料组成的群组：氧气、臭氧、水或过氧化氢；以及
于该含氧层上进行一惰性等离子体处理，以使该含氧层中的氧自由基填入该高介电常数介电层中，以取代所述多个空穴与所述多个杂质。
2.如权利要求1所述的高介电常数介电层的制造方法，其中该形成一高介电常数介电层于一基材上的步骤及该以原子层沉积工艺形成一含氧层于该高介电常数介电层上的步骤使用不同的氧源化学品。
3.如权利要求1所述的高介电常数介电层的制造方法，其中在该含氧层上进行一惰性等离子体处理的步骤使用氮气、氩气、氦气至少其一作为气体源。
4.如权利要求1所述的高介电常数介电层的制造方法，其中该于该含氧层上进行一惰性等离子体处理的步骤在100mTorr至10Torr的压力及20W至500W的电源功率下进行。
5.一种半导体装置的栅极介电层的制造方法，包括：
以一第一原子层沉积工艺在一基材上形成一氧化铪层，作为一栅极介电层，该氧化铪层包括多个空穴与多个杂质；
以一第二原子层沉积工艺形成一不含金属元素的含氧层于该氧化铪层上，其中该含氧层的沉积源仅包含氧源化学品，该氧源化学品择自下列材料组成的群组：氧气、臭氧、水或过氧化氢；以及
于该含氧层上进行一惰性等离子体工艺，以使该含氧层中的氧自由基填入该氧化铪层中，以取代所述多个空穴与所述多个杂质。
6.如权利要求5所述的半导体装置的栅极介电层的制造方法，其中在该第一及第二原子层沉积工艺使用不同的氧源化学品。
7.如权利要求5所述的半导体装置的栅极介电层的制造方法，其中该于该含氧层上进行一惰性等离子体处理的步骤使用氮气、氩气、氦气至少其一作为气体源。
8.如权利要求5所述的半导体装置的栅极介电层的制造方法，其中该于该含氧层上进行一惰性等离子体处理的步骤在100mTorr至10Torr的压力及20W至500W的电源功率下进行。
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US8357603B2 (en) * 2009-12-18 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate fill and method of making
US9337103B2 (en) * 2012-12-07 2016-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for removing hard mask oxide and making gate structure of semiconductor devices
US9698234B2 (en) 2014-08-08 2017-07-04 Samsung Electronics Co., Ltd. Interface layer for gate stack using O3 post treatment
US11290110B2 (en) 2017-10-26 2022-03-29 Samsung Electronics Co., Ltd. Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1875463A (zh) * 2003-11-08 2006-12-06 先进微装置公司 于晶体管工艺中整合高k栅极电介质的方法
CN101593686A (zh) * 2008-05-30 2009-12-02 中芯国际集成电路制造(北京)有限公司 金属栅极形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
KR100568448B1 (ko) * 2004-04-19 2006-04-07 삼성전자주식회사 감소된 불순물을 갖는 고유전막의 제조방법
US20060019033A1 (en) * 2004-05-21 2006-01-26 Applied Materials, Inc. Plasma treatment of hafnium-containing materials
US8603924B2 (en) * 2010-10-19 2013-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming gate dielectric material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1875463A (zh) * 2003-11-08 2006-12-06 先进微装置公司 于晶体管工艺中整合高k栅极电介质的方法
CN101593686A (zh) * 2008-05-30 2009-12-02 中芯国际集成电路制造(北京)有限公司 金属栅极形成方法

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