CN102194894B - Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof - Google Patents
Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof Download PDFInfo
- Publication number
- CN102194894B CN102194894B CN 201110116537 CN201110116537A CN102194894B CN 102194894 B CN102194894 B CN 102194894B CN 201110116537 CN201110116537 CN 201110116537 CN 201110116537 A CN201110116537 A CN 201110116537A CN 102194894 B CN102194894 B CN 102194894B
- Authority
- CN
- China
- Prior art keywords
- silicon
- silicon chip
- diode
- type semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
- Silver Salt Photography Or Processing Solution Therefor (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses an electrical-surge-resistance low-voltage-protection silicon diode and a manufacturing method thereof. The manufacturing method comprises the following steps of: (1) diffusing N+ type semiconductor impurity phosphor onto the surface of a P-type monocrystalline silicon polished wafer to obtain a PN+ silicon wafer; (2) washing the PN+ silicon wafer with an electrochemical washing fluid No.1 and an electrochemical washing fluid No.2, flushing with pure water and spinning the silicon wafer to dryness; (3) carrying out N- type epitaxial growth on the washed PN+ silicon wafer to obtain a PN+N- silicon wafer; (4) diffusing N+ type semiconductor impurity phosphor onto the PN+N- silicon wafer to obtain a PN+N-N+ silicon wafer; (5) plating a metal layer on double surfaces of the PN+N-N+ silicon wafer, alloying and carrying out saw cutting to obtain a diode chip; and (6) welding the diode chip and a packaging base, applying protection glue, carrying out mold pressing and forming, and packaging to obtain a device. The electrical-surge-resistance low-voltage-protection silicon diode manufactured with the manufacturing method disclosed by the invention has the characteristics of universal production equipment, high cost performance of the product and wide market.
Description
Technical field
The present invention relates to a kind of anti-electric surge low-voltage variation silicon diode and preparation method thereof.
Background technology
The fast development of semiconductor technology and information industry; integrated circuit and the precision instrument circuit elements device low pressure that more and more becomes; take on the safety of Protective IC and electronic circuit and effectively anti-lightning, damage of electrostatic discharge effect electronic regulation, moment the over-voltage suppression silicon diode demand grow with each passing day; particularly protect voltage range to be lower than 10 volts the reliable anti-electric surge low-voltage variation silicon diode of high stable, existing home products still can not satisfy the demands fully.Enforcement of the present invention can provide a kind of highly reliable, colory anti-electric surge low pressure silicon protection new unit.
This anti-electric surge low-voltage variation silicon diode is mainly for the protection of the integrated circuit with power inductance.For example the inductance of transformer can produce transient peak voltage in the flyback converter in the voltage transitions process, in order to protect whole circuit, need to carry out the clamper restriction to this voltage.Normal RC damping circuit and the RCD damping circuit of adopting carries out the clamper restriction in the traditional circuit, and the designer also adopts single voltage stabilizing didoe to come protective circuit simultaneously.RC damping circuit and RCD damping circuit performance are more stable, eliminate the electromotive force concussion that inductance produces by the damping circuit of electric capacity and resistance, come the self induction electromotive force of absorption inductor by diode.But the damping circuit method will be used a resistance, an electric capacity and a diode usually, for realizing a kind of function, needs to install a plurality of components and parts on the circuit board like this, certainly will reduce security reliability.Using single voltage stabilizing didoe inhibition moment overvoltage, the anti-electric surge of circuit safety is new developing direction.
Feature of the present invention is to diffuse into N+ type semiconductor impurities phosphorus twice in a low-resistance P-type silicon single-crystal polishing plate minute priority, obtain for the first time interior N+ layer, obtain outer N+ layer for the second time, in addition, between inside and outside two N+ layers, by the epitaxial growth of N-type, be inserted into a N-silicon epitaxy layer, obtaining vertically is the silicon diode structure of PN+N-N+.The effect of N-silicon epitaxy layer is as one barrier, prevents when electrode metal alloy thereafter N+ layer in the circulation and the PN junction inefficacy occurs.The N+P that wherein is comprised of interior N+ layer partly is the core of the monolateral sudden change PN junction of silicon, and the function of outer N+ layer is to make to form good ohmic between silicon and the metal electrode and contact.The phosphorus impurities surface concentration of inside and outside N+ layer is 10
21/ cm
3
Table 1, table 2, table 3(Fig. 4, Fig. 5, Fig. 6) shown in the analog result resistivity Res that represented P type silicon single crystal and silicon diode protect relation between the voltage Vbr.
Table 1
| Intrinsic Res | Intrinsic concentration | The doping junction depth | Ns | RS | Vbr |
| 0.01ohm.cm | 7.98e18 | 7.6μm | 0.73e21 | 0.63 | 8.3V |
Table 2
| Intrinsic Res | Intrinsic concentration | The doping junction depth | Ns | RS | Vbr |
| 0.02ohm.cm | 2.68e18 | 8μm | 0.73e21 | 0.61 | 11.6V |
Table 3
| Intrinsic Res | Intrinsic concentration | The doping junction depth | Ns | RS | Vbr |
| 0.08ohm.cm | 3.28e18 | 9.5μm | 0.74e21 | 0.61 | 23.7V |
Simulated conditions: chip thickness 300 μ m, the unit length of side 50 μ m.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art; employing diffuses into N+ type semiconductor impurities phosphorus at P type silicon single-crystal polishing plate; carry out the epitaxially grown process of N-type in conjunction with the centre, obtain a kind of anti-electric surge low-voltage variation silicon diode, its preparation methods steps is as follows:
1) be that 250～300 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.01～0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCL:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.05～0.10 Ω .cm, and thickness is 10～15 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
It is general that the anti-electric surge low-voltage variation silicon diode of manufacturing of the present invention has production equipment, and the product cost performance is high, the characteristics of extensive market.
Description of drawings
Fig. 1 is the structural representation of anti-electric surge low-voltage variation silicon diode;
Fig. 2 is preparation method's flow process of anti-electric surge low-voltage variation silicon diode;
Fig. 3 is the Impurity Distribution schematic diagram of anti-electric surge low-voltage variation silicon diode;
Fig. 4, Fig. 5, Fig. 6 are the processing simulation figure of resistivity Res and the silicon diode protection voltage Vbr Relations Among of P type silicon single crystal.
Embodiment
Anti-electric surge low-voltage variation silicon diode is: adopt and diffuse into N+ type semiconductor impurities phosphorus at P type silicon single-crystal polishing plate; carry out the epitaxially grown process of N-type in conjunction with the centre; obtain a kind of anti-electric surge low-voltage variation silicon diode, its preparation methods steps is as follows:
1) be that 250～300 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.01～0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCL:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.05～0.10 Ω .cm, and thickness is 10～15 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
Embodiment 1
1) be that 250 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.01 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCL:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.05 Ω .cm, and thickness is 15 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
1) be that 280 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.04 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCL:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.10 Ω .cm, and thickness is 10 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 9 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
Embodiment 3
1) be that 300 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCL:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.08 Ω .cm, and thickness is 12 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
Claims (2)
1. anti-electric surge low-voltage variation silicon diode, it is characterized in that in resistivity being that the P type silicon single-crystal polishing plate of 0.01～0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus, carry out the epitaxial growth of N-type, diffuse into again N+ type semiconductor impurities phosphorus, manufacture the diode that vertical structure is PN+N-N+; Concrete preparation method's step is as follows:
1) be that 250～300 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.01～0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCl:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.05～0.10 Ω .cm, and thickness is 10～15 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
2. a kind of preparation method of anti-electric surge low-voltage variation silicon diode as claimed in claim 1 is characterized in that its step is as follows:
1) be that 250～300 μ m, resistivity are that the P type silicon single-crystal polishing plate surface of 0.01～0.08 Ω .cm diffuses into N+ type semiconductor impurities phosphorus at thickness, obtain the PN+ silicon chip, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times, the N+ type semiconductor impurities phosphorus surface concentration that diffuses into is 10
21/ cm
3
2) clean the PN+ silicon chip with electronics chemical cleaning 1# liquid, cleaning temperature is 80～85 ℃, and scavenging period is 10～15 minutes, pure water rinsing; Clean with electronics chemical cleaning 2# liquid, cleaning temperature is 80～85 ℃ again, and scavenging period is 10～15 minutes, dry, and pure water water outlet resistivity 10～12 Ω .cm, the volume ratio that electron chemistry cleans 1# liquid is: NH
4OH:H
2O
2: H
2O=1:2:5, the volume ratio that electron chemistry cleans 2# liquid is: HCl:H
2O
2: H
2O=1:2:8;
3) the PN+ silicon chip after cleaning carries out the epitaxial growth of N-type, obtains the PN+N-silicon chip, and the N-silicon epitaxy layer resistivity of PN+N-silicon chip is 0.05～0.10 Ω .cm, and thickness is 10～15 μ m;
4) diffuse into N+ type semiconductor impurities phosphorus at the PN+N-silicon chip, obtain the silicon chip of PN+N-N+, 1190～1200 ℃ of diffusion temperatures, 8～10 minutes diffusion times;
5) metal level on two plated surfaces of PN+N-N+ silicon chip carries out alloy, and sawing obtains diode chip for backlight unit;
6) with diode chip for backlight unit and encapsulation base plate welding, upper protection glue, moulded section are packaged into device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110116537 CN102194894B (en) | 2011-05-06 | 2011-05-06 | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110116537 CN102194894B (en) | 2011-05-06 | 2011-05-06 | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102194894A CN102194894A (en) | 2011-09-21 |
| CN102194894B true CN102194894B (en) | 2013-01-02 |
Family
ID=44602651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110116537 Expired - Fee Related CN102194894B (en) | 2011-05-06 | 2011-05-06 | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102194894B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681635A (en) * | 2015-03-09 | 2015-06-03 | 江苏中科君芯科技有限公司 | Diode structure for reducing anode hole injection |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08316499A (en) * | 1995-05-23 | 1996-11-29 | Toyo Electric Mfg Co Ltd | High-speed diode |
| US5880511A (en) * | 1995-06-30 | 1999-03-09 | Semtech Corporation | Low-voltage punch-through transient suppressor employing a dual-base structure |
| JP3968912B2 (en) * | 1999-05-10 | 2007-08-29 | 富士電機デバイステクノロジー株式会社 | diode |
| JP2007294833A (en) * | 2006-03-27 | 2007-11-08 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| US7638816B2 (en) * | 2007-08-28 | 2009-12-29 | Littelfuse, Inc. | Epitaxial surge protection device |
| CN101621002B (en) * | 2009-08-05 | 2014-04-16 | 广东百圳君耀电子有限公司 | Manufacturing method of low-voltage transient voltage suppression diode chip |
| CN101908504B (en) * | 2010-07-07 | 2012-06-27 | 天水天光半导体有限责任公司 | Abrupt-junction voltage stabilizing diode made of polysilicon and manufacture process thereof |
-
2011
- 2011-05-06 CN CN 201110116537 patent/CN102194894B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN102194894A (en) | 2011-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102856318B (en) | Uni-directional transient voltage suppressor | |
| CN101527324B (en) | Two-way low-voltage punch-through transient voltage suppression diode and manufacturing method thereof | |
| CN104078353B (en) | Reverse GPP high-voltage diodes chip and production technology in a kind of automobile module | |
| CN103035746B (en) | Current regulative diode and manufacturing method thereof | |
| JP2013080946A5 (en) | ||
| CN202384330U (en) | Glass passivated chip with multilayer protection | |
| CN102789970A (en) | Preparation method for fast recovery diode chip | |
| CN107680962B (en) | Low forward voltage TVS device and manufacturing method thereof | |
| CN102290337A (en) | Manufacturing method for silicon epitaxial wafer of low-voltage TVS (transient voltage suppressor) | |
| CN106169508B (en) | Bidirectional ultra-low capacitance transient voltage suppressor and manufacturing method thereof | |
| CN102194894B (en) | Electrical-surge-resistance low-voltage-protection silicon diode and manufacturing method thereof | |
| CN210866178U (en) | TVS device of integrated unidirectional low-capacity GPP process | |
| CN111755529A (en) | Bidirectional symmetrical TVS diode and manufacturing method thereof | |
| KR20150096914A (en) | Method of manufacturing low capacitance TVS and Devices using the method | |
| CN103972305B (en) | Method for manufacturing low-voltage transient voltage suppression diode chip | |
| CN105679836B (en) | Ultra-low capacitance TVS diode structure and preparation method thereof | |
| CN103050545A (en) | TVS (Transient Voltage Suppressor) diode and manufacturing method thereof | |
| CN104617158B (en) | A kind of Transient Voltage Suppressor structure with ultra-deep groove | |
| CN107301995A (en) | Transient Voltage Suppressor and preparation method thereof | |
| CN206947345U (en) | A kind of ultra-low capacitance TVS device structure | |
| CN103474346A (en) | Realization method of transient voltage suppression diode PN junction | |
| CN102117806B (en) | Duodiode integrating Zener diode with rectifying diode and production method thereof | |
| CN104851925B (en) | A kind of backside openings structure of local back contact solar cell | |
| CN109449152B (en) | Inhibition chip and preparation method thereof | |
| CN208781854U (en) | A kind of unidirectional TVS device of big surge |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: HANGZHOU JINGDI SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: HANGZHOU HANGXIN ELECTRONIC INDUSTRY CO., LTD. Effective date: 20130930 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130930 Address after: Hangzhou City, Zhejiang Province, Binjiang District Puyan street 310053 Albert Road No. 3 Building 3 Patentee after: HANGZHOU JINGDI SEMICONDUCTOR CO., LTD. Address before: 7 building, 310053 hi tech software park, Hangzhou, Zhejiang, Binjiang District Patentee before: Hangzhou Hangxin Electronic Industry Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130102 Termination date: 20150506 |
|
| EXPY | Termination of patent right or utility model |