CN202384330U - Glass passivated chip with multilayer protection - Google Patents
Glass passivated chip with multilayer protection Download PDFInfo
- Publication number
- CN202384330U CN202384330U CN2011205626634U CN201120562663U CN202384330U CN 202384330 U CN202384330 U CN 202384330U CN 2011205626634 U CN2011205626634 U CN 2011205626634U CN 201120562663 U CN201120562663 U CN 201120562663U CN 202384330 U CN202384330 U CN 202384330U
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Abstract
The utility model discloses a glass passivated chip with multilayer protection. The glass passivated chip comprises a semiconductor substrate, a P+ layer on the semiconductor substrate, an N+ layer, and a glass passivation layer, wherein an oxygen-containing polycrystalline silicon protection layer and a silicon nitride protection layer are arranged in the etched trench of the semiconductor substrate; the oxygen-containing polycrystalline silicon protection layer is located on the surface of the etched trench; and the silicon nitride protection layer is located between the oxygen-containing polycrystalline silicon protection layer and the glass passivation layer. The glass passivated chip provided by the utility model can improve the resistance to reverse voltage surge, thereby improving the service life and reliability of the product.
Description
Technical field
The utility model relates to the diode rectification chip part in a kind of electronic semiconductor components encapsulating material, relates in particular to a kind of glassivation chip of multilayer protection structure.
Background technology
After diode rectification chip product of the prior art adopts the silicon materials multiple operation to handle usually; Adopt glassivation technology protection PN junction one time; Improve the reverse reactance voltage ability of chip, for example Chinese patent number " 200920120101.7 " discloses a kind of mesa glassivation diode chip for backlight unit, and its open day is 2011.09.14; Comprise and adopt different doping processs, P type semiconductor and N type semiconductor are produced on the same block semiconductor substrate and at the PN junction of its interface formation; And be positioned at the table top sidewall and be coated on the outside passivation glass layer of PN junction; Near the sectional thickness that said glass passivation layer is positioned at the said PN junction position is positioned near the sectional thickness the said channel bottom greater than said glass passivation layer.
But it is following not enough that existing diode rectification chip mainly also exists: one, downstream industry encapsulation finished product is applied in the electronic circuit as diode, during rectified action, because of circuit load; Electric capacity; Inductance can form single or a plurality of reverse voltages in the accidental circuit and impact chip when each waveform work of device is accomplished, this moment, magnitude of voltage can reach several kilovolts or volt up to ten thousand, directly can cause chip reverse breakdown PN junction; The lead-in wire component failure can cause components and parts to cross thermal explosion when serious.Two, this kind inefficacy is according to operating position, and processing procedure lost efficacy at 100ppm, because of the component failure repair rate near 7%, according to the inefficacy product analysis, be mostly reverse over-voltage breakdown.Three, a domestic not reproducible anti-pressure ability (VRSM) is in 1500V-2000V level, and an external not reproducible anti-pressure ability (VRSM) is in the 2500-3000 level.
Summary of the invention
The purpose of the utility model is to overcome the problems referred to above that existing diode rectification chip exists, and a kind of glassivation chip of multilayer protection is provided, and the utility model can improve the anti-reverse voltage impact capacity of chip, improves finished product life-span and reliability.
For realizing above-mentioned purpose, the technical scheme that the utility model adopts is following:
A kind of glassivation chip of multilayer protection; Comprise P+ layer, N+ layer and glass passivation layer on semiconductor chip, the semiconductor chip; It is characterized in that: be provided with in the erosion grooves of said semiconductor chip and contain oxygen polysilicon protection layer and silicon nitride protective layer; The said oxygen polysilicon protection layer that contains is positioned on the erosion grooves surface, and silicon nitride protective layer is containing between oxygen polysilicon protection layer and the glass passivation layer.
Said P+ layer and N+ laminar surface are all electroplated and are provided with nickel dam.
The said thickness that contains oxygen polysilicon protection layer is the 500-1500 dust.
The thickness of said silicon nitride protective layer is the 200-1000 dust.
The thickness of said nickel dam is 2-10um.
Adopt the advantage of the utility model to be:
One, in the utility model, be provided with in the erosion grooves of said semiconductor chip and contain oxygen polysilicon protection layer and silicon nitride protective layer, the said oxygen polysilicon protection layer that contains is positioned on the erosion grooves surface; Silicon nitride protective layer is containing between oxygen polysilicon protection layer and the glass passivation layer, on the basis of glass passivation layer protection, through increase the growth protecting layer at the erosion grooves place; The protection PN junction; Improve the anti-reverse voltage impact capacity of chip, make the anti-reverse voltage impact capacity of chip (VRSM) can reach the 6000V-8000V level, greatly improve finished product life-span and reliability; Inefficacy can reduce 60ppm at least to processing procedure, reaches the 40ppm level; At least reduce by 2 percentage points to using to lose efficacy, the economic benefit in later stage greatly is provided.
Two, in the utility model, said P+ layer and N+ laminar surface are all electroplated and are provided with nickel dam, combine with other protective layer, have further guaranteed the anti-reverse voltage impact capacity of chip.
Three, in the utility model, the said thickness that contains oxygen polysilicon protection layer is the 500-1500 dust, can better combine to form holistic protective layer with silicon nitride protective layer, and the protection effect is better.
Four, in the utility model, the thickness of said silicon nitride protective layer is the 200-1000 dust, can with contain oxygen polysilicon protection layer and better combine to form holistic protective layer, further guarantee the anti-reverse voltage impact capacity of chip.
Five, in the utility model, the thickness of said nickel dam is 2-10um, combines with other protective layer, and chip is formed complete protection.
Description of drawings
Fig. 1 is the utility model structural representation
Be labeled as among the figure: 1, semiconductor chip, 2, the P+ layer, 3, the N+ layer, 4, glass passivation layer, 5, contain oxygen polysilicon protection layer, 6, silicon nitride protective layer, 7, nickel dam.
Embodiment
A kind of glassivation chip of multilayer protection; Comprise P+ layer 2, N+ layer 3 and glass passivation layer 4 on semiconductor chip 1, the semiconductor chip 1; Be provided with in the erosion grooves of said semiconductor chip 1 and contain oxygen polysilicon protection layer 5 and silicon nitride protective layer 6; The said oxygen polysilicon protection layer 5 that contains is positioned on the erosion grooves surface, and silicon nitride protective layer 6 is containing between oxygen polysilicon protection layer 5 and the glass passivation layer 4.
The preferred implementation of the utility model is that said P+ layer 2 is all electroplated with N+ layer 3 surface and is provided with nickel dam 7, but is not limited thereto execution mode.
The another preferred implementation of the utility model does, the said thickness that contains oxygen polysilicon protection layer 5 is the 500-1500 dust, for example 500 dusts, 1000 dusts or 1500 dusts, but be not limited thereto.
The another preferred implementation of the utility model does, the thickness of said silicon nitride protective layer 6 is the 200-1000 dust, for example 200 dusts, 600 dusts or 1000 dusts, but be not limited thereto.
The another preferred implementation of the utility model does, the thickness of said nickel dam 7 is 2-10um, for example 2um, 6um or 10um, but be not limited thereto.
Below in conjunction with accompanying drawing the utility model is described further:
In the utility model, semiconductor chip 1 is can spread growth P+ layer 2 and N+ layer 3 through diffusion technology on the N base material, but is not limited thereto mode.
In the utility model, the nickel dam 7 of semiconductor chip 1 upper and lower surfaces can be respectively through being electroplated onto P+ layer 2 upper surface and N+ layer 3 lower surface, but be not limited thereto mode.
In the utility model, glass passivation layer 4 can be through sintering process protection PN junction; Contain oxygen polysilicon protection layer 5 and can accomplish through the CVD chemical deposition process, but be not limited to aforementioned manner with silicon nitride protective layer 6.
Claims (5)
1. the glassivation chip of multilayer protection; Comprise P+ layer (2), N+ layer (3) and glass passivation layer (4) on semiconductor chip (1), the semiconductor chip (1); It is characterized in that: be provided with in the erosion grooves of said semiconductor chip (1) and contain oxygen polysilicon protection layer (5) and silicon nitride protective layer (6); The said oxygen polysilicon protection layer (5) that contains is positioned on the erosion grooves surface, and silicon nitride protective layer (6) is positioned at and contains between oxygen polysilicon protection layer (5) and the glass passivation layer (4).
2. the glassivation chip of multilayer protection according to claim 1, it is characterized in that: said P+ layer (2) and N+ layer (3) surface are all electroplated and are provided with nickel dam (7).
3. the glassivation chip of multilayer protection according to claim 1 and 2, it is characterized in that: the said thickness that contains oxygen polysilicon protection layer (5) is the 500-1500 dust.
4. the glassivation chip of multilayer protection according to claim 1 and 2, it is characterized in that: the thickness of said silicon nitride protective layer (6) is the 200-1000 dust.
5. the glassivation chip of multilayer protection according to claim 2, it is characterized in that: the thickness of said nickel dam (7) is 2-10um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205626634U CN202384330U (en) | 2011-12-29 | 2011-12-29 | Glass passivated chip with multilayer protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205626634U CN202384330U (en) | 2011-12-29 | 2011-12-29 | Glass passivated chip with multilayer protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202384330U true CN202384330U (en) | 2012-08-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011205626634U Expired - Lifetime CN202384330U (en) | 2011-12-29 | 2011-12-29 | Glass passivated chip with multilayer protection |
Country Status (1)
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| CN (1) | CN202384330U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983077A (en) * | 2012-12-06 | 2013-03-20 | 乐山嘉洋科技发展有限公司 | Diode chip manufacturing method |
| CN104900716A (en) * | 2015-05-18 | 2015-09-09 | 杭州士兰集成电路有限公司 | Unidirectional TVS device structure and manufacturing method thereof |
| CN105405758A (en) * | 2015-12-02 | 2016-03-16 | 浙江明德微电子股份有限公司 | Glass passivation process of diode chip |
| CN107170727A (en) * | 2017-06-02 | 2017-09-15 | 朝阳无线电元件有限责任公司 | A kind of I classes metallurgical bonding diode design and manufacturing technology |
| CN113380622A (en) * | 2021-06-11 | 2021-09-10 | 青岛海宜丰电力电子有限公司 | High-temperature diode preparation method and high-temperature diode |
| CN117558634A (en) * | 2024-01-09 | 2024-02-13 | 江苏环鑫半导体有限公司 | Surface passivation process of semiconductor wafer |
-
2011
- 2011-12-29 CN CN2011205626634U patent/CN202384330U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983077A (en) * | 2012-12-06 | 2013-03-20 | 乐山嘉洋科技发展有限公司 | Diode chip manufacturing method |
| CN102983077B (en) * | 2012-12-06 | 2015-10-14 | 乐山嘉洋科技发展有限公司 | A kind of preparation method of diode chip for backlight unit |
| CN104900716A (en) * | 2015-05-18 | 2015-09-09 | 杭州士兰集成电路有限公司 | Unidirectional TVS device structure and manufacturing method thereof |
| CN104900716B (en) * | 2015-05-18 | 2018-07-20 | 杭州士兰集成电路有限公司 | Unidirectional TVS device structure and preparation method thereof |
| CN105405758A (en) * | 2015-12-02 | 2016-03-16 | 浙江明德微电子股份有限公司 | Glass passivation process of diode chip |
| CN105405758B (en) * | 2015-12-02 | 2018-08-07 | 浙江明德微电子股份有限公司 | A kind of glass passivation process of diode chip for backlight unit |
| CN107170727A (en) * | 2017-06-02 | 2017-09-15 | 朝阳无线电元件有限责任公司 | A kind of I classes metallurgical bonding diode design and manufacturing technology |
| CN113380622A (en) * | 2021-06-11 | 2021-09-10 | 青岛海宜丰电力电子有限公司 | High-temperature diode preparation method and high-temperature diode |
| CN117558634A (en) * | 2024-01-09 | 2024-02-13 | 江苏环鑫半导体有限公司 | Surface passivation process of semiconductor wafer |
| CN117558634B (en) * | 2024-01-09 | 2024-04-02 | 江苏环鑫半导体有限公司 | Surface passivation process of semiconductor wafer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120815 |
|
| CX01 | Expiry of patent term |