CN105405758B - A kind of glass passivation process of diode chip for backlight unit - Google Patents
A kind of glass passivation process of diode chip for backlight unit Download PDFInfo
- Publication number
- CN105405758B CN105405758B CN201510867849.3A CN201510867849A CN105405758B CN 105405758 B CN105405758 B CN 105405758B CN 201510867849 A CN201510867849 A CN 201510867849A CN 105405758 B CN105405758 B CN 105405758B
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- glass
- diode chip
- backlight unit
- sintering
- baking
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- 239000011521 glass Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000002161 passivation Methods 0.000 title claims abstract description 18
- 238000005245 sintering Methods 0.000 claims abstract description 35
- 238000010345 tape casting Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000013021 overheating Methods 0.000 claims 2
- 238000004528 spin coating Methods 0.000 abstract description 6
- 238000005253 cladding Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000005520 cutting process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000011049 filling Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
- Dicing (AREA)
Abstract
The present invention relates to a kind of glass passivation process of semiconductor diode chip, belong to field of semiconductor devices, glass paste is inserted in diode chip for backlight unit groove using knife coating twice, increase the thickness of glass in diode chip for backlight unit groove with this, the glass in diode chip for backlight unit groove is set to be distributed mainly on trenched side-wall in conjunction with flash baking mode, recycle spin-coating method that glass paste is spun on diode chip for backlight unit boss and flash baking, boss is outputed by photolithographicallpatterned and etches window, will carry out glass sintering after glass passivation layer removal in window.There is the present invention diode chip for backlight unit channel bottom glass thin, side thickness, the feature of boss edge glass thickness to be conducive to chip cutting, while provide better glass passivation layer cladding for PN junction and boss edge wedge angle.
Description
Technical field
The present invention relates to a kind of glass passivation process of semiconductor diode chip, belong to field of semiconductor devices.
Background technology
Passivating material one of of the glass as semiconductor devices, is usually used in the PN junction of protection diode chip.The prior art
It generally uses knife coating that glass paste is inserted diode chip for backlight unit trench interiors, is put into after being baked in baking oven and carries out glass burning again
Knot, to realize the cladding to PN junction.Often bottom is thick for the thickness of glass that the method is formed, and side is thin, in order to preferably protect
PN junction usually requires repeatedly to scratch operation, the thicker cutting for being unfavorable for diode chip for backlight unit of bottom glass.
It is existing in order to reduce the thickness of glass of channel bottom, while preferably to the cladding at diode chip for backlight unit boss edge
Using light blockage method glass passivation process, i.e., technology also has：Glass powder is mixed into photoresist, is inserted in diode chip for backlight unit groove
Portion, then by the glass of means of photolithography removal channel bottom, to retain glass and the realization pair at diode chip for backlight unit boss edge
The cladding of PN junction.The method needs to use special lithographic equipment, equipment input cost higher.
Invention content
The object of the present invention is to provide a kind of glass passivation process of diode chip for backlight unit, it is not necessary to can be real using special equipment
Existing diode chip for backlight unit channel bottom glass thin, side thickness, while can realize and boss edge is preferably coated.
In order to achieve the above objectives, the technical solution adopted in the present invention is：
A kind of glass passivation process of diode chip for backlight unit, includes the following steps：
1）Glass paste is inserted in the groove of diode chip for backlight unit using knife coating, first time glass is carried out after being dried with baking oven
Sintering；
2）Glass paste is inserted in the groove of diode chip for backlight unit with knife coating again, is then directly positioned over diode chip for backlight unit
In heating plate, second of glass sintering is carried out after high temperature flash baking；
3）Glass paste is spun and coated in diode chip for backlight unit surface and groove, is then directly positioned over diode chip for backlight unit
In heating plate, third time glass sintering is carried out after high temperature flash baking；
4）Photoresist is applied in diode chip for backlight unit surface and groove, the erosion of diode chip for backlight unit boss is outputed by photolithographicallpatterned
Window is carved, glass passivation layer in window is removed, then remove the photoresist in diode chip for backlight unit surface and groove, finally carries out the
Four glass sinterings.
It is as follows to the further setting of above-mentioned technical proposal：
The baking temperature of the baking oven is 90 ± 5 DEG C, and baking time is 30 ± 5 minutes.
The baking temperature of the heating plate is 200 ± 20 DEG C, and baking time is 2~5 minutes.
The first time, second, the 4th glass sintering temperature are 810 ± 5 DEG C, and sintering time is 30~40 minutes.
The third time glass sintering temperature is 500 ± 20 DEG C, and sintering time is 10~20 minutes.
Compared with prior art knife coating, the glass passivation layer that the present invention is formed has channel bottom thin, the spy of side thickness
Point is conducive to the cutting of diode chip for backlight unit, while glass passivation layer is thicker at PN junction, and covered effect is more preferable；With prior art light
Resistance method is compared, under the premise of need not introduce special lithographic equipment, you can realizes diode chip for backlight unit channel bottom glass thin, side
The characteristics of wall thickness, diode chip for backlight unit boss edge reservation glass is thicker, the more conducively protection of boss edge wedge angle.
The present invention is further elaborated below by way of the drawings and specific embodiments.
Description of the drawings：
Fig. 1 is not carry out diode chip for backlight unit schematic diagram before glass passivation process；
Fig. 2 is glass model schematic diagram after first time glass sintering of the invention；
Fig. 3 is glass model schematic diagram after second of glass sintering of the invention；
Fig. 4 is glass model schematic diagram after the 4th glass sintering of the invention.
Specific implementation mode：
In conjunction with shown in Fig. 1 to Fig. 4, present pre-ferred embodiments technique is given below：
1）Glass paste is inserted in the groove of diode chip for backlight unit with knife coating first, puts it into baking 30 in 90 DEG C of baking ovens
Minute, then sintering 30 minutes in 810 DEG C of sintering furnaces are pushed into, first time glass sintering is completed, glass model such as Fig. 2 institutes are formed by
Show.
2）Glass paste is inserted in diode chip for backlight unit groove with knife coating again, is placed in 200 DEG C of heating plates fast
Speed baking 3 minutes, then sintering 30 minutes in 810 DEG C of sintering furnaces are pushed into, second of glass sintering is completed, glass model is formed by
As shown in Figure 3.
3）Glass paste is coated in diode chip for backlight unit surface and groove using spin-coating method, is placed on 200 DEG C of heating
Quick baking 3 minutes on plate, then sintering 10 minutes in 500 DEG C of sintering furnaces are pushed into, complete third time glass sintering.
4）Photoresist is spun in diode chip for backlight unit surface and groove, the etching of diode chip for backlight unit boss is outputed by photoetching
Glass passivation layer in window is etched removal, then after removing diode chip for backlight unit surface residual photoresist, pushed it by window
Sintering 30 minutes in 810 DEG C of sintering furnaces, complete the 4th glass sintering, it is as shown in Figure 4 to be formed by final glass model.
The present invention is inserted glass paste in the groove of diode chip for backlight unit in the way of first time knife coating routine work, at this time
Thickness of glass in diode chip for backlight unit groove is thin and is mainly distributed on channel bottom, not can be well protected exposed on trenched side-wall
PN junction.It recycles second of knife coating to continue to insert glass paste in the groove of diode chip for backlight unit, increases in filling groove
The amount of glass paste, but conventional roasting mode is not used, but quickly glass paste is dried using heating plate high temperature, make
Glass paste in second of filling groove is mainly distributed on trenched side-wall, changes the glass model that traditional roasting mode is formed.
In this way, glass thickness can form the preferable protection to PN junction at trenched side-wall, channel bottom glass thin is also beneficial to follow-up diode
Chip cutting operation.
For mesa high-voltage diode chip, since diode chip for backlight unit boss surrounding forms point in etching process
Angle be easy to cause point discharge phenomenon when diode chip for backlight unit is powered, and influences the functional reliability of diode chip for backlight unit, so needing
The wedge angle of boss surrounding is protected.Glass paste is coated on diode chip for backlight unit boss by the present invention using spin-coating method, spin coating
Method keeps the glass paste of coating thicker, is conducive to the cladding to diode chip for backlight unit boss periphery closed angle, but remains in boss table simultaneously
The glass in face is also thicker, is unfavorable for the etching of glass in subsequent boss window.Therefore, the present invention is after spin coating glass slurry
The third time glass sintering temperature of progress is relatively low, prevents glass from reaching inversion point temperature, such sintering processing, favorably
In subsequently thicker glass etching in boss window is removed, the 4th glass sintering be only the glassy layer to being coated after spin coating into
Capable final sintering sizing.
Above example be only to illustrate the present invention preferred technique scheme and unrestricted, those of ordinary skill in the art couple
Other modifications or equivalent replacement that technical scheme of the present invention is made, without departing from the spirit and model of technical solution of the present invention
It encloses, should all cover in scope of the presently claimed invention.
Claims (3)
1. a kind of glass passivation process of diode chip for backlight unit, it is characterised in that：Include the following steps：
1）Glass paste is inserted in the groove of diode chip for backlight unit using knife coating, first time glass burning is carried out after being dried with baking oven
The baking temperature of knot, the baking oven is 90 ± 5 DEG C, and baking time is 30 ± 5 minutes；
2）Glass paste is inserted in the groove of diode chip for backlight unit with knife coating again, diode chip for backlight unit is directly then positioned over heating
On plate, second of glass sintering is carried out after high temperature flash baking, the baking temperature of the heating plate is 200 ± 20 DEG C, when baking
Between be 2~5 minutes；
3）Glass paste is spun and coated in diode chip for backlight unit surface and groove, diode chip for backlight unit is directly then positioned over heating
On plate, third time glass sintering is carried out after high temperature flash baking, the baking temperature of the heating plate is 200 ± 20 DEG C, when baking
Between be 2~5 minutes；
4）Photoresist is applied in diode chip for backlight unit surface and groove, diode chip for backlight unit boss etch window is outputed by photolithographicallpatterned
Mouthful, glass passivation layer in window is removed, then remove the photoresist in diode chip for backlight unit surface and groove, is finally carried out the 4th time
Glass sintering.
2. a kind of glass passivation process of diode chip for backlight unit according to claim 1, it is characterised in that：The first time,
Second, the 4th glass sintering temperature is 810 ± 5 DEG C, and sintering time is 30~40 minutes.
3. a kind of glass passivation process of diode chip for backlight unit according to claim 1, it is characterised in that：The third time glass
Glass sintering temperature is 500 ± 20 DEG C, and sintering time is 10~20 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510867849.3A CN105405758B (en) | 2015-12-02 | 2015-12-02 | A kind of glass passivation process of diode chip for backlight unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510867849.3A CN105405758B (en) | 2015-12-02 | 2015-12-02 | A kind of glass passivation process of diode chip for backlight unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105405758A CN105405758A (en) | 2016-03-16 |
| CN105405758B true CN105405758B (en) | 2018-08-07 |
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| CN201510867849.3A Active CN105405758B (en) | 2015-12-02 | 2015-12-02 | A kind of glass passivation process of diode chip for backlight unit |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309078B (en) * | 2017-07-26 | 2020-08-21 | 天津环鑫科技发展有限公司 | Silicon wafer photoetching process |
| CN108461381A (en) * | 2018-01-29 | 2018-08-28 | 郭光辉 | A kind of manufacture craft of semiconductor GPP rectification chips |
| CN110137077A (en) * | 2018-07-23 | 2019-08-16 | 扬州虹扬科技发展有限公司 | A kind of diode assembly groove polishing method |
| CN114171416B (en) * | 2022-02-14 | 2022-06-03 | 浙江里阳半导体有限公司 | TVS chip and glass passivation method and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4194934A (en) * | 1977-05-23 | 1980-03-25 | Varo Semiconductor, Inc. | Method of passivating a semiconductor device utilizing dual polycrystalline layers |
| CN201985106U (en) * | 2010-10-19 | 2011-09-21 | 上海美高森美半导体有限公司 | Composite inner passivation layer structure of transient voltage suppression diode |
| CN202384330U (en) * | 2011-12-29 | 2012-08-15 | 乐山嘉洋科技发展有限公司 | Glass passivated chip with multilayer protection |
-
2015
- 2015-12-02 CN CN201510867849.3A patent/CN105405758B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4194934A (en) * | 1977-05-23 | 1980-03-25 | Varo Semiconductor, Inc. | Method of passivating a semiconductor device utilizing dual polycrystalline layers |
| CN201985106U (en) * | 2010-10-19 | 2011-09-21 | 上海美高森美半导体有限公司 | Composite inner passivation layer structure of transient voltage suppression diode |
| CN202384330U (en) * | 2011-12-29 | 2012-08-15 | 乐山嘉洋科技发展有限公司 | Glass passivated chip with multilayer protection |
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| CN105405758A (en) | 2016-03-16 |
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