CN102130183A - 低压双向保护二级管 - Google Patents
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Abstract
一种垂直双向保护二极管,包括,在第一导电类型的重掺杂衬底上的第一、第二和第一导电类型的第一、第二和第三区域,这些区域的掺杂级都大于2到5x1019atoms/cm3,并且被绝缘沟道横向分隔,这些区域中的每一个区域的厚度都小于4μm。
Description
技术领域
本发明涉及一种低压双向保护二极管,也就是说,该二极管的双向击穿电压都小于10伏,优选地接近6伏。
背景技术
通常,当期望减小击穿电压时,更具体地说,当要获得对称二极管时,也就是说,该二极管具有接近于6到10伏基本上相等的击穿电压,用于构造双向保护二极管的各种技术都存在局限性。此外,已知的双向二极管通常会受到存在于两个偏置方向中的至少一个或另一个方向中的“阶跃恢复(Snapback)”现象的影响,也就是说,即使发生击穿的电压很小,例如,接近10伏,也会存在短暂的初始过电压,也就是说,二极管两端的电压上升到比基准值更大的值,例如,在退回到接近10伏的保护值之前,从12伏到14伏的值。
发明内容
因而,本发明一个实施例的主要目的是为了克服已知双向保护二极管的至少一部分缺点。
本发明一个实施例的另一个目的是为了提供双向都具有接近6伏的击穿电压的双向保护二极管。
本发明一个实施例的一个目的是为了提供一种自由阶跃恢复的双向保护二极管。
本发明一个实施例的一个目的是为了提供一种小型的双向保护二极管。
为了达到至少部分这些目的,本发明的一个实施例提供了一种垂直双向保护二极管,包括,在第一导电类型的重掺杂衬底上的第一、第二和第一导电类型的第一、第二和第三区域,这些区域的掺杂级都大于2到5x1019atoms/cm3,并且被绝缘沟道横向分隔,这些区域中的每一个区域的厚度都小于4μm。
根据本发明一个实施例,第二和第三区域由厚度小于4μm的外延层中的植入物形成。
根据本发明一个实施例,这些不同的区域分别是P型,N型和P型,第一区域的最大掺杂级近似5x1019atoms/cm3,第二区域的最大掺杂级近似1020atoms/cm3,第三区域的最大掺杂级近似5x1019atoms/cm3,每个区域的掺杂曲线的顶部间隔小于3μm。
本发明的一个实施例提供了一种用于制造垂直双向保护二极管的方法,包括以下步骤:
在重掺杂P型衬底中形成第一最重掺杂P型区域;
在该结构上形成第一外延层;
在第一外延层中形成第二重掺杂N型区域;
在该结构上形成第二外延层;
在第二外延层中形成第三重掺杂P型区域;
该结构四周围绕横越前述三个区域的绝缘沟道。
根据本发明一个实施例,最后两个步骤的顺序可以倒置。
根据本发明一个实施例,各种植入物的剂量范围在1到10x1016atoms/cm2之间。
结合附图将详细讨论本发明的前述目的,特征和优点,不限于具体实施例的描述。
附图说明
图1是说明根据本发明一个实施例的保护二极管的横截面视图;
图2示出了图1二极管一个例子的掺杂级;和
图3A至3F示出了用于制造根据本发明一个实施例的双向保护二极管的连续步骤。
具体实施方式
与通常对微型元件的表示相同,各种横截面视图不是按照实际比例绘制的,应当认为仅是示例说明的。
图1示出了一种垂直类型的二极管,包括,在P+型衬底1上面,分别是P++型、N++型和P++型的最重掺杂连续层3、4和5。这里的“最重掺杂”意味着掺杂级大于或等于5x1019atoms/cm3。衬底1的下表面覆盖有金属M1。层3,4和5的组件被具有绝缘边缘8的外围沟道7横向分隔,并且上层5覆盖有金属M2。由于PNP晶体管的N++底部的最重掺杂级,该晶体管的增益相当低,这抑制了阶跃恢复现象。同样应当注意该结构具有基本对称的形状。此外,有源结构被绝缘沟道环绕着的事实能够避免在其他类型结构中的组件边界上所会出现的任何边缘和交界弯曲的现象。
图2示出了图1结构所选择的掺杂级的一个例子。图2示出了根据e微米厚度变化的含量c(atoms/cm3)。已经标明了区域3,4和5的厚度e3,e4和e5。应当指出N++层4的厚度e4优选的近似2μm。实践上,范围是从1.5到3μm。类似地,每个交界处和每个P++区域3和5的最大掺杂区域之间的距离近似2μm,并且优选地在1到3μm范围之内。
衬底1被表示为具有的掺杂含量范围在1和2x1019atoms/cm3之间。实际上,这是可供销售的衬底的最高掺杂极限。当然,如果能够提供更高掺杂级的衬底,则P++层3是没有必要的。
图3A至3F说明了用于制造图1的双向保护二极管的方法的一个实施例的连续步骤。
如图3A所示,首先应尽可能地使P+衬底1重掺杂,例如,使其具有从1到2x1019atoms/cm3的掺杂级,这相当于5mΩ.cm的阻抗。
在衬底上,P型掺杂物,例如,硼,被在浅的深度植入尽可能大的剂量,例如,从1到10x1016atoms/cm2,以在该步骤结束时,在近2μm的厚度范围内达到的最大掺杂级近似5x1019atoms/cm3。优选地,区域3是局部的,也就是说,并没有扩展到整个衬底表面,其植入由掩模限定。
如图3B所示,已经完成了P或N型层14的外延,该外延具有的掺杂低于5x1018atoms/cm3并且厚度从1到3μm,例如,1.5μm。
如图3C所示,一种N型掺杂,例如,在区域3上面,砷按照1到10x1016atoms/cm2的剂量被局部地植入在外延层14中,从而在该层的较薄的厚度上达到的最大含量近似2x1020atoms/cm3。
如图3D所示,提供另一个外延层15,其具有的掺杂低于5x1018atoms/cm3并且厚度从2到5μm,例如,优选的是3.5μm。
如图3E所示,然后通过掩模施加一种P型掺杂的重植入物,例如,按照1到10x1016atoms/cm2剂量的硼,从而在这个层中达到的最大掺杂级近似1020atoms/cm3。
在图3F所示的步骤中,该结构被一个外围沟道7分隔。
然后执行下列常规步骤:使沟道壁绝缘,填充该沟道(例如,使用尽可能氧化的多晶硅),形成前表面金属M1,研磨衬底的后表面以获得厚度范围近似从50到200μm的结构,在形成后表面金属M2以获得图1所示的组件。
应当指出在图2的曲线中,厚的的起点对应于衬底1的表面,负的厚度对应于外延层。
本发明可能具有不同的变化。例如,图3E和3F的步骤顺序可以被倒置,也就是说,绝缘沟道可以在形成P++区域5的植入物完成之前形成。
本发明制造方法的一个优点在于以低功率在较小厚度的层内实现植入物,这能够限制缺陷的产生并且限制会破坏该结构的退火处理步骤。
能够看出这种二极管在金属M1和M2之间的两个偏置方向中具有近似6伏的击穿电压。通过改变离子植入物剂量来形成层3,4和5,该击穿电压可以被调整到更高值,例如,高达10v。所完成的检验说明不存在任何阶跃恢复现象。
已经描述了本发明的具体实施例。本领域技术人员应当清楚各种变化和改变。特别是关于所指示的数值和所使用的掺杂物的类型。
这种改变,修改和改进应当确定为本公开内容的一部分,并且确定属于本发明的精神和范围之内。因此,前述描述仅是示例性的并不意旨限制性的。本发明仅由下述权利要求及其等同物来限定。
Claims (6)
1.一种垂直双向保护二极管,其包括,在第一导电类型的重掺杂衬底(1)上的第一、第二和第一导电类型的第一(3)、第二(4)和第三(5)区域,这些区域的掺杂级都大于2到5x1019atoms/cm3,并且被绝缘沟道(7)横向分隔,这些区域中的每一个区域的厚度都小于4μm。
2.根据权利要求1的双向保护二极管,其中第二和第三区域由厚度小于4μm的外延层中的植入物形成。
3.根据权利要求1的双保护向二极管,其中这些不同的区域分别是P型、N型和P型,第一区域的最大掺杂级近似为5x1019atoms/cm3,第二区域的最大掺杂级近似为1020atoms/cm3,以及第三区域的最大掺杂级近似为5x1019atoms/cm3,每个区域的掺杂曲线的顶部间隔小于3μm。
4.一种用于制造垂直双向保护二极管的方法,其包括以下步骤:
在重掺杂P型衬底(1)中形成第一最重掺杂P型区域(3);
在该结构上形成第一外延层(14);
在第一外延层(14)中形成第二重掺杂N型区域(4);
在该结构上形成第二外延层(15);
在第二外延层(15)中形成第三重掺杂P型区域(5);和
该结构四周围绕横越前述三个区域的绝缘沟道。
5.根据权利要求4的方法,其中最后两个步骤的顺序可以倒置。
6.根据权利要求4的方法,其中完成重掺杂区域的植入物的剂量范围在1到10x1016atoms/cm2之间。
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FR0958323A FR2953062B1 (fr) | 2009-11-24 | 2009-11-24 | Diode de protection bidirectionnelle basse tension |
FR0958323 | 2009-11-24 |
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US8288839B2 (en) | 2009-04-30 | 2012-10-16 | Alpha & Omega Semiconductor, Inc. | Transient voltage suppressor having symmetrical breakdown voltages |
FR2960097A1 (fr) * | 2010-05-11 | 2011-11-18 | St Microelectronics Tours Sas | Composant de protection bidirectionnel |
US8664080B2 (en) * | 2011-05-25 | 2014-03-04 | Texas Instruments Incorporated | Vertical ESD protection device |
US8698196B2 (en) * | 2011-06-28 | 2014-04-15 | Alpha And Omega Semiconductor Incorporated | Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage |
US9059324B2 (en) | 2013-06-30 | 2015-06-16 | Texas Instruments Incorporated | Bi-directional ESD diode structure with ultra-low capacitance that consumes a small amount of silicon real estate |
CN108598078B (zh) * | 2018-07-11 | 2024-06-04 | 上海艾为电子技术股份有限公司 | 一种esd保护电路及电子装置 |
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JP5073933B2 (ja) * | 2005-09-27 | 2012-11-14 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
US7666751B2 (en) * | 2007-09-21 | 2010-02-23 | Semiconductor Components Industries, Llc | Method of forming a high capacitance diode and structure therefor |
US7842969B2 (en) * | 2008-07-10 | 2010-11-30 | Semiconductor Components Industries, Llc | Low clamp voltage ESD device and method therefor |
US7812367B2 (en) * | 2008-10-15 | 2010-10-12 | Semiconductor Components Industries, Llc | Two terminal low capacitance multi-channel ESD device |
US8288839B2 (en) * | 2009-04-30 | 2012-10-16 | Alpha & Omega Semiconductor, Inc. | Transient voltage suppressor having symmetrical breakdown voltages |
-
2009
- 2009-11-24 FR FR0958323A patent/FR2953062B1/fr not_active Expired - Fee Related
-
2010
- 2010-10-27 EP EP10189069.7A patent/EP2325893B1/fr active Active
- 2010-11-16 US US12/946,992 patent/US8536682B2/en active Active
- 2010-11-18 CN CN201010561335.2A patent/CN102130183B/zh active Active
Patent Citations (4)
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US4405932A (en) * | 1979-12-26 | 1983-09-20 | Hitachi, Ltd. | Punch through reference diode |
US6459133B1 (en) * | 1999-04-08 | 2002-10-01 | Koninklijke Phillips Electronics N.V. | Enhanced flux semiconductor device with mesa and method of manufacturing same |
CN1605127A (zh) * | 2001-07-11 | 2005-04-06 | 通用半导体公司 | 具有表面击穿保护的低压穿通双向瞬态电压抑制器件及其制造方法 |
CN101506974A (zh) * | 2006-11-30 | 2009-08-12 | 万国半导体股份有限公司 | 利用沟槽隔离形成的无闭锁垂直瞬态电压抑制二极管阵列结构 |
Also Published As
Publication number | Publication date |
---|---|
EP2325893A2 (fr) | 2011-05-25 |
EP2325893A3 (fr) | 2014-03-26 |
CN102130183B (zh) | 2016-03-16 |
EP2325893B1 (fr) | 2015-04-15 |
FR2953062A1 (fr) | 2011-05-27 |
US8536682B2 (en) | 2013-09-17 |
FR2953062B1 (fr) | 2011-12-16 |
US20110121429A1 (en) | 2011-05-26 |
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