CN102117774B - 集成电路元件的形成方法 - Google Patents
集成电路元件的形成方法 Download PDFInfo
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- CN102117774B CN102117774B CN201010212841.0A CN201010212841A CN102117774B CN 102117774 B CN102117774 B CN 102117774B CN 201010212841 A CN201010212841 A CN 201010212841A CN 102117774 B CN102117774 B CN 102117774B
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Abstract
本发明提供一种形成集成电路元件的方法,该方法包括提供基板,具有第一区、第二区、及第三区;以及分别形成第一栅极结构于第一区中、第二栅极结构于第二区中、及第三栅极结构于第三区中。第一、第二及第三栅极结构包括栅极介电层,且栅极介电层分别具有第一厚度、第二厚度、及第三厚度。上述形成第一、第二及第三厚度的栅极介电层的步骤包括当形成第一、第二及第三栅极结构时,形成蚀刻阻挡层于第一、第二及第三区三者中至少一者的栅极介电层上;和/或在形成栅极结构于第一、第二及第三区三者中至少一者中之前,先进行注入工艺于第一、第二及第三区三者中至少一者上。本发明可减少有源区氧化层蚀刻的次数。
Description
技术领域
本发明涉及集成电路元件的形成方法,更特别涉及形成具有不同厚度的栅极介电层的集成电路元件。
背景技术
半导体集成电路产业已快速成长一段时日。在集成电路进步的过程中,其功能密度(每单位面积的芯片具有的内连线元件数目)越来越大,而其尺寸(工艺所能形成的最小元件或连线)则越来越小。工艺尺寸缩小有益于提高工艺效率及相关成本。然而上述进步也会增加集成电路工艺及生产的复杂性,为使进步易于了解,集成电路工艺的发展需类似的生产方法及发展。
发明内容
为克服上述现有技术的缺陷,本发明提供一种集成电路元件的形成方法,其中集成电路元件包含不同厚度的栅极介电层,包括提供基板,基板具有第一区、第二区、及第三区;形成第一栅极结构于第一区中,其中第一栅极结构包括具有第一厚度的第一栅极介电层、阻挡层、及虚置栅极层;形成第二栅极结构于第二区中,其中第二栅极结构包括虚置栅极介电层及虚置栅极层;形成第三栅极结构于第三区中,其中第三栅极结构包括虚置栅极介电层及虚置栅极层;移除第一区、第二区、及第三区的虚置栅极层,以形成开口于第一栅极结构、第二栅极结构、及第三栅极结构中;进行注入工艺于第二区;移除第二栅极结构与第三栅极结构的虚置栅极介电层;形成界面介电层以填入第二栅极结构与第三栅极结构的部分开口,其中第二栅极结构的界面介电层具有第二厚度,而第三栅极结构的界面介电层具有第三厚度;以及形成高介电常数介电层栅极于第一栅极结构、第二栅极结构、及第三栅极结构的开口中。
本发明也提供一种形成集成电路元件的方法,包括提供基板,基板具有第一区、第二区、及第三区;以及形成第一栅极结构于第一区中、第二栅极结构于第二区中、及第三栅极结构于第三区中,其中第一栅极结构、第二栅极结构、及第三栅极结构包括栅极介电层,且第一区、第二区、及第三区的栅极介电层分别具有第一厚度、第二厚度、及第三厚度;其中形成第一厚度、第二厚度、及第三厚度的栅极介电层的步骤包括当形成第一栅极结构、第二栅极结构、及第三栅极结构时,形成蚀刻阻挡层于第一区、第二区、及第三区三者中至少一者的栅极介电层上;以及在形成栅极结构于第一区、第二区、及第三区三者中至少一者中之前,先进行注入工艺于第一区、第二区、及第三区三者中至少一者上。
本发明更提供一种集成电路元件的形成方法,其中集成电路元件包含不同厚度的栅极介电层,包括提供基板,基板具有第一区、第二区、及第三区;形成具有第一厚度的第一栅极介电层于第一区中;形成阻挡层于第一栅极介电层上;形成虚置栅极介电层于第二区及第三区中;形成虚置栅极层于阻挡层及虚置栅极介电层上;进行栅极图案化工艺以形成栅极结构于第一区、第二区、及第三区中;移除第一区、第二区、及第三区的栅极结构的虚置栅极层,以形成开口于第一区、第二区、及第三区的栅极结构中;进行注入工艺于第二区或第三区;移除第二区及第三区的栅极结构中的虚置栅极介电层;以及将界面层填入第二区及第三区的栅极结构的部分开口,其中第二区中的界面层具有第二厚度,而第三区中的界面层具有第三厚度。
本发明主要的好处在于,可减少有源区氧化层蚀刻的次数,降低缺角(divot)的深度;可同时于第二及第三区形成栅极氧化层,减少热工艺的次数,并降低其对源/漏极接面深度的影响。此外,无黄光工艺接触第二或第三区的栅极氧化层,可增加核心电路元件氧化层的可靠。
附图说明
图1是本发明一实施例中集成电路元件的制备方法的流程图;以及
图2A-图2K是对应图1中不同步骤的集成电路元件剖视图。
其中,附图标记说明如下:
100~方法;102、104、106、108、110、112、114、116、118、120、122、124、126~步骤;200~半导体元件;210~基板;211A~高功率区、211B~低功率区;211C~中间核心区;212~绝缘区;214~栅极介电层;216~蚀刻阻挡层;218~虚置栅极介电层;220~虚置栅极层;222~侧壁间隔物;223~掺杂区;224~层间介电层;226~图案化层;228~注入工艺;230~注入区;234~高介电常数介电层;236~阻挡层。
具体实施方式
可以理解的是,下述内容提供多种实施例以说明本发明的多种特征。为了简化说明,将采用特定的实施例、单元、及组合方式说明。然而这些特例并非用以限制本发明。举例来说,形成某一元件于另一元件上包含了两元件为直接接触,或者两者间隔有其他元件这两种情况。此外为了简化说明,本发明在不同图示中采用相同标记标示不同实施例的类似元件,但上述重复的标记并不代表不同实施例中的元件具有相同的对应关系。
接下来将根据图1的方法100搭配图2A-图2K的半导体元件200进行说明。半导体元件200是整体或部分的集成电路,可包含逻辑电路/元件、存储单元/元件如SRAM、射频元件、输入/输出元件、系统单芯片(SoC)元件、特用集成电路(ASIC)元件、其他适当元件、和/或上述的组合。半导体元件200可包含无源单元如电阻、电容、电感、和/或保险丝,或有源单元如p型沟道场效应晶体管(PFET)、n型沟道场效应晶体管(NFET)、金属氧化物半导体场效应晶体管(MOSFET)、互补式金属氧化物半导体晶体管(CMOS)、高压晶体管、和/或高频晶体管,其他合适单元,和/或上述的组合。可以理解的是,在方法100之前、之中、或之后可采用其他步骤。在其他实施例中,可置换或省略方法100的部分步骤。可以理解的是,半导体元件200可进一步添加其他结构。在其他实施例中,可置换或省略半导体元件200的部分结构。
图1是形成半导体元件200的方法100的流程图。图2A-图2K是对应图1中不同步骤的半导体元件剖视图。经由方法100,可使半导体元件200具有不同厚度的栅极介电层。换句话说,经由方法100形成的半导体元件200其栅极介电层可具有不同厚度和/或不同材质。这对系统单芯片(SoC)或特用集成电路(ASIC)的技术格外有利。可以理解的是,不同实施例将具有不同优点,任一实施例的特色并不需强加于其他实施例。可以理解的是,半导体元件200可由CMOS工艺形成,部分工艺并不会完整交待于后叙篇幅中。
如图1及图2A所示,方法100的步骤102提供基板210。在此实施例中,基板210为半导体基板如硅。此外,基板210包含半导体元素如结晶硅和/或结晶锗;半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、和/或锑化铟;半导体合金如硅锗化物、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、和/或磷砷化镓铟;或上述的组合。半导体合金基板如硅锗化物可具有梯度浓度,其中某处的硅与锗具有一特定比例,另一处的硅与锗具有另一特定比例,两处之间的硅与锗的比例渐增或渐减。硅锗合金可形成于硅基板上。硅锗基板可具有应力。此外,半导体基板可为绝缘层上硅(SOI)。在某些实施例中,半导体基板可包含掺杂的外延层。在其他实施例中,硅基板可含有多层的半导体化合物结构。
视情况需要,基板210可含有不同的掺杂区如p型阱区或n型阱区。掺杂区可掺杂p型杂质如硼或BF2、n型杂质如磷或砷、或上述的组合。掺杂区可直接形成于基板210上、p型阱区中、n型阱区中、双阱区结构、或隆起结构。基板210可更包含多种有源区如n型金属氧化物半导体晶体管(NMOS)元件区或p型金属氧化物半导体晶体管(PMOS)元件区。
基板210包含绝缘区212以分隔绝缘基板210的不同区域如图2A所示的第一区、第二区、及第三区。在此实施例中,绝缘区212可分隔高功率区211A(也称为输入/输出区或第一元件区)、低功率区211B(也称为第二元件区)、及中间核心区211C(也称为第三元件区)。绝缘区212用以定义并电性绝缘不同区域,其形成方式可为局部氧化硅(LOCOS)或浅沟槽绝缘(STI)。绝缘区212的材料可为氧化硅、氮化硅、氮氧化硅、其他合适材料、或上述的组合。绝缘区212可由任何合适工艺形成。举例来说,浅沟槽绝缘工艺包含光刻工艺、以干蚀刻和/或湿蚀刻等方式蚀刻基板以形成沟槽、以及以化学气相沉积等方法将一或多种介电材料填入沟槽。在部分实施例中,填入沟槽的材料可为多层结构,如先形成热氧化衬垫层,再填入氮化硅或氧化硅。
如前所述,半导体元件200包含三个元件:位于高功率区211A(第一元件区)的第一元件、位于低功率区211B(第二元件区)的第二元件、以及位于中间核心区211C(第三元件区)的第三元件。在此实施例中,第一、第二、及第三元件包含具有栅极介电层的栅极结构。综上所述,半导体元件200可称为三栅极晶体管元件。上述第一、第二、及第三元件具有不同厚度的栅极介电层。举例来说,高功率区211A的第一元件具有第一厚度(等效氧化物厚度,简称EOT)的栅极介电层,即最厚的栅极介电层。低功率区211B的第二元件具有第二厚度的栅极介电层,即中等EOT的栅极介电层,其厚度介于第一元件及第二元件的栅极介电层厚度之间。中间核心区211C的第三元件具有第三厚度的栅极介电层,即最薄EOT的栅极介电层。本发明揭示一种工艺,可使上述不同区域的栅极介电层具有不同厚度和/或不同材质。上述不同厚度的栅极介电层可避免元件信赖度和/或栅极氧化层厚度相同的问题。上述实施例的元件区仅用以举例,而半导体元件200可包含上述元件区的组合和/或其他多种元件区。相同地,不同元件区中的栅极介电层各自具有不同厚度。
如图2B及步骤104所示,将具有第一厚度的栅极介电层214形成于基板210上。栅极介电层214(又称第一栅极介电层)可为高功率区211A(又称第一元件区)的栅极介电层。高功率区211A的第一元件的栅极介电层,一般为半导体元件200中最厚的栅极介电层。如此一来,栅极介电层214的厚度可符合元件需求,以负荷高压元件如高压晶体管的操作电压。
在此实施例中,栅极介电层214包含氧化物材料如氧化硅。此外,栅极介电层214包含任何合适介电材料如氮化硅、氮氧化硅、其他合适的介电材料、和/或上述的组合。栅极介电层214的形成方式可为任何合适工艺如化学气相沉积(CVD)、原子层沉积(ALD)、等离子体增强式CVD(PECVD)、等离子体增强式ALD(PEALD)、其他合适工艺、和/或上述的组合。此外,栅极介电层214可由热成长法形成,如热氧化工艺。
在步骤106中,形成适当厚度的蚀刻阻挡层216于栅极介电层214上。蚀刻阻挡层216可包含氮化物材料。举例来说,氮化物是氮化硅层和/或氮化层。当蚀刻阻挡层216为氮化硅时,其形成方法可为任何合适工艺如CVD、ALD、PECVD、PEALD、其他合适工艺、和/或上述的组合。当蚀刻阻挡层216为氮化层时,其形成方法可为任何合适工艺如利用氨气的热氮化法。在另一实施例中,氮化层的形成方法可为等离子体氮化工艺。在又一实施例中,氮化层的形成方法可为临场注入工艺。在后续讨论中,蚀刻阻挡层216可保护栅极介电层214(如第一元件中具有第一厚度的第一栅极介电层)免于后续工艺如虚置栅极移除工艺的损害。蚀刻阻挡层216也可保护氧化材质的栅极介电层免于损害。
在步骤108中,将移除低电压区211B及中间核心区211C的栅极介电层214及蚀刻阻挡层216,如图2C所示。上述移除特定区域的栅极介电层214及蚀刻阻挡层216的方法可为适当工艺,如光刻图案化及蚀刻等工艺。光刻图案化工艺包含涂布光致抗蚀剂如旋涂法、软烘烤、对准光掩模、曝光、曝光后烘烤、显影、冲洗、干燥如硬烘烤、其他合适工艺、或上述的组合。此外,光刻的曝光工艺可改用其他方法如无光掩模光刻、电子束直写、和/或离子束直写。蚀刻工艺包含干蚀刻、湿蚀刻、和/或其他蚀刻方法。在一实施例中,先以适当工艺如旋涂法形成光致抗蚀剂层于蚀刻阻挡层216上,接着图案化光致抗蚀剂层。接着可采用干蚀刻工艺,将光致抗蚀剂层露出或未露出蚀刻阻挡层216的图案,转移至下层如蚀刻阻挡层216及栅极介电层214。举例来说,未露出的蚀刻阻挡层216位于高功率区211A,而露出的蚀刻阻挡层216位于低功率区211B及中间核心区211C。接着以适当工艺移除露出的蚀刻阻挡层216及其下的栅极介电层214,即移除低功率区211B及中间核心区211C的栅极介电层214及蚀刻阻挡层216。之后再剥除残留于高功率区211A的光致抗蚀剂层。
在步骤110中,形成虚置栅极介电层218于基板210上。如图2D所示,上述虚置栅极介电层218特别形成于低功率区211B及中间核心区211C上。虚置栅极介电层218可为任何合适材料。举例来说,虚置栅极介电层218可包含氧化物材料。虚置栅极介电层218的形成方法可为任何合适工艺如热氧化法、CVD、ALD、PECVD、PEALD、其他合适工艺、和/或上述的组合。在形成虚置栅极介电层218的过程中,蚀刻阻挡层216可避免高功率区211A的第一元件的栅极介电层214其厚度受到影响,并确保上述区域的栅极介电层214维持其厚度(如第一厚度)。
在步骤112中,形成虚置栅极层220于基板210上。虚置栅极层220也可称之为虚置栅极。如图2E所示,沉积虚置栅极层220于栅极介电层214、蚀刻阻挡层216、及虚置栅极介电层218上的方法可为物理气相沉积(PVD)或CVD等工艺。上述虚置栅极层220的形成方法也可采用其他沉积工艺。在此例中,虚置栅极层220包括多晶硅或非晶硅。虚置栅极层220可包含其他合适材料。
在步骤114中,进行栅极图案化工艺以形成高功率区211A、低功率区211B、及中间核心区211C的栅极结构。以图2F为例,于高功率区211A、低功率区211B、及中间核心区211C形成栅极结构的方法可为适当工艺,如图案化及蚀刻等工艺。每一栅极结构包含栅极堆叠,如栅极介电层214、蚀刻阻挡层216、虚置栅极介电层218、和/或虚置栅极层220。在此实施例中,基板210上的高功率区211A的第一栅极结构包含栅极介电层214、蚀刻阻挡层216、及虚置栅极层220;基板210上的低功率区211B的第二栅极结构包含虚置栅极介电层218及虚置栅极层220;基板210上的中间核心区211C的第三栅极结构包含虚置栅极介电层218及虚置栅极层220。可以理解的是,上述栅极堆叠可包含其他层。
在一实施例中,可采用适当工艺如旋涂法将光致抗蚀剂层形成于虚置栅极层220上,接着形成图案化光致抗蚀剂结构。之后以干蚀刻工艺将光致抗蚀剂层的图案转移至其下的层状结构,如栅极介电层214、蚀刻阻挡层216、虚置栅极介电层218、及虚置栅极层220,以形成高功率区211A、低功率区211B、及中间核心区211C的栅极结构的栅极堆叠。接着剥除光致抗蚀剂层。在另一实施例中,先形成硬掩模层于虚置栅极层上;形成图案化光致抗蚀剂层于硬掩模层上;将光致抗蚀剂层的图案转移至硬掩模层,再转移至虚置栅极层(及其下的层状结构)以形成栅极结构的栅极堆叠。可以理解的是,上述例子并未限制本发明不可采用其他形成栅极堆叠的工艺步骤。
上述栅极结构可进一步包含侧壁间隔物222于栅极堆叠的侧壁上,其形成方法可为任何合适工艺,其厚度可为任何合适厚度。侧壁间隔物222位于栅极堆叠的每一侧壁上,其组成可为任何合适材料。在不同实施例中,侧壁间隔物222包含介电材料如氮化硅、碳化硅、氮氧化硅、其他合适材料、和/或上述的组合。侧壁间隔物222可用以定义后续形成的掺杂区如重掺杂源极/漏极区。在形成侧壁间隔物时,可同时形成其他结构如密封层和/或侧壁衬垫层。
多种掺杂区223也可形成于基板210中。举例来说,掺杂区223包含轻掺杂源极/漏极区(LDD)和/或源极/漏极区(也称之为重掺杂源极/漏极区),其形成方法可为一或多重的注入工艺、光刻工艺、扩散工艺、和/或其他合适工艺。掺杂区223的杂质及掺杂型态端视元件需要而定。上述杂质包含p型杂质如硼或BF2、n型杂质如磷或砷、或上述的组合。LDD及源极/漏极区可包含多种掺杂轮廓。LDD的形成顺序可在侧壁间隔物222之前。源极/漏极区的形成顺序可在侧壁间隔物222之后,使其一或多重注入工艺对准侧壁间隔物222的边缘。此外,可进行一或多重回火工艺以活化LDD和/或源极/漏极区。上述回火工艺包含快速热回火工艺和/或激光回火工艺。在部分实施例中,源极/漏极区可包含隆起区域,其形成方式可为一或多重外延工艺,以形成结晶态的硅锗合金和/或硅结构于基板210上。其他材料结构也可应用于上述隆起区域。外延工艺可为CVD技术如气相外延和/或超真空CVD(UHV-CVD)、分子束外延、和/或其他合适工艺。外延工艺可采用气相和/或液相前驱物,以与基板210的材质如硅产生作用力。
接着可形成一或多个接触结构如金属硅化物区。可耦合至源极/漏极区的接触结构包含金属硅化物如镍硅化物、镍铂硅化物、镍铂锗硅化物、镍锗硅化物、钇硅化物、铂硅化物、铱硅化物、铒硅化物、钴硅化物、其他合适金属硅化物材料、和/或上述的组合。接触特征的形成方式可为任何合适工艺,如自我对准金属硅化工艺。举例来说,可先沉积金属材料于基板上,如基板的硅区和/或掺杂区。接着进行金属硅化工艺,使沉积的金属材料与硅区持续反应,其反应温度取决于金属材料种类。接着移除未反应的金属材料。最后可额外加热反应形成的金属硅化物,以降低其电阻。
接着可形成层间介电层(ILD)224于基板210上。层间介电层224包含任何合适材料如氧化硅、氮化硅、氮氧化硅、四乙氧硅烷形成的氧化物、其他合适介电材料、和/或上述的组合。此外,层间介电层224包含低介电常数的介电材料如氟掺杂硅酸盐玻璃(FSG)、碳掺杂氧化硅、Black (购自美国加州的Santa Clara公司)、干凝胶、气胶、非晶氟化碳、聚对二甲苯、双苯并环丁烷(BCB)、SiLK(购自美国密西根州的密德兰的Dow Chemical)、聚酰亚胺、其他合适材料、和/或上述的组合。层间介电层224可为高深宽比工艺(HARP)和/或高密度等离子体沉积(HDP)工艺形成的氧化层。层间介电层224的形成方法可为其他合适工艺如CVD、高密度等离子体CVD、溅镀、和/或其他合适方法。层间介电层224可为含有多种介电材料的多层结构。此外,可形成其他层于层间介电层224之上和/或之下。接着可进行一或多重化学机械研磨工艺(CMP)平坦化层间介电层224。举例来说,可进行CMP直到露出第一元件、第二元件、及第三元件的虚置栅极层220,如图2F所示。
如图1的步骤116及图2G所示,移除高功率区211A、低功率区211B、及中间核心区211C的栅极结构的虚置栅极层220,以形成开口(或沟槽)于栅极结构中。移除虚置栅极层220的方法可为任何合适工艺。举例来说,虚置栅极层220的移除方法包含一或多重蚀刻工艺,如湿蚀刻工艺、干蚀刻工艺、和/或上述的组合。在此实施例中,虚置栅极层220可由采用氨水和/或稀盐酸溶液的湿蚀刻工艺移除。
在步骤118中,于低功率区211B进行注入工艺。上述步骤更以光刻及图案化工艺形成具有适当厚度的图案化层226于基板上。如图2H所示,图案化层226形成于高功率区211A及中间核心区211C上,以保护上述区域的第一元件及第二元件免于受到低功率区211B的注入工艺影响。图案化层226包含光致抗蚀剂层和/或硬掩模层。光致抗蚀剂层可为正型或负型光致抗蚀剂。举例来说,光致抗蚀剂层包含化学增强(CA)光致抗蚀剂。硬掩模层包含任何合适材料如氮化硅、氮氧化硅、碳化硅、碳氧化硅、旋涂玻璃、和/或其他合适材料。
当进行注入工艺228于露出的低功率区211B时,杂质将穿过低功率区211B的栅极结构的开口(沟槽)的基板表面,以形成注入区230。注入工艺228可采用任何合适杂质。在此实施例中,杂质可为铟、氩、硅、和/或氟。注入工艺228包含任何合适的注入剂量和/或能量。注入工艺228可用以提升注入区230在后续工艺的氧化速率。上述注入工艺可影响注入区的氧化速率,因此低功率区211B及中间核心区211C后续形成的栅极介电层将具有不同的厚度。在此实施例中,当形成栅极介电层于低功率区211B及中间核心区211C时,低功率区211B的栅极介电层厚度(第二厚度)将大于中间核心区的栅极介电层厚度(第三厚度)。上述厚度差异的成因为注入工艺228形成的注入区230的氧化速率较高。在形成注入区230后,可移除图案化层226。
在步骤120中,将移除位于低功率区211B及中间核心区211C的栅极结构的开口(沟槽)中的虚置栅极介电层218,如图2I所示。移除虚置栅极介电层218的方法可为任何合适工艺,如各式蚀刻工艺。举例来说,可用气体工艺和/或含有稀氢氟酸的湿式蚀刻工艺移除虚置栅极介电层218。在移除工艺中,蚀刻阻挡层216可保护高功率区211A的第一元件的栅极介电层214(具有第一厚度)免于上述移除工艺影响。这是因为蚀刻阻挡层216可增加虚置栅极介电层218与栅极介电层214/蚀刻阻挡层216之间的蚀刻选择性。如此一来,蚀刻工艺可选择性地较快移除虚置栅极介电层218(如氧化物材料),并较慢移除蚀刻阻挡层216(如氮化物材料)。举例来说,氮化物/氧化物的蚀刻选择比可大于3。上述蚀刻工艺可部分或完全地移除蚀刻阻挡层216。
在步骤122中,形成界面层232B及232C于半导体元件200的栅极结构的开口(沟槽)中。界面层322B及232C的形成方法可为任何合适工艺,其厚度也可为任何合适厚度。举例来说,界面层232B及232C包含成长氧化硅层如热氧化层或化学氧化层。界面层232B及232C可为原始氧化层。在另一例中,界面层232B及232C可为ALD或CVD等工艺沉积的氧化层。此外,界面层232B及232C包含其他合适的介电材料层如氮氧化硅。
形成于低功率区211B及中间核心区211C的界面层232B及232C,是作为第二元件及第三元件的栅极介电层。界面层232B及232C部分填入低功率区211B及中间核心区211C的栅极结构的开口(沟槽)中。如图2J所示,位于低功率区211B的界面层B(也称之为栅极介电层)具有第二厚度,而中间核心区232C的界面层C(也称之为栅极介电层)具有第三厚度,两者的厚度不同。必需注意的是,第三元件的栅极介电层为三种元件区中最薄的栅极介电层,因此界面层232B比界面层232C厚。上述界面层的厚度差异来自于注入工艺所造成的不同氧化速率,这将使两种元件区具有不同的沟道氧化增强条件。
在此实施例中,部分的蚀刻阻挡层216仍保留于高功率区211A的第一元件的栅极结构中。保留的蚀刻阻挡层216可作为高功率区211A的第一元件其栅极堆叠的界面层。由于蚀刻阻挡层216可避免栅极介电层214受到前述工艺的影响,高功率区211A的第一元件的栅极介电层可保持其厚度。如此一来,高功率区211A的栅极介电层214可维持第一厚度,即三种元件区域中最厚的栅极介电层厚度。
在步骤124及图2K中,可形成高介电常数介电层234于半导体元件200的栅极结构的开口(沟槽)中。高功率区211A、低功率区211B、及中间核心区211C的栅极结构的部分开口(沟槽)填入高介电常数介电层234。在高介电常数介电层234上可形成阻挡层(盖层)236。高介电常数介电层234及阻挡层236可由任何合适工艺形成,且具有任何合适厚度。高介电常数介电层234包含高介电常数的介电材料如氧化铪、氧化铪硅、氮氧化铪硅、氧化铪钽、氧化铪钛、氧化铪锆、氧化镧、氧化铝、氧化锆、氧化钛、氧化钽、氧化钇、氧化锶钛(STO)、氧化钛钡(BTO)、氧化锆钡、氧化镧铪、氧化硅镧、氧化硅铝、氧化钛钡/锶(BST)、氧化铝、氮化硅、氮氧化物、其他合适的高介电常数介电材料、和/或上述的组合。阻挡层236包含适当材料如钛、氮化钛、钽、氮化钽、其他合适材料、和/或上述的组合。
在步骤126中,可进行后续工艺如下。举例来说,可形成金属栅极于高功率区211A的第一元件、低功率区211B的第二元件、及中间核心区211C的第三元件中。金属栅极可填入高功率区211A、低功率区211B、及中间核心区211C的栅极结构的开口中。金属栅极可由任何合适工艺形成,且具有任何合适厚度。举例来说,金属栅极的形成方法可为ALD,CVD或PVD。接着可进行一或多重CMP工艺以平坦化金属栅极及高介电常数介电层234(和/或阻挡层236)。可以理解的是,上述方法可形成n型金属及p型金属结构。如此一来,在形成金属栅极结构时,可形成n/p型图案以分隔不同型的元件,反之亦然。金属栅极可进一包包含衬垫层、工作函数层、填充层、其他合适的层、和/或上述的组合。
每一元件的金属栅极包含相同或不同的材料和/或厚度。金属栅极包含工作函数材料及额外的导电材料。工作函数层及导电层包含任何合适的材料如铝、铜、钨、钛、钽、氮化钛、氮化钽、镍硅化物、钴硅化物、银、碳化钽、氮化硅钽、氮化碳钽、钛铝合金、氮化铝钛、氮化钨、金属合金、多晶硅、其他合适材料、和/或上述的组合。NMOS元件的工作函数层包含氮化钽、钛铝合金、氮化钛铝、或上述的组合。PMOS元件的工作函数层包含钨、氮化钛、氮化钨、或上述的组合。
半导体元件200接着可进行其他CMOS或MOS工艺以形成公知技术已知的其他特征。后续工艺可形成额外接触物、多种导孔/导线、以及多层内连线结构(如金属层及层间介电层)于基板210上,以连接半导体元件的多种结构。额外结构可电性连接元件如已形成的金属栅极结构。举例来说,多层内连线包含垂直内连线如公知导孔或接触物,以及水平内连线如金属连线。多种内连线结构可采用多种导电材料如铜、钨、和/或金属硅化物。在一实施例中,可采用镶嵌和/或双镶嵌工艺形成铜相关的多层内连线结构。
虽然本发明已以数个优选实施例揭示如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (10)
1.一种集成电路元件的形成方法,其中集成电路元件包含不同厚度的栅极介电层,包括:
提供一基板,该基板具有一第一区、一第二区、及一第三区;
形成一第一栅极结构于该第一区中,其中该第一栅极结构包括一具有第一厚度的第一栅极介电层、一阻挡层、及一虚置栅极层;
形成一第二栅极结构于该第二区中,其中该第二栅极结构包括一虚置栅极介电层及一虚置栅极层;
形成一第三栅极结构于该第三区中,其中该第三栅极结构包括一虚置栅极介电层及一虚置栅极层;
移除该第一区、该第二区、及该第三区的该虚置栅极层,以形成开口于该第一栅极结构、该第二栅极结构、及该第三栅极结构中;
进行一注入工艺于该第二区;
移除该第二栅极结构与该第三栅极结构的该虚置栅极介电层;
形成一界面介电层以填入该第二栅极结构与该第三栅极结构的部分开口,其中该第二栅极结构的界面介电层具有一第二厚度,而第三栅极结构的界面介电层具有一第三厚度;以及
形成栅极于该第一栅极结构、该第二栅极结构、及该第三栅极结构的开口中。
2.如权利要求1所述的集成电路元件的形成方法,其中进行该注入工艺于该第二区的步骤中,该注入工艺的杂质择自下列群组之一:铟、氩、硅、氟、及上述的组合。
3.如权利要求1所述的集成电路元件的形成方法,其中形成具有该阻挡层的该第一栅极结构的步骤,包括形成一氮化层于具有第一厚度的该第一栅极介电层上。
4.如权利要求1所述的集成电路元件的形成方法,其中形成栅极于该第一栅极结构、该第二栅极结构、及该第三栅极结构的开口中的步骤,包括将高介电常数材料层及导电层填入该第一栅极结构、该第二栅极结构、及该第三栅极结构的开口中。
5.一种形成集成电路元件的方法,包括:
提供一基板,该基板具有一第一区、一第二区、及一第三区;以及
形成一第一栅极结构于该第一区中、一第二栅极结构于该第二区中、及一第三栅极结构于该第三区中,其中该第一栅极结构、该第二栅极结构、及该第三栅极结构包括一栅极介电层以及虚置栅极,且该第一区、该第二区、及该第三区的栅极介电层分别具有第一厚度、第二厚度、及第三厚度;
其中形成第一厚度、第二厚度、及第三厚度的栅极介电层的步骤包括:
当形成该第一栅极结构、该第二栅极结构、及该第三栅极结构时,形成一蚀刻阻挡层于该第一区、该第二区、及该第三区三者中至少一者的该栅极介电层上;以及
在形成栅极结构于该第一区、该第二区、及该第三区三者中至少一者中之前,先进行一注入工艺于该第一区、该第二区、及该第三区三者中至少一者上,其中,在进行一注入工艺之前,移除该第一区、该第二区、及该第三区中的虚置栅极。
6.如权利要求5所述的集成电路元件的形成方法,其中形成该蚀刻阻挡层于该第一区、该第二区、及该第三区三者中至少一者的该栅极介电层上的步骤,包括形成一氮化层。
7.如权利要求5所述的集成电路元件的形成方法,其中进行该注入工艺于该第一区、该第二区、及该第三区三者中至少一者上的步骤,该注入工艺的杂质择自下列群组之一:铟、氩、硅、氟、及上述的组合。
8.一种集成电路元件的形成方法,其中集成电路元件包含不同厚度的栅极介电层,包括:
提供一基板,该基板具有一第一区、一第二区、及一第三区;
形成一具有第一厚度的第一栅极介电层于该第一区中;
形成一阻挡层于该第一栅极介电层上;
形成一虚置栅极介电层于该第二区及该第三区中;
形成一虚置栅极层于该阻挡层及该虚置栅极介电层上;
进行一栅极图案化工艺以形成栅极结构于该第一区、该第二区、及该第三区中;
移除该第一区、该第二区、及该第三区的栅极结构的虚置栅极层,以形成开口于该第一区、该第二区、及该第三区的栅极结构中;
进行一注入工艺于该第二区或该第三区;
移除该第二区及该第三区的栅极结构中的虚置栅极介电层;以及
将一界面层填入该第二区及该第三区的栅极结构的部分开口,其中该第二区中的界面层具有一第二厚度,而该第三区中的界面层具有一第三厚度。
9.如权利要求8所述的集成电路元件的形成方法,其中形成该阻挡层于该第一栅极介电层上的步骤,包括形成一氮化物材料组成的阻挡层。
10.如权利要求8所述的集成电路元件的形成方法,其中将该界面层填入该第二区及该第三区的栅极结构的部分开口的步骤,进一步包括:
自第一区的栅极结构的开口移除该阻挡层;以及
将该界面层填入该第一区的栅极结构的部分开口。
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CN101262010A (zh) * | 2007-03-06 | 2008-09-10 | 台湾积体电路制造股份有限公司 | 金属氧化物半导体晶体管及高压金属氧化物半导体晶体管 |
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US8283222B2 (en) | 2012-10-09 |
CN102117774A (zh) | 2011-07-06 |
US20110159678A1 (en) | 2011-06-30 |
US8008143B2 (en) | 2011-08-30 |
US20110306196A1 (en) | 2011-12-15 |
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