CN102097413A - Structure and method for testing integrity of grid oxide layer and dielectric layer - Google Patents
Structure and method for testing integrity of grid oxide layer and dielectric layer Download PDFInfo
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- CN102097413A CN102097413A CN2009102011993A CN200910201199A CN102097413A CN 102097413 A CN102097413 A CN 102097413A CN 2009102011993 A CN2009102011993 A CN 2009102011993A CN 200910201199 A CN200910201199 A CN 200910201199A CN 102097413 A CN102097413 A CN 102097413A
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Abstract
The invention relates to a structure and method for testing the integrity of a grid oxide layer and a dielectric layer. The method for testing the integrity of the grid oxide layer comprises the following steps of: testing the integrity of the grid oxide layer through a first welding pad and a second welding pad, calibrating that a test result is in a passed state and finishing the test if the test is passed; or else, testing whether a short-circuited problem exists between the first welding pad and a third welding pad or between the second welding pad and the third welding pad; calibrating that the test result is in a passed state and finishing the test if the short-circuited problem exists; and calibrating that the test result is in a failed state and finishing the test if the short-circuited problem does not exist. The invention eliminates the interference of a short-circuited problem in a metal interaction layer on the test result and improves the test accuracy in testing the integrity of the grid oxide layer and the dielectric layer.
Description
Technical field
The present invention relates to the semiconductor test field, particularly the test structure and the method for testing of a kind of test structure of gate oxide integrity and method of testing and a kind of dielectric layer integrality.
Background technology
In the manufacture process of semiconductor device, for manufacturing process is monitored, guarantee the reliability of semiconductor device, common way is to form test structure (testkey) in device, is used for the test of some key parameters.In CMOS technology, gate oxide (gate oxide) is the important structure in the device architecture, gate oxide should be an ideal medium layer, wherein do not influence the defective of its insulation characterisitic, but, in manufacture process, all can influence the quality of gate oxide as factors such as ions diffusion intrusion, trap-charges.
Gate oxide integrity (gate oxide integrity is called for short GOI) test is the test process of checking gate oxide quality.In the manufacture process of semiconductor device, generally all will form special test structure is used for gate oxide integrity (GOI) test, detects in the gate oxide whether have defective, prevents that gate oxide defect from causing the reliability decrease of device.Similarly, after interconnection structure forms, need prevent because defectives such as ions diffusion cause the puncture voltage of dielectric layer to descend, make the reliability decrease of device the integrity test of the dielectric layer between the adjacent interconnection structure.
Fig. 1 has provided the test structure of a kind of gate oxide integrity of prior art.Device under test at first is provided, is formed with MOS transistor in the described device under test, described MOS transistor mainly comprises substrate 100, gate oxide 101, gate electrode 102 and source electrode and drain electrode (not shown); Described test structure mainly comprises weld pad 103 and weld pad 104, and weld pad 103 is connected in described substrate 100; Weld pad 104 is connected in described gate electrode.When carrying out gate oxide integrity (GOI) test, between described weld pad 103 and weld pad 104, apply voltage, with puncture voltage (the voltage breakdown that measures described gate oxide 101, be called for short Vbd), if puncture voltage is higher, be higher than specification voltage, then show not have defective in the gate oxide 101, test is passed through; On the contrary,, show then in the gate oxide 101 to have defective that test is not passed through if puncture voltage is lower than specification voltage.
The patent No. is the test structure that discloses a kind of gate oxide integrity in the Chinese patent of ZL200510030381, mainly comprises: many polysilicon grid lines, and decoder and a weld pad, wherein, described gate electrode before the polysilicon grid line is equivalent to.In test process, whole polysilicon grid lines are connected to decoder, and are connected to described weld pad by decoder, need to select the polysilicon grid line of test by decoder.Though do not mention the weld pad that is connected to substrate in the above-mentioned disclosed scheme, in fact remain with 2 weld pads and carry out gate oxide integrity (GOI) test.In test process, by decoder weld pad is connected to different polysilicon grid lines and tests one by one, thereby determine location of fault.
But in fact, the weld pad of described test structure is not to be connected directly to described gate electrode and substrate, but is connected to gate electrode and substrate indirectly by the metal interconnecting layer in the device.As shown in Figure 2, be formed with MOS transistor in the substrate 100, described MOS transistor comprises gate oxide 101, gate electrode 102, source electrode and drain electrode (not shown), on described MOS transistor, be formed with metal interconnecting layer 110, Fig. 2 is a schematic diagram, described metal interconnecting layer 110 can be first metal interconnecting layer, also can be other metal interconnecting layers, as second metal interconnecting layer.Be formed with connection gasket 110a and 110b in the described metal interconnecting layer 110, also be formed with embolism under the connection gasket, be connected with gate electrode 102 with described substrate 100 respectively.Weld pad 103 is connected to the substrate 100 of MOS transistor by described connection gasket 110a, and weld pad 104 is connected to the gate electrode 102 of MOS transistor by described connection gasket 110b.Therefore, if having defective in the metal interconnecting layer 110, will influence the test result of gate oxide integrity (GOI) test.If the puncture voltage in the test process between weld pad 103 and the weld pad 104 is very little, test result is not passed through, then its reason both may be to have defective in the gate oxide 101, it also may be defectiveness in the metal interconnecting layer 110, as there being bridge joint (bridging) defective between connection gasket 110a and the 110b, as shown in Figure 3, on the metal interconnecting layer 110 metal remained is arranged, cause short circuit between connection gasket 110a and the 110b, thereby make and also be short-circuited between weld pad 103 and 104.In the test process of reality, be gate oxide or metal interconnecting layer in order to judge the unsanctioned real causes of test, need carry out failure analysis (failure analysis, be called for short FA), require a great deal of time, manpower and equipment cost.
Summary of the invention
The problem that the present invention solves provides the test structure and the method for testing of a kind of gate oxide and dielectric layer integrality, avoids the interference of metal interconnected layer defects to test result, improves the measuring accuracy of gate oxide and dielectric layer integrality.
The invention provides a kind of test structure of gate oxide integrity, comprise: successively first connection gasket of the gate oxide on the substrate, gate electrode, the described substrate of connection, connect described gate electrode second connection gasket and and described first connection gasket and second connection gasket between all have the 3rd connection gasket at interval, wherein said first connection gasket, second connection gasket, the 3rd connection gasket are formed in the same dielectric layer; First weld pad is connected in described first connection gasket; Second weld pad is connected in described second connection gasket; It is characterized in that, also comprise the 3rd weld pad, be connected in described the 3rd connection gasket.
Optionally, be formed with contact hole under described first connection gasket, second connection gasket, the 3rd connection gasket.
Optionally, described the 3rd connection gasket and the 3rd weld pad are respectively second connection gasket and second weld pad in another test structure.
Optionally, described the 3rd connection gasket and the 3rd weld pad are respectively second connection gasket and second weld pad in the adjacent test structure.
The present invention also provides a kind of method of testing of using the gate oxide integrity of above-mentioned test structure, comprising:
By first weld pad and second weld pad integrality of gate oxide is tested, if test passes through, then test result is demarcated to passing through, and finishes to test;
Otherwise, test between first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad whether have short circuit problem, if there is a short circuit problem, then test result is demarcated to passing through, and finishes to test; If there is not a short circuit problem, then test result is demarcated to not passing through, and finishes to test.
Optionally, state by first weld pad and second weld pad gate oxide integrity to be tested and comprise: test the puncture voltage between first weld pad and second weld pad, if puncture voltage is higher than specification voltage (specification voltage), then test is passed through; Otherwise test is not passed through.
Optionally, whether exist short circuit problem to comprise between described test first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad: to test between first weld pad and the 3rd weld pad or the leakage current between second weld pad and the 3rd weld pad, if leakage current is higher than specification electric current (specification current), then have short circuit problem, test result is demarcated to passing through; Otherwise do not have short circuit problem, test result is demarcated to not passing through.
In order to address the above problem, the present invention also provides a kind of test structure of dielectric layer integrality, be formed with metal interconnecting layer on the described dielectric layer, described test structure comprises: first electrode and second electrode, be formed in the described dielectric layer, connect described first electrode first connection gasket, connect described second electrode second connection gasket and and described first connection gasket and second connection gasket between all have the 3rd connection gasket at interval, described first connection gasket, second connection gasket and the 3rd connection gasket are formed in the described metal interconnecting layer; First weld pad connects described first connection gasket; Second weld pad connects described second connection gasket; It is characterized in that, also comprise the 3rd weld pad, connect described the 3rd connection gasket.
Optionally, be formed with embolism under described first connection gasket, second connection gasket, the 3rd connection gasket.
Optionally, described the 3rd connection gasket and the 3rd weld pad are respectively second connection gasket and second weld pad in another test structure.
Optionally, described the 3rd connection gasket and the 3rd weld pad are respectively first connection gasket and first weld pad in the adjacent test structure, perhaps are respectively second connection gasket and second weld pad in the adjacent test structure.
The present invention also provides a kind of method of testing of using the dielectric layer integrality of above-mentioned test structure, comprising:
By first weld pad and second weld pad integrality of dielectric layer is tested, if test passes through, then test result is demarcated to passing through, and finishes to test;
Otherwise, test between first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad whether have short circuit problem, if there is a short circuit problem, then test result is demarcated to passing through, and finishes to test; If there is not a short circuit problem, then test result is demarcated to not passing through, and finishes to test.
Optionally, the described dielectric layer integrality test by first weld pad and second weld pad comprises: test the puncture voltage between first weld pad and second weld pad, if puncture voltage is higher than specification voltage, then test is passed through; Otherwise test is not passed through.
Optionally, whether exist short circuit problem to comprise between described test first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad: to test between first weld pad and the 3rd weld pad or the leakage current between second weld pad and the 3rd weld pad, if leakage current is higher than the specification electric current, then have short circuit problem, test result is demarcated to passing through; Otherwise do not have short circuit problem, test result is demarcated to not passing through.
In the above-mentioned disclosed technical scheme, compared with prior art increased a weld pad, when conventional integrity test is not passed through, by using the weld pad that increases metal interconnecting layer is tested, got rid of the interference of the short circuit problem in the metal interconnecting layer, improved the measuring accuracy of gate oxide and dielectric layer integrity test test result.
Description of drawings
Fig. 1 to Fig. 3 is the cross-sectional view of test structure of the grid silicon oxide layer integrality of prior art;
Fig. 4 is the structural representation of test structure of the gate oxide integrity of the embodiment of the invention;
Fig. 5 is the schematic flow sheet of method of testing of the gate oxide integrity of the embodiment of the invention;
Fig. 6 is the structural representation of test structure of the dielectric layer integrality of the embodiment of the invention.
Embodiment
In actual production, as shown in Figure 3, the weld pad 103 and 104 of test structure is to be connected in the gate electrode 102 of MOS transistor and substrate 100 indirectly by connection gasket 110a in the metal interconnecting layer and 110b.And the forming process of described connection gasket 110a and 110b mainly comprises: form opening in dielectric layer; In described opening, fill metal, form the connection gasket on embolism and the embolism, in filling process, have part metals to overflow described opening and cover the dielectric layer surface; Grind the metal that removal covers the dielectric layer surface by chemico-mechanical polishing (CMP), finish the forming process of metal interconnecting layer.In CMP (Chemical Mechanical Polishing) process, if having metal remained to cover the dielectric layer surface after the polishing, as shown in Figure 3, can cause between the connection gasket in the metal interconnecting layer to have bridge defects, disturb the test result of gate oxide integrity.Discover that through the inventor in CMP (Chemical Mechanical Polishing) process, the zone of wafer peripheral is easier to take place the polishing residual phenomena, causes to have bridge defects in the metal interconnecting layer, disturbs the test result of gate oxide integrity (GOI) test.Add up through the inventor, in the unsanctioned situation of gate oxide integrity (GOI) test, have 30% to be because the bridge defects of metal interconnecting layer causes, be not that gate oxide itself exists defective, therefore, need to improve existing test structure and method of testing, the defective in the eliminating metal interconnecting layer is improved measuring accuracy to the interference of test result.
The invention provides the test structure and the method for testing of a kind of gate oxide and dielectric layer integrality, increased a weld pad, when conventionally test does not pass through, by using the weld pad that increases metal interconnecting layer is tested, got rid of the interference of the short circuit problem in the metal interconnecting layer, improved the measuring accuracy of gate oxide and dielectric layer integrity test test result.
For method of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 4 has provided the structural representation of test structure of the gate oxide integrity of the embodiment of the invention.
As shown in Figure 4, comprise in the device of described test structure and be formed with MOS transistor and dielectric layer 210, described MOS transistor comprises substrate 200, gate oxide 201, gate electrode 202, source electrode and drain electrode (not shown), be formed with the first connection gasket 210a in the described dielectric layer 210, the second connection gasket 210b and the 3rd connection gasket 210c, be formed with contact hole (contact) 210d under above-mentioned in the present embodiment three connection gaskets, 210e, 210f, the wherein said second connection gasket 210b is connected in described gate electrode 202 by contact hole 210e, the described first connection gasket 210a is connected in described substrate 200 by contact hole 210d, have between described the 3rd connection gasket 210c and the described first connection gasket 210a and the second connection gasket 210b at interval, and it is contactless between contact hole 210f under it and the described substrate 200, make not have between itself and described gate electrode 201 and the substrate 200 and electrically connect, be formed with contact hole 210f under described in the present embodiment the 3rd connection gasket 210c, in other embodiments of the invention, described the 3rd connection gasket 210c can be independent connection gasket structure, and the below is not formed with contact hole.The test structure of gate oxide integrity also comprises: first weld pad 203 is connected with described gate electrode 202 by the first connection gasket 210a; Second weld pad 204 is connected with described substrate 200 by the second connection gasket 210b; The 3rd weld pad 205 is connected with described the 3rd connection gasket 210c, insulation between described the 3rd weld pad 205 and described gate electrode 202 and the substrate 200.
In actual process, described the 3rd connection gasket 210c can be connected in source electrode, drain electrode or the gate electrode of other adjacent mos transistors by the contact hole 210f under it, also can be connected in transistorized source electrode or drain electrode shown in Fig. 4.
In addition, described the 3rd weld pad 205 and the 3rd connection gasket 210c can be respectively second weld pad and second connection gaskets of other test structures, i.e. weld pad that links to each other with gate electrode and connection gasket, make in this way, weld pad and connection gasket between can multiplexing different test structures, and do not need to make one the 3rd weld pad separately for each test structure, reduced complexity, reduced cost.As a preferred scheme, described the 3rd weld pad 205 and the 3rd connection gasket 210c are preferably second weld pad and second connection gasket of adjacent test structure respectively.
In the present embodiment, described dielectric layer 210 is the dielectric layer in first metal interconnecting layer, in other embodiments of the invention, also can be other dielectric layers.
Fig. 5 has provided the structural representation of method of testing of the gate oxide integrity of the embodiment of the invention, below in conjunction with Figure 4 and 5 present embodiment is elaborated.
With reference to figure 4 and Fig. 5, execution in step S1 tests the puncture voltage between first weld pad 203 and second weld pad 204.Specifically comprise: between described first weld pad 203 and second weld pad 204, connect a voltage source, and progressively increase the output voltage of described voltage source, to record puncture voltage.Because described first weld pad 203 is connected in described gate electrode 202, the second weld pads 204 and is connected in described substrate 200, therefore, this step is to test by the integrality of first weld pad 203 and 204 pairs of gate oxides 201 of second weld pad, and is same as the prior art.
Execution in step S2 judges that whether described puncture voltage is less than specification voltage.If puncture voltage is bigger, greater than specification voltage, then show in the described gate oxide 201 not defective, execution in step S3 demarcates test result for passing through, and finishes described gate oxide integrity (GOI) test; If puncture voltage is less, then show in the gate oxide 201 to have defective, or the short circuit that exists bridge defects to cause between the first connection gasket 210a and the second connection gasket 210b, in this case, then continue execution in step S4.
With reference to figure 4 and Fig. 5, execution in step S4 tests the leakage current between first weld pad 203 and the 3rd weld pad 205 or second weld pad 204 and the 3rd weld pad 205.Specifically comprise: applying a fixed voltage between described first weld pad 203 and the 3rd weld pad 205 or between second weld pad 204 and the 3rd weld pad 205, and measuring corresponding leakage current.Owing to do not electrically connect between described the 3rd weld pad 205 and described gate electrode 202 and the substrate 200, be insulation each other, therefore, this step is the equal of that the metal interconnect structure in the dielectric layer 210 is tested, detect between its inner connection gasket 210a, 210b and the 210c whether have short circuit problem, prevent that the bridge defects between the connection gasket in the dielectric layer 210 from causing interference to the result of described gate oxide integrity (GOI) test.
Execution in step S5 judges that whether described leakage current is greater than the specification electric current.If leakage current is bigger, greater than the specification electric current, then show the short circuit problem that exists bridge defects to cause between connection gasket 210a, the 210b of described dielectric layer 210 inside and the 210c, the puncture voltage that has recorded among the step S1 before having caused is too small, therefore, the integrality of described gate oxide 201 does not have problem, execution in step S7, test result is demarcated to passing through, and finish to test.If leakage current is less, less than the specification electric current, then show the short circuit problem that does not exist bridge defects to cause between the connection gasket in the described dielectric layer 201, the puncture voltage that records among the step S1 before showing is too small to be that defective by gate oxide 201 causes, execution in step S6, test result is demarcated to not passing through, and finish to test.
Need to prove that size and concrete technology according to device under test are used in the test process judge that specification electric current and specification voltage that whether test is passed through have than big difference, therefore, its numerical value are not done too much relating in the present embodiment.
Fig. 6 has provided the structural representation of test structure of the dielectric layer integrality of the embodiment of the invention.
As shown in Figure 6, the semiconductor-based end 300, be provided, be formed with dielectric layer 301 and metal interconnecting layer 310 at described the semiconductor-based end 300, be formed with metal interconnect structures such as embolism in the described dielectric layer 301, constituted the first electrode 301a and the second electrode 301b in the dielectric material both sides; Be formed with the first connection gasket 310a in the described metal interconnecting layer 310, the second connection gasket 310b and the 3rd connection gasket 310c, wherein the first connection gasket 310a and the second connection gasket 310b are respectively by the embolism 310d under it, 310e is connected in the described first electrode 301a and the second electrode 301b, all have between the 3rd connection gasket 310c and the described first connection gasket 310a and the second connection gasket 310b at interval, also be formed with embolism 310f under the 3rd connection gasket 310c described in the present embodiment, but it is not connected in the described first electrode 301a and the second electrode 301b, makes not have between itself and the described first electrode 301a and the second electrode 301b to electrically connect.Described test structure also comprises: first weld pad 302 is connected with the described first electrode 301a by the described first connection gasket 310a; Second weld pad 303 is connected with the described second electrode 301b by the described second connection gasket 310b; The 3rd weld pad 304 is connected with described the 3rd connection gasket 310c, and and the described first electrode 301a and the second electrode 301b between do not have to electrically connect.Similar with the test structure of described gate oxide integrity before, described the 3rd weld pad 304 and the 3rd connection gasket 310c can be first weld pad and first connection gasket or second weld pad and second connection gasket of other test structures (as adjacent test structure), thereby reduce the complexity of described test structure.
The concrete steps of the method for testing of the dielectric layer integrality of present embodiment can be with reference to figure 5, mainly comprise: the integrality by first weld pad 302 and 303 pairs of described dielectric layers of second weld pad is tested, if by test, then show to exist bridge defects to cause short circuit problem between the first connection gasket 310a and the second connection gasket 310b in dielectric layer 301 defectiveness own or the metal interconnecting layer 310; Test whether there is short circuit phenomenon in the metal interconnecting layer 310 by first weld pad 302 and the 3rd weld pad 304 or second weld pad 303 and the 3rd weld pad 304 afterwards, in order to get rid of defective in the metal interconnecting layer 310 to dielectric layer integrity test result's interference.The method of testing in the present embodiment and the method for testing of aforementioned gate oxide integrity are similar, repeat no more here.
To sum up, the invention provides the test structure and the method for testing of a kind of gate oxide and dielectric layer integrality, increased a weld pad, when conventional integrity test is not passed through, use the weld pad that increases that metal interconnecting layer is tested, got rid of the interference of the short circuit problem in the metal interconnecting layer, improved the measuring accuracy of gate oxide and dielectric layer integrity test test result.
In addition, compared with prior art, the present invention does not need to carry out failure analysis just can get rid of short circuit problem in the metal interconnecting layer to the interference of test result, has shortened test period, has reduced testing cost.
Further, the weld pad of the present invention between can also multiplexing different test structures realized identical effect, compared with prior art do not increase the complexity of test structure.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. the test structure of a gate oxide integrity, comprise: successively first connection gasket of the gate oxide on the substrate, gate electrode, the described substrate of connection, connect described gate electrode second connection gasket and and described first connection gasket and second connection gasket between all have the 3rd connection gasket at interval, wherein said first connection gasket, second connection gasket, the 3rd connection gasket are formed in the same dielectric layer; First weld pad is connected in described first connection gasket; Second weld pad is connected in described second connection gasket; It is characterized in that, also comprise the 3rd weld pad, be connected in described the 3rd connection gasket.
2. the test structure of gate oxide integrity according to claim 1 is characterized in that, is formed with contact hole under described first connection gasket, second connection gasket, the 3rd connection gasket.
3. the test structure of gate oxide integrity according to claim 1 is characterized in that, described the 3rd connection gasket and the 3rd weld pad are respectively second connection gasket and second weld pad in another test structure.
4. the test structure of gate oxide integrity according to claim 3 is characterized in that, described the 3rd connection gasket and the 3rd weld pad are respectively second connection gasket and second weld pad in the adjacent test structure.
5. a method of testing of using the gate oxide integrity of each described test structure in the claim 1 to 4 is characterized in that, comprising:
By first weld pad and second weld pad integrality of gate oxide is tested, if test is passed through, then test result is demarcated to passing through;
Otherwise, test between first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad whether have short circuit problem, if there is short circuit problem, then test result is demarcated to passing through; If there is not short circuit problem, then test result is demarcated to not passing through.
6. the method for testing of gate oxide integrity according to claim 5, it is characterized in that, described gate oxide integrity the test by first weld pad and second weld pad comprises: test the puncture voltage between first weld pad and second weld pad, if puncture voltage is higher than specification voltage, then test is passed through; Otherwise test is not passed through.
7. the method for testing of gate oxide integrity according to claim 5, it is characterized in that, whether exist short circuit problem to comprise between described test first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad: to test between first weld pad and the 3rd weld pad or the leakage current between second weld pad and the 3rd weld pad, if leakage current is higher than the specification electric current, then have short circuit problem, test result is demarcated to passing through; Otherwise do not have short circuit problem, test result is demarcated to not passing through.
8. the test structure of a dielectric layer integrality is formed with metal interconnecting layer on the described dielectric layer, and described test structure comprises: first electrode and second electrode are formed in the described dielectric layer; Connect described first electrode first connection gasket, connect described second electrode second connection gasket and and described first connection gasket and second connection gasket between all have the 3rd connection gasket at interval, described first connection gasket, second connection gasket and the 3rd connection gasket are formed in the described metal interconnecting layer; First weld pad connects described first connection gasket; Second weld pad connects described second connection gasket; It is characterized in that, also comprise the 3rd weld pad, connect described the 3rd connection gasket.
9. the test structure of dielectric layer integrality according to claim 8 is characterized in that, is formed with embolism under described first connection gasket, second connection gasket, the 3rd connection gasket.
10. the test structure of dielectric layer integrality according to claim 8, it is characterized in that, described the 3rd connection gasket and the 3rd weld pad are respectively first connection gasket and first weld pad in another test structure, perhaps are respectively second connection gasket and second weld pad in another test structure.
11. the test structure of dielectric layer integrality according to claim 10, it is characterized in that, described the 3rd connection gasket and the 3rd weld pad are respectively first connection gasket and first weld pad in the adjacent test structure, perhaps are respectively second connection gasket and second weld pad in the adjacent test structure.
12. a method of testing of using the dielectric layer integrality of each described test structure of claim 8 to 11 is characterized in that, comprising:
By first weld pad and second weld pad integrality of dielectric layer is tested, if test passes through, then test result is demarcated to passing through, and finishes to test;
Otherwise, test between first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad whether have short circuit problem, if there is a short circuit problem, then test result is demarcated to passing through, and finishes to test; If there is not a short circuit problem, then test result is demarcated to not passing through, and finishes to test.
13. the method for testing of dielectric layer integrality according to claim 12, it is characterized in that, the described dielectric layer integrality test by first weld pad and second weld pad comprises: test the puncture voltage between first weld pad and second weld pad, if puncture voltage is higher than specification voltage, then test is passed through; Otherwise test is not passed through.
14. the method for testing of dielectric layer integrality according to claim 12, it is characterized in that, whether exist short circuit problem to comprise between described test first weld pad and the 3rd weld pad or between second weld pad and the 3rd weld pad: to test between first weld pad and the 3rd weld pad or the leakage current between second weld pad and the 3rd weld pad, if leakage current is higher than the specification electric current, then have short circuit problem, test result is demarcated to passing through; Otherwise do not have short circuit problem, test result is demarcated to not passing through.
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