CN101281897B - Matrix type structure for testing integrality of gate oxic horizon - Google Patents
Matrix type structure for testing integrality of gate oxic horizon Download PDFInfo
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- CN101281897B CN101281897B CN 200710039185 CN200710039185A CN101281897B CN 101281897 B CN101281897 B CN 101281897B CN 200710039185 CN200710039185 CN 200710039185 CN 200710039185 A CN200710039185 A CN 200710039185A CN 101281897 B CN101281897 B CN 101281897B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
The invention provides a matrix-type test structure for testing grid oxide layer integrality, which relates to a semiconductor test technique. By employing existing large area test structure, breakdown of a grid oxide layer is difficult to be exactly measured due to larger background current and series resistance, and measurement accuracy is low; by employing a plurality of small area test structure, disadvantages such as long test time and large use quantity of welding pads come into existence. The matrix-type test structure for testing grid oxide layer integrality comprises m*n test units arranged in matrix form, each of the test unit has a first lead wire and a second lead wire, wherein the first lead wires of m test units of each line are all connected to a metal conductor, the second lead wires of n test units of each row are all connected to another metal conductor, and one end of each metal conductor is connected to a welding pad. The matrix-type test structure of present invention can save test time, increase test accuracy, and reduce use quantity and occupancy area of welding pads.
Description
Technical field
The present invention relates to semiconductor test technology, relate in particular to a kind of test structure that is used to test gate oxide integrity.
Background technology
(Gate Oxide Integrity GOI) in the test, adopts large-area test structure usually at traditional gate oxide integrity.With electric capacity is example, referring to Fig. 1, this test structure is to go between respectively to weld pad P1 and P2 in polysilicon layer (poly) in capacitor C and the substrate (substrate), by on weld pad P1, P2, loading test voltage, and utilize the test card probe to contact with weld pad P1, P2, capacitor C is carried out the GOI test.
Enter 90nm after the epoch at semiconductor fabrication process, the gate oxide of semiconductor device is done more and more thinlyyer (less than 12 dusts), makes the leakage current of device sharply increase, and causes adopting the large tracts of land structure to be difficult to measure the gate oxide breakdown voltage of device.In addition, because the substrate and the polysilicon layer impedance of large tracts of land structure are bigger, add the increase of leakage current, cause the pressure drop of polysilicon layer and substrate to increase, this pressure drop has very big influence to certainty of measurement, therefore need use the test structure of small size instead.
Yet,, can obtain effective result just must test enough large-area structure in order to reach certain testing reliability.The gross area of supposing test structure should reach 1000 * 1000 μ m
2, and the area of unit testing structure only is 100 * 100 μ m
2, then must test 100 unit and could satisfy reliability requirement, the testing time that is spent is very long.In addition, each test cell need be equipped with two weld pads, then adopts above-mentioned method of testing to need to expend 200 weld pads altogether, and these weld pads can take sizable test space.
Summary of the invention
The object of the present invention is to provide a kind of matrix type test structure that is used to test gate oxide integrity,, improve measuring accuracy, and reduce weld pad usage quantity and weld pad area occupied to save the testing time.
To achieve the above object, the invention provides a kind of matrix type test structure that is used to test gate oxide integrity, by m * n test cell, m, n are natural number, form by the matrix form arrangement, described each test cell has first lead-in wire and second lead-in wire, wherein, first lead-in wire of the m of each a row test cell all is connected to a strip metal conductor, second lead-in wire of n test cell of each row also is connected to a strip metal conductor, and an end of each strip metal conductor is connected to a weld pad.
In above-mentioned matrix type test structure, by being connected to n the weld pad that each test cell first goes between, and be connected on m the weld pad of each test cell second lead-in wire and load test voltage simultaneously, can carry out gate oxide integrity (GOI) test simultaneously to m * n test cell.
In above-mentioned matrix type test structure, by being connected to the j row (weld pad of test cell first lead-in wire of 1≤j≤n), and be connected to that i is capable (to load test voltage respectively on the weld pad of the test cell of 1≤i≤m) second lead-in wire, can carry out gate oxide integrity (GOI) test separately to the test cell that is positioned at the capable j row of i.
In above-mentioned matrix type test structure, described test cell is an electric capacity, and this first lead-in wire is drawn from the polysilicon layer of electric capacity, and this second lead-in wire is drawn from the substrate of electric capacity.
In above-mentioned matrix type test structure, the gross area of m * n test cell should reach the requirement of testing reliability.
The matrix type test structure that is used to test gate oxide integrity of the present invention, become matrix form by unit cell arrangement with small area structure, and adopt metallic conductor that the lead-in wire of the test cell of each row or each row is linked together, make it compared with prior art, have following advantage and good effect:
1. can on all small area structure, load test voltage simultaneously, needn't test one by one, save the testing time greatly;
2. owing to adopted small area structure, the leakage current of test cell is reduced, simultaneously, connect each bar lead-in wire, can reduce the series resistance of polysilicon layer and substrate, thereby improve measuring accuracy by adopting metallic conductor;
3. the method for traditional unit testing one by one need expend 2mn weld pad, and structure of the present invention only need expend m+n weld pad, can significantly reduce the weld pad usage quantity, has also dwindled to test shared area;
4. because the frequency of exposure of test card probe and weld pad significantly reduces, can reduce the damage probability of test card, prolong the useful life of test card.
Description of drawings
By following examples and in conjunction with the description of its accompanying drawing, can further understand purpose, specific structural features and the advantage of its invention.Wherein, accompanying drawing is:
Fig. 1 is existing GOI test structure schematic diagram;
Fig. 2 is the schematic diagram of the matrix type GOI test structure of the specific embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the matrix type test structure that is used to test gate oxide integrity of the present invention is described in further detail.
The matrix type structure that is used for the GOI test of the present invention, form by the matrix form arrangement by m * n test cell (m, n are natural number), each test cell all has first lead-in wire and second lead-in wire, wherein, first lead-in wire of the m of each a row test cell all is connected to a strip metal conductor, second lead-in wire of n test cell of each row also is connected to a strip metal conductor, and an end of each strip metal conductor is connected to a weld pad, adopts a m+n strip metal conductor and m+n weld pad altogether.For the leakage current that reduces single test cell and the series resistance of polysilicon layer and substrate, to improve measuring accuracy, the area of each test cell of this matrix type structure is less, yet its gross area should reach the requirement of testing reliability.
Fig. 2 is the structural representation of the specific embodiment of the invention, and 9 electric capacity that drawn among the figure are arranged in 3 * 3 matrixes, promptly corresponding m=3, the situation of n=3.These 9 electric capacity be labeled as respectively C11, C12 ..., C33, each electric capacity all has two lead-in wires, draws from polysilicon layer and substrate respectively.First lead-in wire of 3 electric capacity of each row is connected to a weld pad P1 by a strip metal conductor Q1, and second lead-in wire of 3 electric capacity of each row is connected to another weld pad P2 by another strip metal conductor Q2 again.
When adopting Fig. 2 structure to carry out the dielectric breakdown test, only need on 3 weld pad P1 that are connected to each electric capacity first lead-in wire, to load test voltage, and will be connected to 3 weld pad P2 ground connection that each electric capacity second goes between, and once can finish the test of 9 electric capacity, shortened the testing time greatly.In addition, because the area of each electric capacity is less, its leakage current is also less relatively, adds to adopt metallic conductor as the connection medium between voltage source and the oxide layer, can reduce the pressure drop of polysilicon layer and substrate, thereby improves test accuracy.
In detecting during gate oxide breakdown, can judge whether this electric capacity punctures by the leakage current that electric capacity is measured in row choosing and column selection one by one, when detecting some electric capacity and punctured, then stop to test.When for example needing to test the leakage current of C31, only need on leftmost weld pad P1 and weld pad P2 bottom, to load corresponding test voltage and get final product.Similarly, owing to adopted the electric capacity of small size and metallic conductor as connecting medium, can avoid gate oxide breakdown to be covered by big background current, reduced the series resistance of polysilicon layer and substrate simultaneously, can detect gate oxide breakdown more accurately, its measuring accuracy can be improved.
As can be seen from the figure, adopt matrix type test structure of the present invention only need use m+n=6 weld pad to get final product, and if use conventional methods one by one test, then need 2mn=18 weld pad, not only increased cost, also taken bigger test area.
In sum, adopt matrix type test structure of the present invention to save the testing time, improve measuring accuracy, and reduce weld pad usage quantity and weld pad area occupied.
Claims (7)
1. matrix type test structure that is used to test gate oxide integrity, by m * n test cell, m, n are natural number, form by the matrix form arrangement, described each test cell has first lead-in wire and second lead-in wire, it is characterized in that: first lead-in wire of the m of each a row test cell all is connected to a strip metal conductor, and second lead-in wire of n test cell of each row also is connected to a strip metal conductor, and an end of each strip metal conductor is connected to a weld pad.
2. matrix type test structure as claimed in claim 1, it is characterized in that: by being connected to n the weld pad that each test cell first goes between, and be connected on m the weld pad of each test cell second lead-in wire and load test voltage respectively, m * n test cell carried out gate oxide integrity (GOI) test simultaneously.
3. matrix type test structure as claimed in claim 1, it is characterized in that: by being connected to the weld pad that j row test cell first goes between, and be connected on the weld pad of the capable test cell of i second lead-in wire and load test voltage respectively, the test cell that is positioned at the capable j row of i is carried out gate oxide integrity (GOI) test separately, 1≤j≤n wherein, 1≤i≤m.
4. matrix type test structure as claimed in claim 1 is characterized in that: described test cell is an electric capacity.
5. matrix type test structure as claimed in claim 4 is characterized in that: described first lead-in wire is drawn from the polysilicon layer of electric capacity.
6. matrix type test structure as claimed in claim 4 is characterized in that: described second lead-in wire is drawn from the substrate of electric capacity.
7. matrix type test structure as claimed in claim 1 is characterized in that: the gross area of m * n test cell should reach the requirement of testing reliability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200710039185 CN101281897B (en) | 2007-04-06 | 2007-04-06 | Matrix type structure for testing integrality of gate oxic horizon |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710039185 CN101281897B (en) | 2007-04-06 | 2007-04-06 | Matrix type structure for testing integrality of gate oxic horizon |
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| Publication Number | Publication Date |
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| CN101281897A CN101281897A (en) | 2008-10-08 |
| CN101281897B true CN101281897B (en) | 2011-07-20 |
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| CN 200710039185 Expired - Fee Related CN101281897B (en) | 2007-04-06 | 2007-04-06 | Matrix type structure for testing integrality of gate oxic horizon |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101702005B (en) * | 2009-10-28 | 2012-12-12 | 上海宏力半导体制造有限公司 | Time dependent dielectric breakdown parallel testing circuit |
| CN102097413B (en) * | 2009-12-15 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Structure and method for testing integrity of grid oxide layer and dielectric layer |
| CN102109569B (en) * | 2009-12-29 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Method for dielectric breakdown test on gate oxide adopting probe card |
| CN101800212B (en) * | 2010-03-12 | 2013-09-25 | 上海宏力半导体制造有限公司 | Test structure for integrity of semiconductor element gate oxide |
| CN102176443A (en) * | 2011-02-23 | 2011-09-07 | 北京大学 | Structure and method for testing breakdown reliability of oxide layer |
| CN102683324B (en) * | 2011-03-11 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | Test structure for interconnected metal capacitors |
| CN102693959B (en) * | 2011-03-25 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Grid resistor test structure for MOS transistor |
| CN103941171B (en) * | 2013-01-22 | 2017-05-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure and test method |
| CN104637922B (en) * | 2013-11-14 | 2018-04-27 | 中芯国际集成电路制造(上海)有限公司 | Test structure and its test method for gate medium integrality |
| CN104716123B (en) * | 2013-12-17 | 2018-06-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of test method and test structure |
| CN115954343B (en) * | 2023-03-09 | 2023-06-09 | 合肥晶合集成电路股份有限公司 | Gate oxide layer test structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355344A (en) * | 1992-11-13 | 1994-10-11 | Sgs-Thomson Microelectronics, Inc. | Structure for using a portion of an integrated circuit die |
| US6028324A (en) * | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
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2007
- 2007-04-06 CN CN 200710039185 patent/CN101281897B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355344A (en) * | 1992-11-13 | 1994-10-11 | Sgs-Thomson Microelectronics, Inc. | Structure for using a portion of an integrated circuit die |
| US6028324A (en) * | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
Non-Patent Citations (1)
| Title |
|---|
| JP特开平8-8312A 1996.01.12 |
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