CN103779327A - IMD measurement circuit structure and IMD performance test method - Google Patents
IMD measurement circuit structure and IMD performance test method Download PDFInfo
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Abstract
The invention discloses an IMD measurement circuit structure and an IMD performance test method. The IMD measurement circuit structure is arranged between a first measurement welding pad and a second measurement welding pad. The IMD measurement circuit structure comprises a metal wire layer to metal wire layer structure, a through hole terminal to metal wire layer structure, an upper metal wire layer to lower metal wire layer structure and a through hole to through hole structure. The IMD measurement circuit structure of the invention includes various structures at the same time, so the whole IMD measurement circuit structure have performances reflected by the structures at the same time, so that in the IMD performance tests, by adopting the IMD measurement circuit structure of the invention, the performances of the IMD comprising the various structures can be acquired only by performing the IMD performance test for the IMD measurement circuit structure of the invention for one time. According to the invention, a large number of test structures do not need to be designed any more and multiple tests do not need to be performed any mode, so the IMD test process is greatly simplified to make the test process simple and effective, so that the production cycle of a semiconductor integrated circuit is shortened, and the production cost is reduced.
Description
Technical field
The present invention relates to semiconductor fabrication, be particularly related in a kind of semiconductor integrated circuit manufacture process for IMD(Inter Metal Dielectric, metal interlamination medium layer) the IMD measuring circuit structure and the IMD performance test methods that adopt while carrying out performance test.
Background technology
Low-k(low-k) material (k<3.0) is due to its intrinsic low-k, can produce lower capacitance (C), thereby be widely used in field of semiconductor manufacture, as the dielectric layer material as being filled between metal level (comprising interconnection line (interconnect), through hole (via)).So, at BEOL(Back End Of Line, last part technology) adopt dielectric layer that Low-k material makes (as the dielectric layer between interconnection line, dielectric layer between interconnection line and through hole, dielectric layer between through hole and through hole etc.), its puncture voltage (Vbd, Voltage breakdown) can obviously reduce, particularly its TDDB(Time Dependent Dielectric Breakdown, dielectric layer time breakdown effect) more can significantly decline, this just the reliability of the technique to BEOL have higher requirement, the performance of the circuit structure that BEOL is manufactured is tested and is also become most important.
Current, specially for IMD(Inter Metal Dielectric, metal interlamination medium layer) test of performance, mainly be metal line layer to metal line layer (metal to metal) structure, through hole, through hole (via to via) structure and upper strata metal line layer to be tested lower metal line layer (upper metal to bottom metal) the corresponding IMD character of structure, these structure types are relatively single simple, only can measure the character that punctures of very simple wire structures.
As shown in Figure 1, for being directed to the graphic structure schematic diagram of the IMD test of metal line layer to metal line layer (metal to metal) structure.This test structure comprises the first measurement weld pad (PAD) 31 and the second measurement weld pad 32 that are set up in parallel, on the first measurement weld pad 31, connect some metal line layers that are parallel to each other 1, second measures the some metal line layers that are parallel to each other 1 of same connection on weld pad 32, the metal line layer 1 being connected with the first measurement weld pad 31 and and the metal line layer 1 that is connected of the second measurement weld pad 32 between mutually intert and be parallel to each other, metal line layer 1 is dentation and distributes, the metal line layer 1 being connected with the first measurement weld pad 31 is not connected with the second measurement weld pad 32, the metal line layer 1 being connected with the second measurement weld pad 32 is not connected with the first measurement weld pad 31, all metal line layers are all in same layer, between metal line layer 1, be filled with the dielectric layer (not shown in figure 1) of Low-k material.Like this, by measuring on weld pad 32 and apply after voltage at the first measurement weld pad 31 and second, just can measure the character that punctures to metal to metal (the metal to metal) IMD that structure is relevant.
As shown in Figure 2, for being directed to the graphic structure schematic diagram of the IMD test of through hole to through hole (via to via) structure.This test structure comprises the first measurement weld pad (PAD) 31 and the second measurement weld pad 32 that are set up in parallel; Wherein, the first measurement weld pad 31 and second is measured weld pad 32 and is connected respectively some through hole test structures 200 of being combined by upper strata metal line layer 11, through hole 2 and lower metal line layer 12, in this through hole test structure 200, between upper strata metal line layer 11 and lower metal line layer 12, have certain intervals, and upper strata metal line layer 11 is connected by multiple through holes 2 with lower metal line layer 12; Figure 2 shows that vertical view, what from Fig. 2, see is upper strata metal line layer 11 and the lower metal line layer 12 overlaping; The through hole test structure 200 being connected with the first measurement weld pad 31 and and the through hole test structure 200 that is connected of the second measurement weld pad 32 between mutually intert and be parallel to each other, through hole test structure 200 is dentation and distributes; The through hole test structure 200 being connected with the first measurement weld pad 31 is not connected with the second measurement weld pad 32, and the through hole test structure 200 being connected with the second measurement weld pad 32 is not connected with the first measurement weld pad 31; In this structure, the through hole 2 that is arranged in the through hole test structure 200 being connected with the first measurement weld pad 31 is parallel to each other with the through hole 2 that is arranged in the through hole test structure 200 being connected with the second measurement weld pad 32; The dielectric layer (not shown in Fig. 2) that is filled with Low-k material between through hole test structure 200, makes to be filled by Low-k material between through hole 2.Like this, by measuring on weld pad 32 and apply after voltage at the first measurement weld pad 31 and second, just can measure and the puncture character of through hole to through hole (the via to via) IMD that structure is relevant
As shown in Figure 3, the graphic structure schematic diagram for the IMD of lower metal line layer (upper metal to bottom metal) structure being tested for upper strata metal line layer.This test structure comprises the first weld pad (PAD) 31 and the second measurement weld pad 32 that are set up in parallel; Wherein, the first measurement weld pad 31 connects respectively some upper stratas metal line layer 11, the second measurement weld pads 32 and connects respectively some lower metal line layers 12; Between upper strata metal line layer 11 and lower metal line layer 12, there is certain intervals, and upper strata metal line layer 11 and the metal wire overlay structure 300 shown in lower metal line layer 12 overlaid composition diagram 3; The upper strata metal line layer 11 being connected with the first measurement weld pad 31 and and the lower metal line layer 12 that is connected of the second measurement weld pad 32 between be parallel to each other, and be dentation and distribute; The upper strata metal line layer 11 being connected with the first measurement weld pad 31 is not connected with the second measurement weld pad 32, and the lower metal line layer 12 being connected with the second measurement weld pad 32 is not connected with the first measurement weld pad 31; Between upper strata metal line layer 11 and lower metal line layer 12, be filled with the dielectric layer (not shown in Fig. 3) of Low-k material.Like this, by measuring on weld pad 32 and apply after voltage at the first measurement weld pad 31 and second, just can measure the character that punctures to upper strata metal pair lower metal (the upper metal to bottom metal) IMD that structure is relevant.
But, in actual chips design, because the complexity connecting up and then the complexity that has caused the made layout of metallic layer of BEOL can and be deposited if metal to metal structure, through hole are to various structures such as through-hole structure and upper strata metal pair lower metal structures at the made whole metal level of BEOL technique simultaneously.Shown in Fig. 1 to Fig. 3 is only in many structures the simplest three kinds, and other structure also comprises as through hole end (metal end) structure to metal etc.For the test of the IMD character in this labyrinth, need to carry out independent separately test for the various structures that occur in the made whole metal level of BEOL technique, this just need to design respectively a large amount of test structures and repeatedly test, to complete the test for the corresponding IMD performance of the made whole metal level of BEOL technique.Numerous and diverse and the poor efficiency of whole test process.
Summary of the invention
In view of this, the invention provides a kind of IMD measuring circuit structure and IMD performance test methods, to simplify the process of carrying out performance test in prior art for IMD, improve testing efficiency.
The application's technical scheme is achieved in that
A kind of IMD measuring circuit structure, be arranged at the first measurement weld pad and second and measure between weld pad, described IMD measuring circuit structure comprise metal line layer to metal line layer metal to metal structure, through hole end to metal line layer viaend to metal structure, upper strata metal line layer to lower metal line layer upper metal to bottom metal structure and through hole to through hole viato via structure.
Further, described IMD measuring circuit structure also comprises the dielectric layer of Low-k material, and in described IMD measuring circuit structure, all metal line layer and through hole are all arranged in the dielectric layer of described Low-k material.
Further, described metal line layer, in metal line layer structure, is filled with the dielectric layer of Low-k material between different metal line layers; Described through hole end, in metal line layer structure, is filled with the dielectric layer of Low-k material between through hole and metal line layer; Described upper strata metal line layer, in lower metal line layer structure, is filled with the dielectric layer of Low-k material between upper strata metal line layer and lower metal line layer; Described through hole, in through-hole structure, is filled with the dielectric layer of Low-k material between through hole and through hole.
Further, the metal line layer being electrically connected with described the first measurement weld pad and through hole are not electrically connected with described the second measurement weld pad, and the metal line layer being electrically connected with described the second measurement weld pad and through hole are not electrically connected with described the first measurement weld pad.
A kind of IMD performance test methods, comprising:
Measure between weld pad and set up IMD measuring circuit structure at the first measurement weld pad and second;
Described the first measurement weld pad and second is measured to weld pad and apply voltage;
Between measurement the first measurement weld pad and the second measurement weld pad, voltage and described the first measurement weld pad or second of flowing through are measured the electric current of weld pad, to obtain the I-V indicatrix about described IMD measuring circuit structure;
Judge the performance of described IMD measuring circuit structure according to described I-V indicatrix.
Further, described IMD measuring circuit structure comprise metal line layer to metal line layer metal to metal structure, through hole end to metal line layer via end to metal structure, upper strata metal line layer to lower metal line layer upper metal to bottom metal structure and through hole to through hole via to via structure.
Further, described IMD measuring circuit structure also comprises the dielectric layer of Low-k material, and in described IMD measuring circuit structure, all metal line layer and through hole are all arranged in the dielectric layer of described Low-k material.
Further, described metal line layer, in metal line layer structure, is filled with the dielectric layer of Low-k material between different metal line layers; Described through hole end, in metal line layer structure, is filled with the dielectric layer of Low-k material between through hole and metal line layer; Described upper strata metal line layer, in lower metal line layer structure, is filled with the dielectric layer of Low-k material between upper strata metal line layer and lower metal line layer; Described through hole, in through-hole structure, is filled with the dielectric layer of Low-k material between through hole and through hole.
Further, the metal line layer being electrically connected with described the first measurement weld pad and through hole are not electrically connected with described the second measurement weld pad, and the metal line layer being electrically connected with described the second measurement weld pad and through hole are not electrically connected with described the first measurement weld pad.
Further, the performance of described IMD measuring circuit structure comprises puncture voltage Vbd and dielectric layer time breakdown effect TDDB.
Can find out from such scheme, in IMD measuring circuit structure provided by the invention, comprise metal line layer to metal line layer structure simultaneously, through hole end is to metal line layer structure, upper strata metal line layer to lower metal line layer structure and through hole to various structures such as through-hole structures, therefore in whole IMD measuring circuit structure, had the performance that these structures reflect concurrently simultaneously, so adopt IMD measuring circuit structure of the present invention in the time carrying out IMD performance test, only carry out the once IMD performance test for IMD measuring circuit structure of the present invention, just can obtain the performance of the IMD including various structures.Compared with prior art, do not need to design again a large amount of test structures and repeatedly test, having simplified greatly IMD test process, making test process simple and efficient, thereby having shortened the production cycle of semiconductor integrated circuit, having reduced production cost.IMD performance test methods of the present invention compared with prior art, has been simplified IMD test process greatly, and then makes test process simple and efficient, can shorten the production cycle of semiconductor integrated circuit, and then reduce production costs.
Accompanying drawing explanation
Fig. 1 is the graphic structure schematic diagram of for metal line layer, the IMD of metal line layer structure being tested in prior art;
Fig. 2 is the graphic structure schematic diagram of for through hole, the IMD of through-hole structure being tested in prior art;
Fig. 3 is the graphic structure schematic diagram of for upper strata metal line layer, the IMD of lower metal line layer structure being tested in prior art;
Fig. 4 is IMD measuring circuit structure embodiment schematic diagram of the present invention;
Fig. 5 is the three-dimensional view of regional area in the IMD measuring circuit structure of Fig. 4;
Fig. 6 is the FB(flow block) of this IMD performance test methods;
Fig. 7 is the I-V indicatrix schematic diagram of the IMD measuring circuit structure obtained in IMD performance test methods of the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
Be illustrated in figure 4 IMD measuring circuit structure embodiment schematic diagram of the present invention, the three-dimensional view of regional area in the IMD measuring circuit structure that Fig. 5 is Fig. 4.Shown in Fig. 4 and Fig. 5, IMD measuring circuit structure of the present invention is arranged at the first measurement weld pad 31 and second and measures between weld pad 32, this IMD measuring circuit structure comprise metal line layer to metal line layer (metal to metal) structure A, through hole end to metal line layer (via end to metal) structure B, upper strata metal line layer to lower metal line layer (upper metal to bottom metal) structure C and through hole to through hole (via to via) structure D.
IMD measuring circuit structure of the present invention also comprises dotted line frame region in dielectric layer 4(Fig. 4 of Low-k material), in IMD measuring circuit structure, all metal line layer and through hole are all arranged in the dielectric layer 4 of described Low-k material.
Wherein, as shown in Figure 4, metal line layer is the metal line layer in same layer to two metal line layers corresponding in metal line layer structure A, and the metal line layer that the two lower metal line layers 12 that be arranged in parallel of alphabetical as shown in Figure 4 A both sides form is to metal line layer structure A.Should be noted that, the metal line layer comprising in Fig. 4 is to metal line layer structure A, be not only the metal line layer of two places letters A shown in Fig. 4 to metal line layer structure A, between the two lower metal line layers 12 that what other were adjacent be arranged in parallel and the adjacent two upper strata metal line layers 11 that are arranged in parallel, be metal line layer to metal line layer structure A.
As Fig. 5 and with reference to as shown in figure 4, through hole end that through hole end is connected with a metal line layer for through hole 2 to metal line layer structure B adjacent with this through hole end and structure that the metal line layer that is not connected with this through hole forms.For example, shown in Fig. 5, be positioned at the structure that the through hole end of the through hole 2 of letter b downside forms with the upper strata metal line layer 11 of letter b upside adjacent with it and that be not connected with this through hole 2, wherein, this through hole end that is positioned at the through hole 2 of letter b downside is connected with the end of the upper strata metal line layer 11 that is positioned at letter b lower-left side.This through hole end is in metal line layer structure B, equally also the end that is positioned at the upper strata metal line layer 11 of letter b lower-left side because be positioned at the through hole end of the through hole 2 of letter b downside, therefore through hole end to metal line layer structure also referred to as metal line layer end to metal line layer (metal end to metal) structure.Through hole end in Fig. 5 is to metal line layer structure B, not only be confined to the structure at letter b place in Fig. 5, in Fig. 5, have 4 through holes 2, a through hole end of each through hole 2 is to there being one to be adjacent and not connected metal line layer (upper strata metal line layer 11, lower metal line layer 12), therefore, the through hole end in Fig. 5 has 4 to metal line layer structure B.In Fig. 4 view of structure, there is more through hole end to metal line layer structure B according to the wiring environment of surrounding's metal line layer of each through hole 2 in figure as a whole.
As Fig. 5 and with reference to as shown in figure 4, upper strata metal line layer is made up of the overlapped region between not interconnected upper strata metal line layer 11 and lower metal line layer 12 lower metal line layer structure C, in Fig. 4, have 4 upper strata, place metal line layers to lower metal line layer structure C.
As Fig. 5 and with reference to as shown in figure 4, through hole is made up of adjacent and unconnected through hole 2 through-hole structure D, has 4 pairs as having adjacent between 2, two of 4 through holes and unconnected through hole 2 in Fig. 4, thus in Fig. 5 total through hole to through-hole structure D 4 places.In Fig. 4, can there is some places through hole to through-hole structure D according to the layout of the quantity of through hole 4 and metal line layer.
IMD measuring circuit structure shown in Fig. 4, is only a concrete enforcement structure, and actual IMD measuring circuit can be according to enlightenment of the present invention and actual needs, and those skilled in the art carry out wires design voluntarily.
In the IMD measuring circuit structure shown in Fig. 4 and Fig. 5, metal line layer to metal line layer structure A in, between different metal line layers, be filled with the dielectric layer 4 of Low-k material, as being filled with the dielectric layer 4 of Low-k material between different upper strata metal line layers 11, between different lower metal line layers 12, be filled with the dielectric layer 4 of Low-k material; Through hole end to metal line layer structure B in, between through hole 2 and metal line layer, be filled with the dielectric layer 4 of Low-k material; Upper strata metal line layer to lower metal line layer structure in, between upper strata metal line layer 11 and lower metal line layer 12, be filled with the dielectric layer 4 of Low-k material; Through hole to through-hole structure in, between through hole 2 and through hole 2, be filled with the dielectric layer 4 of Low-k material.In a word, in the IMD measuring circuit structure shown in Fig. 4 and Fig. 5, except upper strata metal line layer 11, lower metal line layer 12 and the occupied space of through hole 2, its complementary space is all filled by the dielectric layer 4 of Low-k material.
In IMD measuring circuit structure, the metal line layer being electrically connected with described the first measurement weld pad 31 and through hole are not electrically connected with described the second measurement weld pad, and the metal line layer being electrically connected with described the second measurement weld pad 32 and through hole are not electrically connected with described the first measurement weld pad.The all upper stratas metal line layer 11 being electrically connected with the first measurement weld pad 31, all lower metal line layers 12 and all through holes 2 are not electrically connected with the second measurement weld pad 32, and all upper stratas metal line layer 11 being electrically connected with the second measurement weld pad 32, all lower metal line layers 12 and all through holes 2 are not electrically connected with the first measurement weld pad 32.So just, can guarantee that the first measurement weld pad 31 and second is measured between weld pad 32 can not conducting, and then can measure the performance of this IMD measuring circuit structure.
The present invention also provides a kind of IMD performance test methods, as shown in Figure 6, comprising:
Step 1, measure between weld pad and set up IMD measuring circuit structure at the first measurement weld pad and second;
Between step 3, measurement the first measurement weld pad and the second measurement weld pad, voltage and described the first measurement weld pad or second of flowing through are measured the electric current of weld pad, to obtain the I-V indicatrix about described IMD measuring circuit structure;
Wherein, described IMD measuring circuit structure is the IMD measuring circuit structure shown in as above and Fig. 4, Fig. 5.
Wherein, the I-V indicatrix about described IMD measuring circuit structure obtaining in step 3 can be with reference to shown in figure 7.Wherein, transverse axis represents that voltage (V), the longitudinal axis represent electric current I, measure not directly electrical connection between weld pad although first measures weld pad and second, but due to the existence of the dielectric layer 4 of Low-k material in IMD measuring circuit structure, can produce parasitic capacitance to lower metal line layer structure C and through hole in to through-hole structure D to metal line layer structure B, upper strata metal line layer to metal line layer structure A, through hole end at metal line layer, and can produce the weak current through the dielectric layer 4 of Low-k material.So just, can be by flow through the first measurement weld pad 31 or the second measurement electric current I of weld pad 32 and the record of the voltage V that applies be obtained to corresponding I-V curve.
In Fig. 7, sampleA and sampleB choose this to estimate the measured I-V characteristic curve of structure sample at random.Its I-V slope of curve shows that by abrupt change is slow measured I-V characteristic is for observing the characteristic of low-k dielectric layer.
In step 4, the performance of measured IMD measuring circuit structure comprises Vbd and TDDB.
Wherein, judge the Vbd performance of described IMD measuring circuit structure according to the I-V indicatrix shown in Fig. 7, its detailed process is: arbitrary measurement weld pad making alive (first measures weld pad 31 or second measures weld pad 32), another measures weld pad ground connection.Voltage starts progressively to increase with certain step-length from 0V, measures live end measure the electric current of weld pad (this electric current is the leakage current summation of All Media layer between structure of flowing through) in each step-length.Due to dielectric layer self character, increase gradually with voltage, leakage current increases gradually.When voltage is large during to a certain particular value (being Vbd, Breakdown voltage, puncture voltage), dielectric layer itself cannot bear added electric stress, punctures.Now leakage current increases rapidly (electric current when not puncturing dielectric layer large one more than magnitude).Before puncturing, last normal magnitude of leakage current measuring point voltage of living in is designated as Vbd(puncture voltage).This method of testing is to see the soonest the method for dielectric layer characteristic quality.
The measuring process of TDDB is that another measures weld pad ground connection arbitrary measurement weld pad making alive (first measures weld pad or second measures weld pad 32).This voltage is constant voltage, as variable, rationally selects several measuring points to measure the electric current of institute's making alive measurement weld pad with the time.Dielectric layer can be in certain special time generation punch-through effect under constant electric stress.Cause leakage current to increase sharply.
In above-mentioned IMD measuring circuit structure provided by the invention, comprise metal line layer to metal line layer structure simultaneously, through hole end is to metal line layer structure, upper strata metal line layer to lower metal line layer structure and through hole to various structures such as through-hole structures, therefore in whole IMD measuring circuit structure, had the performance that these structures reflect concurrently simultaneously, therefore in the time carrying out IMD performance test, adopt IMD measuring circuit structure of the present invention, only carry out the once IMD performance test for IMD measuring circuit structure of the present invention, just can obtain the performance of the IMD including various structures.Compared with prior art, do not need to design again a large amount of test structures and repeatedly test, having simplified greatly IMD test process, making test process simple and efficient, thereby having shortened the production cycle of semiconductor integrated circuit, having reduced production cost.IMD performance test methods of the present invention compared with prior art, has been simplified IMD test process greatly, and then makes test process simple and efficient, can shorten the production cycle of semiconductor integrated circuit, and then reduce production costs.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (10)
1. an IMD measuring circuit structure, be arranged at the first measurement weld pad and second and measure between weld pad, it is characterized in that: described IMD measuring circuit structure comprise metal line layer to metal line layer metal to metal structure, through hole end to metal line layer via end to metal structure, upper strata metal line layer to lower metal line layer upper metal to bottom metal structure and through hole to through hole via to via structure.
2. IMD measuring circuit structure according to claim 1, it is characterized in that: described IMD measuring circuit structure also comprises the dielectric layer of Low-k material, in described IMD measuring circuit structure, all metal line layer and through hole are all arranged in the dielectric layer of described Low-k material.
3. IMD measuring circuit structure according to claim 2, is characterized in that: described metal line layer, in metal line layer structure, is filled with the dielectric layer of Low-k material between different metal line layers; Described through hole end, in metal line layer structure, is filled with the dielectric layer of Low-k material between through hole and metal line layer; Described upper strata metal line layer, in lower metal line layer structure, is filled with the dielectric layer of Low-k material between upper strata metal line layer and lower metal line layer; Described through hole, in through-hole structure, is filled with the dielectric layer of Low-k material between through hole and through hole.
4. according to the IMD measuring circuit structure described in claims 1 to 3 any one, it is characterized in that: the metal line layer being electrically connected with described the first measurement weld pad and through hole are not electrically connected with described the second measurement weld pad, the metal line layer being electrically connected with described the second measurement weld pad and through hole are not electrically connected with described the first measurement weld pad.
5. an IMD performance test methods, comprising:
Measure between weld pad and set up IMD measuring circuit structure at the first measurement weld pad and second;
Described the first measurement weld pad and second is measured to weld pad and apply voltage;
Between measurement the first measurement weld pad and the second measurement weld pad, voltage and described the first measurement weld pad or second of flowing through are measured the electric current of weld pad, to obtain the I-V indicatrix about described IMD measuring circuit structure;
Judge the performance of described IMD measuring circuit structure according to described I-V indicatrix.
6. IMD performance test methods according to claim 5, it is characterized in that, described IMD measuring circuit structure comprise metal line layer to metal line layer metal to metal structure, through hole end to metal line layer via end to metal structure, upper strata metal line layer to lower metal line layer upper metal to bottom metal structure and through hole to through hole via to via structure.
7. IMD performance test methods according to claim 6, it is characterized in that, described IMD measuring circuit structure also comprises the dielectric layer of Low-k material, and in described IMD measuring circuit structure, all metal line layer and through hole are all arranged in the dielectric layer of described Low-k material.
8. IMD measuring circuit structure according to claim 7, is characterized in that: described metal line layer, in metal line layer structure, is filled with the dielectric layer of Low-k material between different metal line layers; Described through hole end, in metal line layer structure, is filled with the dielectric layer of Low-k material between through hole and metal line layer; Described upper strata metal line layer, in lower metal line layer structure, is filled with the dielectric layer of Low-k material between upper strata metal line layer and lower metal line layer; Described through hole, in through-hole structure, is filled with the dielectric layer of Low-k material between through hole and through hole.
9. according to the IMD performance test methods described in claim 6 to 8 any one, it is characterized in that: the metal line layer being electrically connected with described the first measurement weld pad and through hole are not electrically connected with described the second measurement weld pad, the metal line layer being electrically connected with described the second measurement weld pad and through hole are not electrically connected with described the first measurement weld pad.
10. IMD performance test methods according to claim 5, is characterized in that, the performance of described IMD measuring circuit structure comprises puncture voltage Vbd and dielectric layer time breakdown effect TDDB.
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| CN105244342A (en) * | 2014-06-18 | 2016-01-13 | 上海华力微电子有限公司 | Electric breakdown test structure |
| CN105244342B (en) * | 2014-06-18 | 2019-02-22 | 上海华力微电子有限公司 | Structure is tested in electrical breakdown |
| CN107346751A (en) * | 2016-05-05 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Test structure and forming method thereof and method of testing |
| CN107346751B (en) * | 2016-05-05 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Test structure, forming method thereof and test method |
| CN106252254A (en) * | 2016-09-27 | 2016-12-21 | 上海华力微电子有限公司 | A kind of chip package interacts and tests structure and method of testing |
| CN110112120A (en) * | 2019-05-21 | 2019-08-09 | 武汉新芯集成电路制造有限公司 | IMD tests structure and semiconductor devices |
| CN117174695A (en) * | 2023-10-30 | 2023-12-05 | 荣耀终端有限公司 | Test structure, semiconductor device, wafer, electronic product and method |
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