CN101800212B - Test structure for integrity of semiconductor element gate oxide - Google Patents
Test structure for integrity of semiconductor element gate oxide Download PDFInfo
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- CN101800212B CN101800212B CN 201010123712 CN201010123712A CN101800212B CN 101800212 B CN101800212 B CN 101800212B CN 201010123712 CN201010123712 CN 201010123712 CN 201010123712 A CN201010123712 A CN 201010123712A CN 101800212 B CN101800212 B CN 101800212B
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Abstract
The invention discloses a test structure for the integrity of a semiconductor element gate oxide, which comprises an active region, a plurality of blocky shallow slot isolators and a plurality of grid structures, wherein the blocky shallow slot isolators are arranged in the active region; and the grid structures cover the shallow slot isolators in parallel at intervals. By using the test structure for the integrity of the semiconductor element grid oxide, the influence on the gate oxide by the stress of the position near the edge of a polysilicon gate and the edges of the shallow slot isolators can be monitored, and the negative effect of the etching of the edges of the gate by the stress of the edges of the shallow slot isolators can be effectively avoided by defect analysis.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of test structure of integrality of gate oxide of semiconductor part.
Background technology
Along with the continuous development of semiconductor technology, the thickness of the gate oxide of the MOS transistor in the integrated circuit also is down to below the 1nm by 20-30nm.Gate oxide constantly develops to the film direction, and supply voltage should not reduce, under higher electric field strength.Certainly will make the performance of gate oxide become distinct issues.The anti-electrical property of grid oxygen is bad will to cause MOS device electrical parameter instability, as: explain threshold voltage drift, mutual conductance decline, leakage current increase etc. further can cause the puncture of grid oxygen, cause the inefficacy of device, make the whole integrated circuit state that paralyses.Therefore, it is most important that the reliability of gate oxide becomes, and the integrity problem of gate oxide is mainly discussed defect concentration (Defect Density) problem and dielectric breakdown (the TDDB:Time Dependent Dielectric Breakdown) problem relevant with the time, these problems are the focuses that very lagre scale integrated circuit (VLSIC) reliability consideration field is paid close attention to always for many years, also are the major reasons that the restriction integrated level improves.
The main monitoring and evaluation gate oxide of gate oxide integrity (GOI) test is subjected to the influence of external factor, and these factors comprise defective or the particulate that produces in the processing procedure.Prior art GOI test structure is mainly monitored active area, the polysilicon gate edge, and the defective at shallow-trench isolation edge sees also Figure 1A to Fig. 1 C, and the GOI test structure of prior art mainly contains following type:
See also Figure 1A, GOI test structure shown in it is the active area type: square polysilicon gate 110 covers square active area 120, this structure has maximum active region area, the influence that gate oxide is caused in order to the stress (stress) of monitoring active area 120.
See also Figure 1B, GOI test structure shown in it is the polysilicon gate edge type: strip polysilicon gate 130 covers square active area 140, this structure has maximum polysilicon gate edge length, the influence that gate oxide is caused in order to the stress of monitoring strip polysilicon gate 130 edges.
See also Fig. 1 C, GOI test structure shown in it is the shallow-trench isolation edge type: square polysilicon gate 150 covers the active area 170 that comprises strip shallow-trench isolation 160, this structure has maximum shallow-trench isolation edge length, the influence that gate oxide is caused in order to the stress of monitoring shallow-trench isolation 160 edges.
Yet because the development of technology, new challenge has been proposed also for the measuring technology of GOI, particularly along with the variation of gate oxide thickness, the introducing of new material, traditional GOI method of testing can not satisfy the progress of technology far away.
In the prior art, the GOI test structure is just paid attention at the grid active area, the polysilicon gate edge, the stress at shallow-trench isolation edge is monitored the influence that gate oxide causes, yet these structures have but been ignored the influence that polysilicon gate edge and shallow-trench isolation side edge stress are nearby produced, and the stress at shallow-trench isolation edge is to the negative influence of being etched with of polysilicon gate edge, see also Fig. 2, it is depicted as the STI cross-sectional view, is 26 at the gate oxide film thickness 220 that the plane area of active area 210 grows as can be known according to figure
And in top corner regions, because the stress that is squeezed, oxide thickness has only 20-24
This meeting in uneven thickness causes two serious consequences: the one, cause double-hump effect (double-hump effect); The 2nd, influence the reliability of gate dielectric layer, i.e. gate oxide integrity GOI.For the MOS device that adopts STI technology, the effect of fringe field can cause the threshold voltage of device, and (thereshold voltage Vth) is reducing near sti region, produces parasitic low threshold voltage metal-oxide-semiconductor, has worsened the performance of device in the subthreshold value zone.And the breakdown characteristics of thinner oxide-film is poor, and the zone of losing efficacy the earliest in the GOI test is exactly at the STI edge usually.
Because GOI test structure of the prior art is ignored this part is carried out defect analysis, cause device to happen occasionally because of the situation that this part exists defective to lose efficacy, reducing along with gate oxide thickness particularly, application with new material, as the application of high dielectric constant materials and novel metal grid, what above problem caused that the problem of component failure becomes becomes increasingly conspicuous.
Summary of the invention
The present invention is intended to solve gate oxide integrity (GOI) test structure of the prior art and ignores gate oxide edge and shallow-trench isolation side edge defective nearby, the problem that causes device to happen occasionally because of this part situation that exists defective to lose efficacy.
In view of this, the invention provides a kind of test structure of integrality of gate oxide of semiconductor part, comprising: active area; Described a plurality of shallow-trench isolation is block, is arranged in the described active area; Being covered on the described shallow-trench isolation of described a plurality of grid structure parallel interval.
Further, described grid structure comprises: grid and gate oxide.
Further, described grid is polysilicon or metal gate.
Further, described gate oxide is oxide layer, nitration case or high dielectric constant material layer.
Utilize the test structure of integrality of gate oxide of semiconductor part provided by the invention can monitor out the influence that polysilicon gate edge and shallow-trench isolation side edge stress are nearby caused gate oxide, and can effectively avoid the stress at shallow-trench isolation edge to the negative effect of the etching at grid edge by defect analysis.
Description of drawings
Figure 1A to Fig. 1 C is depicted as the test structure schematic diagram of gate oxide integrity of the prior art;
Figure 2 shows that the shallow-trench isolation cross-sectional view;
Fig. 3 A and 3B are depicted as the test structure schematic diagram of the integrality of gate oxide of semiconductor part that one embodiment of the invention provides;
Fig. 4 A to 4D is depicted as the test structure schematic diagram of the integrality of gate oxide of semiconductor part that another embodiment of the present invention provides;
Fig. 5 A to 5C is depicted as the test structure schematic diagram of the integrality of gate oxide of semiconductor part that another embodiment of the present invention provides.
Embodiment
For technical characterictic of the present invention is become apparent, below in conjunction with accompanying drawing, provide specific embodiment, the present invention will be further described.
Embodiments of the invention provide a kind of test structure of integrality of gate oxide of semiconductor part, and this test structure comprises: active area; Described a plurality of shallow-trench isolation (STI) is arranged in the described active area from being block; Being covered on the described shallow-trench isolation of described a plurality of grid structure parallel interval.
Wherein said grid structure comprises: grid and gate oxide.Described grid is polysilicon or metal gate.Described gate oxide is oxide layer, nitration case or high dielectric constant material layer.
See also Fig. 3 A, 3B, this two figure be the sparse type of having of providing of one embodiment of the invention arrange from the test structure schematic diagram for the integrality of gate oxide of semiconductor part of block shallow-trench isolation.Wherein the shallow-trench isolation 320 among Fig. 3 A is positioned at grid structure 330 belows, and the shallow-trench isolation 320 ' among Fig. 3 B is positioned between the grid structure 330 '.
When being arranged at active area 310, grid structure 330 in 310 ', 330 ' be covered in that sparse type arranges from block shallow-trench isolation 320, in the time of 320 ', this moment shallow-trench isolation 320,320 ' edge is to grid structure 330, the stress that 330 ' edge produces, wherein the direction of stress is the shallow-trench isolation 320 along box-shaped, 320 ' the angular direction is put on grid structure 330,330 ' edge, thereby the block shallow groove isolation structure that this structure can monitor setting is to grid structure 330, the influence that a stress at 330 ' edge produces.
See also Fig. 4 A to 4D, this four figure is that dense form arranges having of providing of another embodiment of the present invention from the test structure schematic diagram for the integrality of gate oxide of semiconductor part of block shallow-trench isolation.
See also Fig. 4 A, being arranged in parallel of square shallow-trench isolation 420, and it is crossing with grid structure 420, when the grid structure 430 in being arranged at active area 410 is covered in the block shallow-trench isolation 420 of this tight type, adjacent very near perpendicular to the block shallow-trench isolation 420 that grid structure 430 is arranged, thereby can be simultaneously the edge of grid structure 430 be produced two stress, the direction of two stress that produce puts on grid structure 430 edges along shallow-trench isolation 420 cornerwise directions of box-shaped respectively, therefore, this structure can monitor the edge of shallow-trench isolation to the stress influence on the both direction at grid structure edge.
See also Fig. 4 B, wherein compact massive shallow-trench isolation 420 ' is positioned at grid structure 430 ' below.When the grid structure 430 ' in being arranged at active area 410 ' is covered in the block shallow-trench isolation 420 ' of tight type, this moment, block shallow-trench isolation 420 ' was adjacent very near, two adjacent block shallow-trench isolation 420 ', meeting produces two stress to the edge of grid structure 430 ' simultaneously, the direction of two stress that produce puts on grid structure 430 ' edge along shallow-trench isolation 420 ' cornerwise direction of box-shaped respectively, thereby this structure can monitor the edge of shallow-trench isolation to the stress influence on the both direction at grid structure edge.
See also Fig. 4 C, wherein the compact massive shallow-trench isolation 420 " be positioned at grid structure 430 " between, near shallow-trench isolation 420 " grid structure 430 " edge can be subjected to two adjacent block shallow-trench isolation 420 " its edge is produced two stress; the direction of two stress that produce is respectively along the shallow-trench isolation 420 of box-shaped " cornerwise direction puts on grid structure 430 " edge, thereby this structure can monitor the edge of shallow-trench isolation to the stress influence on the both direction at grid structure edge.
See also Fig. 4 D, wherein in block shallow-trench isolation 420 ' " intersect disperse be arranged at active area 410 ' ", it is positioned at grid structure 430 ' " under latent groove isolate 420 ' " and is positioned at grid structure 430 ' " between latent groove isolation 420 ' " adjacent, this moment can be simultaneously to grid structure 430 ' " edge produces two stress; its stress direction is along the shallow-trench isolation 420 of box-shaped ' " cornerwise direction put on grid structure 430 ' " edge; and direction is opposite, thereby this structure can monitor the edge of shallow-trench isolation to the stress influence on the both direction at grid structure edge.
See also Fig. 5 A, this figure is the test structure schematic diagram of the integrality of gate oxide of semiconductor part with dense form block shallow groove isolation structure arranged in a crossed manner that provides of another embodiment of the present invention.
Wherein shallow-trench isolation 520 be arranged under the grid structure 530 and between, all be to be compact shape, when the grid structure 530 in being arranged at active area 510 is covered in the block shallow-trench isolation 520 of dense form, this moment, a plurality of block shallow-trench isolation 520 was adjacent very near, adjacent block shallow-trench isolation 520 under the grid structure 530 can produce two stress to the edge of grid structure 530, the direction of two stress that produce puts on grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, in addition, and the block shallow-trench isolation 520 adjacent with grid structure 530 between the grid structure 530, also can be simultaneously the edge of grid structure 530 be produced two stress, the direction of two stress that produce puts on grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, therefore, this structure can monitor the edge of shallow-trench isolation to the stress influence on the four direction at grid structure edge.
See also Fig. 5 B to Fig. 5 C, it is the distressed structure of the test structure of the integrality of gate oxide of semiconductor part that has dense form block shallow groove isolation structure arranged in a crossed manner among Fig. 5 A.
Wherein, be positioned among Fig. 5 B grid structure 530 ' under bulk dive groove isolate 520 ' arrange for fine and close, grid structure 530 ' between bulk dive groove isolate 520 ' be sparse setting, at this moment, grid structure 530 ' under the bulk groove of diving isolate 520 ' can put on two stress in grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, and grid structure 530 ' between the bulk groove of diving isolate 520 ' can put on the stress in grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, therefore, this structure can monitor the edge of shallow-trench isolation to the stress influence on three directions at grid structure edge.
In Fig. 5 C, be positioned at grid structure 530 " under the bulk groove of diving isolate 520 " and be sparse arrangement, being positioned at grid structure 530 " between the bulk groove of diving isolate 520 " arranges for fine and close, at this moment, grid structure 530 " under the bulk groove of diving isolate 520 " can put on the stress in grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, and grid structure 530 ' between the adjacent bulk groove of diving isolate 520 ' can put on two stress in grid structure 530 edges along block shallow-trench isolation 520 cornerwise directions, therefore, this structure can monitor the edge of shallow-trench isolation to the stress influence on three directions at grid structure edge.
Utilize the test structure of the integrality of gate oxide of semiconductor part that the embodiment of the invention provides to monitor out the influence that polysilicon gate edge and shallow-trench isolation side edge stress are nearby caused gate oxide, and can effectively avoid the stress at shallow-trench isolation edge to the negative effect of the etching at polysilicon gate edge by defect analysis.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. the test structure of an integrality of gate oxide of semiconductor part is characterized in that, comprising:
Active area;
Described a plurality of shallow-trench isolation is that square is block, is arranged in the described active area;
Being covered on the described shallow-trench isolation of described a plurality of grid structure parallel interval, the width of described shallow-trench isolation is less than the width of described grid structure.
2. the test structure of integrality of gate oxide of semiconductor part according to claim 1 is characterized in that, described grid structure comprises: grid and gate oxide.
3. the test structure of integrality of gate oxide of semiconductor part according to claim 2 is characterized in that, described grid is polysilicon or metal gate.
4. the test structure of integrality of gate oxide of semiconductor part according to claim 2 is characterized in that, described gate oxide is oxide layer, nitration case or high dielectric constant material layer.
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101819941B (en) * | 2010-04-29 | 2014-03-12 | 上海宏力半导体制造有限公司 | Testing structure of integrity of semiconductor device gate oxide |
| CN103779326B (en) * | 2012-10-18 | 2016-09-21 | 中芯国际集成电路制造(上海)有限公司 | Goi test circuit structure |
| CN103811466B (en) * | 2012-11-07 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | GOI_TDDB test circuit structure |
| CN103872018B (en) * | 2012-12-11 | 2016-09-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of mos transistor array gate oxide integrity (GOI) test structure |
| CN104465614B (en) * | 2013-09-18 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Test structure and corresponding test method |
| CN104576612B (en) * | 2013-10-23 | 2017-09-26 | 中芯国际集成电路制造(上海)有限公司 | Test structure and forming method thereof, the method for testing of test structure |
| CN108022834B (en) * | 2017-11-30 | 2021-10-01 | 上海华力微电子有限公司 | Method and structure for monitoring 3D grid oxide layer process |
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| US6593157B1 (en) * | 1999-07-16 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Early response to plasma/charging damage by special pattern design of active region |
| CN101281898A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing integrality of grid medium layer, forming method and test method thereof |
| CN101281897A (en) * | 2007-04-06 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Matrix type structure for testing integrality of gate oxic horizon |
| CN101345233A (en) * | 2008-08-19 | 2009-01-14 | 上海宏力半导体制造有限公司 | Test structure and monitoring method for CUI effect of shallow plough groove isolation technology |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593157B1 (en) * | 1999-07-16 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Early response to plasma/charging damage by special pattern design of active region |
| CN101281898A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Structure for testing integrality of grid medium layer, forming method and test method thereof |
| CN101281897A (en) * | 2007-04-06 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Matrix type structure for testing integrality of gate oxic horizon |
| CN101345233A (en) * | 2008-08-19 | 2009-01-14 | 上海宏力半导体制造有限公司 | Test structure and monitoring method for CUI effect of shallow plough groove isolation technology |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |