CN105990422B - A kind of DMOS device - Google Patents
A kind of DMOS device Download PDFInfo
- Publication number
- CN105990422B CN105990422B CN201510054691.8A CN201510054691A CN105990422B CN 105990422 B CN105990422 B CN 105990422B CN 201510054691 A CN201510054691 A CN 201510054691A CN 105990422 B CN105990422 B CN 105990422B
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- China
- Prior art keywords
- field plate
- layer
- vdmos
- semiconductor substrate
- tube core
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 238000007667 floating Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000015556 catabolic process Effects 0.000 claims abstract description 15
- 230000005516 deep trap Effects 0.000 claims description 13
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000001939 inductive effect Effects 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
Abstract
The present invention provides a kind of DMOS device, it include: multiple VDMOS tube cores, wherein each VDMOS tube core includes semiconductor substrate, positioned at the positive epitaxial layer of the semiconductor substrate, the knot terminal surface texture that floating field plate on the dielectric layer and the dielectric layer in the epi-layer surface on the outside of tube core is constituted, wherein, the floating field plate that all adjacent VDMOS tube cores are located at outside is connected by metal bridge.Device according to the present invention, increasing the metal crossover between field plate can be effectively reduced levels of leakage of the VDMOS before breakdown voltage arrival, improve device performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of DMOS device.
Background technique
In semiconductor integrated circuit, circuit based on bilateral diffusion field-effect tranisistor, abbreviation DMOS utilizes two kinds
The sideways diffusion speed difference of foreign atom, forms self aligned submicrometer channel, can achieve very high working frequency and speed.
In 0.35um DMOS technique, it is resistance to improve that device mostly uses Metal field plate to improve depletion region edge field distribution
Voltage levels are illustrated in fig. 1 shown below, and device includes N+ semiconductor substrate 100, the N- epitaxial layer being formed in N+ semiconductor substrate 100
101, it is formed in the dielectric layer 103 on the outside of device and the Metal field plate above dielectric layer 103 104, is formed in semiconductor
The metal back electrode 102 at 100 back side of substrate.In DMOS device, the levels of leakage before reaching voltage breakdown point is device
One of the important indicator of energy.In order to promote breakdown voltage, reduce the levels of leakage of off state, various knot terminal technologies meet the tendency of and
It is raw, it is one kind common in knot terminal technology using Metal field plate technology.In (the i.e. NMOS leakage of VDMOS device metal back electrode 102
End) add forward voltage, the floating Metal field plate on medium of oxides layer can form coupled capacitor shape with dielectric layer and the silicon of lower section
Increase surface depletion at charge inducing, improves radius of curvature to improve breakdown, arrow meaning curve in depletion layer curve such as Fig. 2
It is shown.Metal field plate can increase depletion layer radius of curvature, promote breakdown voltage, but since the dielectric layer in technical process is easy
Charge is captured during high density plasma process and charge inducing of the Metal field plate of floating when measuring breakdown is caused to have
Changing causes soft breakdown or breakdown unstable, leaks electricity higher, reaches a microampere magnitude, as shown in Figure 3.
Therefore, in order to solve the above-mentioned technical problem, it is necessary to propose a kind of new DMOS device.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the present invention provides a kind of DMOS device, comprising:
Multiple VDMOS tube cores are located at the semiconductor and serve as a contrast wherein each VDMOS tube core includes semiconductor substrate
The positive epitaxial layer in bottom, the floating field plate on the dielectric layer and the dielectric layer in the epi-layer surface on the outside of tube core
The knot terminal surface texture of composition, wherein the floating field plate that all adjacent VDMOS tube cores are located at outside passes through metal bridging
It connects.
Optionally, semiconductor substrate is N+ type semiconductor substrate, and the epitaxial layer is N-type epitaxial layer.
Optionally, the floating field plate is floating Metal field plate.
Optionally, the material of the floating Metal field plate is selected from one or more of metallic aluminium, copper, gold, silver, platinum.
Optionally, the material of the metal bridge is selected from one or more of metallic aluminium, copper, gold, silver, platinum, tungsten, tin.
Optionally, the dielectric layer is medium of oxides layer.
Optionally, drain metal is formed at the back side of the semiconductor substrate.
Optionally, the VDMOS tube core further includes at least two p-types doping deep trap being formed in the epitaxial layer.
Optionally, the VDMOS tube core further includes the source region and formation being respectively formed in described two p-type doping deep traps
The source electrode on deep trap and the part source region is adulterated in the p-type.
In conclusion device according to the present invention, increases the metal crossover between field plate VDMOS can be effectively reduced and puncturing
Levels of leakage before voltage arrival, improves device performance.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 is the schematic diagram of the section structure of existing N60V VDMOS；
Fig. 2 is the depletion layer curve synoptic diagram when the metal back electrode of existing N60V VDMOS structure adds forward voltage；
Fig. 3 is the breakdown voltage curve graph when the metal back electrode of existing N60V VDMOS structure adds forward voltage；
Fig. 4 is the schematic diagram of the section structure of VDMOS tube core in exemplary embodiment of the present；
Fig. 5 is the breakdown voltage curve graph of VDMOS tube core in exemplary embodiment of the present.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the area Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then there is no elements or layer between two parties.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relation term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that spatial relation term intention further includes making other than orientation shown in figure
With the different orientation with the device in operation.For example, then, being described as " under other elements if the device in attached drawing is overturn
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Technical solution.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
[exemplary embodiment]
It is described in detail below with reference to structure of the Fig. 4 to DMOS device in the embodiment of the present invention.
The present invention provides a kind of DMOS device, comprising: multiple VDMOS tube cores, wherein each VDMOS tube core includes
Semiconductor substrate, the epitaxial layer in the semiconductor substrate, the medium in the epi-layer surface on the outside of tube core
The knot terminal surface texture that floating field plate on layer and the dielectric layer is constituted, wherein all adjacent VDMOS tube cores are located at outside
The floating field plate pass through metal bridge connect.
The present invention program is retouched in detail by taking the DMOS device that two VDMOS tube cores are constituted as an example in present example
It states, but it is noted that DMOS device of the present invention can also be made of multiple VDMOS tube cores, for example, 3,4,5,6 etc..
Refering to what is shown in Fig. 4, VDMOS tube core 40a and 40b constitute the DMOS device in the embodiment of the present invention, specifically, to it
In the structure of a VDMOS tube core do detailed construction, by taking VDMOS tube core 40a as an example, the structure of VDMOS tube core includes: N+ type half
Conductor substrate 400；It is formed in the positive N-type epitaxial layer 401 of the N+ type semiconductor substrate 400；It is formed in the N-type extension
At least two p-types in layer 401 adulterate deep trap 402, merely illustrate the one of a p-type doping deep trap 402 in Fig. 4 for simplicity
Part；It is formed in two N-type ions injection channel region (not shown) of each deep trap two sides；It is formed in two adjacent deep traps
On two channel regions and the gate oxide (not shown) of described two channel regions is completely covered；It is formed on the gate oxide
Grid (not shown), the grid is generally polysilicon gate；Be respectively formed in two p-types doping deep traps 402 and with institute
State the source region (not shown) of channel region connection；It is formed in the insulating layer on the fractional source regions of the grid two sides and on grid, shape
Deep trap, fractional source regions described in Cheng Yu and the source electrode on insulating layer (only showing part), and it is formed in the gold of the substrate back
Belong to back electrode structure 403, as drain electrode.For simplicity, the part-structure of VDMOS tube core, but this field are merely illustrated in Fig. 4
Technical staff is it is conceivable that further include other unshowned structures, therefore not to repeat here.
In the outside of VDMOS tube core 40a and 40b, i.e., Jie is formed on the epitaxial layer 401 in the outside of p-type doping deep trap 402
Matter layer 404.Optionally, the material of the dielectric layer 404 is oxide.Covering part is formed in the top of the dielectric layer 404
Divide the floating field plate 405 of the dielectric layer 404.In an example, the floating field plate 405 is floating Metal field plate.It is optional
The material on ground, the floating Metal field plate is selected from one or more of metallic aluminium, copper, gold, silver, platinum.On the outside of tube core
Knot terminal surface is constituted by the floating field plate 405 on the dielectric layer 404 and the dielectric layer 404 being located on the epitaxial layer 401
Structure.
With continued reference to Fig. 4, the floating field plate 405 on the outside of VDMOS tube core 40a and VDMOS tube core 40b passes through gold
Belong to bridge 406 to connect.Optionally, the material of the metal bridge 406 be selected from one of metallic aluminium, copper, gold, silver, platinum, tungsten, tin or
It is several.
Illustratively, the metal back electrode structure of each VDMOS tube core is electrically connected.
The Metal field plate of all adjacent tube cores is connected by increasing metal bridge, after drain terminal adds voltage, metal
Field plate and drain terminal capacity area increase, and reduce induction of the capture charge when measuring breakdown to floating Metal field plate in dielectric layer
Charge has an impact, and reaches stable hard breakdown curve and normal leakage current so as to improve soft breakdown.So that depletion region is not
It is normally broadened by influences of fluctuations such as apparatus and process, depletion region edge curvature radius increases the (depletion layer of arrow meaning in such as Fig. 4
Curve), closer to parallel plane knot, reduce electric leakage.Puncture test after increasing metal crossover, as shown in figure 5, not puncturing
Before, about tens Naans of leaking electricity.
In conclusion device according to the present invention, VDMOS is can be effectively reduced in breakdown potential in the metal crossover for increasing field plate
It is pressed onto the levels of leakage before reaching, improves device performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of DMOS device, comprising: multiple VDMOS tube cores, wherein each VDMOS tube core includes semiconductor substrate,
Positioned at the positive epitaxial layer of the semiconductor substrate, dielectric layer in the epi-layer surface on the outside of tube core and given an account of
The knot terminal surface texture that floating field plate on matter layer is constituted, wherein be formed with metal back at the back side of the semiconductor substrate
As drain electrode, the floating field plate that all adjacent VDMOS tube cores are located at outside is connected electrode structure by metal bridge, to increase
Capacity area between the floating field plate and the drain electrode reduces capture charge in the dielectric layer when measuring breakdown pair
The influence of the charge inducing of floating field plate.
2. device according to claim 1, which is characterized in that semiconductor substrate is N+ type semiconductor substrate, the extension
Layer is N-type epitaxial layer.
3. device according to claim 1, which is characterized in that the floating field plate is floating Metal field plate.
4. device according to claim 3, which is characterized in that the material of the floating Metal field plate be selected from metallic aluminium, copper,
One or more of gold, silver, platinum.
5. device according to claim 1, which is characterized in that the material of the metal bridge be selected from metallic aluminium, copper, gold, silver,
One or more of platinum, tungsten, tin.
6. device according to claim 1, which is characterized in that the dielectric layer is medium of oxides layer.
7. device according to claim 1, which is characterized in that the VDMOS tube core further includes being formed in the epitaxial layer
At least two interior p-types adulterate deep trap.
8. device according to claim 7, which is characterized in that the VDMOS tube core further includes being respectively formed in described two
The source electrode that a p-type is adulterated the source region in deep trap and is formed on the p-type doping deep trap and fractional source regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054691.8A CN105990422B (en) | 2015-02-02 | 2015-02-02 | A kind of DMOS device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054691.8A CN105990422B (en) | 2015-02-02 | 2015-02-02 | A kind of DMOS device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990422A CN105990422A (en) | 2016-10-05 |
| CN105990422B true CN105990422B (en) | 2019-01-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510054691.8A Active CN105990422B (en) | 2015-02-02 | 2015-02-02 | A kind of DMOS device |
Country Status (1)
| Country | Link |
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| CN (1) | CN105990422B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929126A (en) * | 2006-09-26 | 2007-03-14 | 无锡博创微电子有限公司 | Depletion type terminal protection structure |
| CN104157691A (en) * | 2014-08-15 | 2014-11-19 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9818742B2 (en) * | 2012-05-11 | 2017-11-14 | Polar Semiconductor, Llc | Semiconductor device isolation using an aligned diffusion and polysilicon field plate |
| US8921797B2 (en) * | 2012-06-20 | 2014-12-30 | Oxford Instruments Analytical Oy | Leakage current collection structure and a radiation detector with the same |
-
2015
- 2015-02-02 CN CN201510054691.8A patent/CN105990422B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1929126A (en) * | 2006-09-26 | 2007-03-14 | 无锡博创微电子有限公司 | Depletion type terminal protection structure |
| CN104157691A (en) * | 2014-08-15 | 2014-11-19 | 苏州捷芯威半导体有限公司 | Semiconductor device and manufacturing method thereof |
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| Publication number | Publication date |
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| CN105990422A (en) | 2016-10-05 |
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