JP2007129097A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of relaxing an electrical field in the vicinity of an electrode formed in a trench at the bottom of the trench of the lateral power semiconductor device having the trench structure, and to provide its manufacturing method. <P>SOLUTION: A p-type floating region 45 is formed within an expanded N drain region 25 formed on the bottom of the trench 24. The region 45 is separated from both a p-type first channel region 43 and a p-type second channel region 44 with the trench 24 bordered, and is formed so as to further overlap on the overlap part where a first gate electrode 28 and a second gate electrode 29 formed within the trench 24 and an interface of an interlayer dielectric 30 filling in between them overlapping the region 25 seen from above of an element to relax the field concentration at the overlap part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a power integrated circuit (power IC) and a manufacturing method thereof.

  In recent years, with the rapid spread of portable information devices and the advancement of communication technology, the importance of power ICs with built-in power MOSFETs (field-effect transistors having an insulated gate structure made of metal-oxide-semiconductor) has increased. Yes. A power IC that integrates a lateral power MOSFET and a control circuit is expected to be smaller, lower power consumption, higher reliability, and lower cost than a conventional power MOSFET combined with a control drive circuit. Is done. Therefore, in order to integrate a control drive circuit composed of a CMOS (complementary MOS) circuit and a lateral power MOSFET on the same semiconductor substrate, development of a high-performance lateral power MOSFET based on a CMOS process has been actively conducted. .

  Incidentally, a MOSFET having a trench structure is known as a technique for reducing the device pitch and increasing the degree of integration. Also in the lateral power MOSFET described above, in order to achieve further higher integration and lower on-resistance, trench technology is actively used.

  FIG. 59 is a cross-sectional view showing an example of a horizontal power element to which a conventional trench structure is applied. As shown in FIG. 59, an N-type well region 2 is provided inside a P-type semiconductor substrate 1. Inside the N-type well region 2, a P-type offset region 3 serving as a channel region is provided. Two trenches 4 are formed inside the P-type offset region 3. An extended N drain region 5 is provided at the bottom of the trench 4. Inside the trench 4, thin gate oxide films 6 and 7 are provided along the bottom surface and the side wall surface of the trench 4.

Gate electrodes 8 and 9 are provided inside the gate oxide films 6 and 7. An interlayer insulating film 10 is buried further inside the gate electrodes 8 and 9. An N ⁺ -type first source region 11 and a P ⁺ -type first source region 12 are provided in the first mesa region of the substrate surface layer that is divided by the trench 4. An N ⁺ -type second source region 13 and a P ⁺ -type second source region 14 are provided in the second mesa region of the substrate surface layer that is divided by the trench 4.

A first source electrode 15 is electrically connected to the N ⁺ -type first source region 11 and the P ⁺ -type first source region 12. A second source electrode 16 is electrically connected to the N ⁺ -type second source region 13 and the P ⁺ -type second source region 14. As described above, a bidirectional element that can flow current from the first source electrode 15 to the second source electrode 16 and can also flow current from the second source electrode 16 to the first source electrode 15 is known. (For example, refer to Patent Document 1).

  The bidirectional element described above is manufactured as follows. First, the N-type well region 2 is formed in the surface layer of the P-type semiconductor substrate 1, and the trench 4 is formed in the surface layer of the N-type well region 2 (the cross-sectional configuration at this time corresponds to FIG. 3). Next, P-type impurities are ion-implanted into the surface layers of the first mesa region and the second mesa region, and N-type impurities are ion-implanted into the bottom surface of the trench 4 (the cross-sectional configuration at this time corresponds to FIGS. 4 and 5). ).

  Next, thermal diffusion is performed to form a P-type offset region 3 in the first mesa region and the second mesa region, and an extended N drain region 5 is formed at the bottom of the trench 4. Next, gate oxide films 6 and 7 are formed inside the trench 4, and gate electrodes 8 and 9 are formed further inside thereof (the cross-sectional structure at this time corresponds to FIG. 6).

Next, N-type impurities and P-type impurities are selectively ion-implanted into the surface layer of the P-type offset region 3 (the cross-sectional configuration at this time corresponds to FIGS. 9 and 10). Next, thermal diffusion is performed to form the N ⁺ -type first source region 11 and the P ⁺ -type first source region 12 in the surface layer of the P-type offset region 3 of the first mesa region, and the second mesa region An N ⁺ -type second source region 13 and a P ⁺ -type second source region 14 are formed in the surface layer of the P-type offset region 3.

  Next, an interlayer insulating film 10 is deposited and planarized (the cross-sectional configuration at this time corresponds to FIG. 11). Finally, a contact hole is opened in the interlayer insulating film 10 to form the first source electrode 15 and the second source electrode 16, and the semiconductor device shown in FIG. 59 is completed.

  In addition, as shown in FIG. 60, an element in which a thick LOCOS (Local Oxidation of Silicon) oxide film 17 is formed on the bottom surface of the trench 4 in the lateral power element having the above-described configuration is known (for example, see Patent Document 2). ). The LOCOS oxide film 17 is formed so that the interface between the gate electrodes 8 and 9 and the oxide film inside the LOCOS oxide film 17 is thickened at the portion where it overlaps the extended N drain region 5. Hereinafter, a portion where the interface between the electrode in the trench and the insulating film (including the oxide film) inside the trench overlaps with the drain region at the bottom of the trench when viewed from above is referred to as an overlap portion.

JP 2004-274039 A JP 2003-249650 A

  However, in the conventional device shown in FIG. 59, the first source electrode 15 and the gate electrode 8 on the side thereof are set to the ground potential, and a high voltage lower than the withstand voltage is applied to the second source electrode 16 and the gate electrode 9 on the side. When the reliability test is performed, electric field concentration occurs in the overlap portion as in the electric field distribution indicated by a broken line in FIG. Then, electrons in the extended N drain region 5 are captured by the thin oxide film, and the extended N drain region 5 is depleted. Therefore, there is a problem that a serious current drop is caused.

  In order to prevent the concentration of the electric field in the overlap portion described above, the width of the trench 4 is widened, or a LOCOS oxide film 17 is formed on the bottom surface of the trench 4 as shown in FIG. It is necessary to thicken the oxide film between 8, 9 and the extended N drain region 5. However, when the trench width is widened, the device pitch increases and the degree of integration of the elements decreases, so that there is a problem that a sufficient on-resistance reduction effect cannot be obtained. On the other hand, if the overlap portion oxide film is thickened by the LOCOS oxide film 17, stress distortion occurs due to the LOCOS oxide film 17, so that there is a problem that reliability is lowered.

  In order to solve the above-described problems caused by the prior art, the present invention can reduce the electric field in the vicinity of the electrode formed in the trench at the bottom of the trench without forming a thick LOCOS oxide film at the bottom of the trench. An object is to provide an apparatus and a method for manufacturing the same.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a trench formed in a surface layer of a semiconductor substrate so that the surface layer of the semiconductor substrate has a first mesa region and a second mesa. A semiconductor device which is divided into regions and in which first mesa regions and second mesa regions are alternately arranged and current is drawn in the first mesa region and the second mesa region, and is formed on a surface layer of a semiconductor substrate A well region, a first conductivity type drain region provided at a bottom of a trench formed in the well region, and a first conductivity type provided in a surface layer of the first mesa region. In the first mesa region between the first source region and the drain region, and along the sidewall of the trench, and in both the first source region and the drain region Contact A first channel region of a second conductivity type, a first gate insulating film provided on a sidewall of the trench along the first channel region, and an inner side of the trench along the first gate insulating film. In the second mesa region between the second source region and the drain region, the first conductivity type second source region provided in the surface layer of the second mesa region, A second channel region of a second conductivity type provided along the sidewall of the trench and in contact with both the second source region and the drain region; and provided on the sidewall of the trench along the second channel region. A second gate insulating film, a second gate electrode provided inside the trench along the second gate insulating film, and provided at the bottom of the trench in the drain region, and the first channel A floating region of a second conductivity type that is separated from both the region and the second channel region and overlaps both the first gate electrode and the second gate electrode as viewed from above, and electrically connected to the first source region A first source electrode to be connected and a second source electrode to be electrically connected to the second source region are provided.

  According to the first aspect of the present invention, since the floating region is provided, the electric field at the bottom of the trench is alleviated. Therefore, at the bottom of the trench, the first gate electrode and the second gate electrode and the insulating film therebetween The electric field in the vicinity of the interface is relaxed. Therefore, depletion of the drain region due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed, so that the on-current is stabilized and the reliability is improved.

  According to another aspect of the semiconductor device of the present invention, the surface layer of the semiconductor substrate is divided into the first mesa region and the second mesa region by the trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region A semiconductor device in which mesa regions are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region, a well region formed in a surface layer of the semiconductor substrate; Within the well region, a first conductivity type first drain region provided at the bottom of a trench formed in the well region, and a first conductivity type source region provided in a surface layer of the first mesa region And a second conductor provided along the sidewall of the trench and in contact with both the source region and the first drain region in the first mesa region between the source region and the first drain region. A channel region of the mold, a gate insulating film provided on the sidewall of the trench along the channel region, a gate electrode provided on the inner side of the trench along the gate insulating film, and a surface of the second mesa region A second drain region of a first conductivity type provided in a layer, and a second mesa region between the second drain region and the first drain region, provided along a sidewall of the trench, and A third drain region of a first conductivity type in contact with both the second drain region and the first drain region; a field insulating film provided on a sidewall of the trench along the third drain region; and the field insulating film A field electrode provided inside the trench along the first drain region, and at the bottom of the trench, and the channel region and the A floating region of a second conductivity type that is separated from both of the three drain regions and overlaps both the gate electrode and the field electrode when viewed from above, a source electrode electrically connected to the source region, and the second drain And a second drain electrode electrically connected to the region.

  According to the second aspect of the present invention, since the floating region is provided, the electric field at the bottom of the trench is relaxed, so that the vicinity of the interface between the gate electrode and the field electrode and the insulating film between them is formed at the bottom of the trench. The electric field at is relaxed. Therefore, depletion of the drain region due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed, so that the on-current is stabilized and the reliability is improved.

  According to a third aspect of the present invention, in the semiconductor device, the surface layer of the semiconductor substrate is divided into the first mesa region and the second mesa region by the trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region A semiconductor device in which mesa regions are alternately arranged and current is drawn in the first mesa region and the second mesa region, the well region formed in a surface layer of a semiconductor substrate, and the well region in the well region A drain region of a first conductivity type provided at the bottom of a trench formed in the region; a first source region of a first conductivity type provided in a surface layer of the first mesa region; and the first source region, A first channel region of a second conductivity type provided along a side wall of the trench in the first mesa region between the drain regions and in contact with both the first source region and the drain region; First A first gate insulating film provided on a sidewall of the trench along the channel region; a first gate electrode provided on the inner side of the trench along the first gate insulating film; and a surface layer of the second mesa region And a second source region of the first conductivity type provided in the second mesa region between the second source region and the drain region, and along the sidewall of the trench, and the second source A second channel region of a second conductivity type in contact with both the region and the drain region; a second gate insulating film provided on a sidewall of the trench along the second channel region; and a second gate insulating film A second gate electrode provided inside the trench along the drain region, in the drain region, at the bottom of the trench, and from both the first channel region and the second channel region A first floating region of a second conductivity type that overlaps the first gate electrode when viewed from above, and a drain region that is provided at the bottom of the trench, and that includes the first channel region and the second channel. A second floating region of a second conductivity type that is separated from both of the regions and overlaps the second gate electrode when viewed from above, a first source electrode electrically connected to the first source region, and the second source And a second source electrode electrically connected to the region.

  According to the third aspect of the invention, since the first floating region and the second floating region are provided, the electric field at the bottom of the trench is alleviated. Therefore, the first gate electrode and the second gate electrode are formed at the bottom of the trench. And the electric field near the interface between them and the insulating film between them is relaxed. Therefore, depletion of the drain region due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed, so that the on-current is stabilized and the reliability is improved.

  In a semiconductor device according to a fourth aspect of the present invention, a surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region A semiconductor device in which mesa regions are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region, a well region formed in a surface layer of the semiconductor substrate; Within the well region, a first conductivity type first drain region provided at the bottom of a trench formed in the well region, and a first conductivity type source region provided in a surface layer of the first mesa region And a second conductor provided along the sidewall of the trench and in contact with both the source region and the first drain region in the first mesa region between the source region and the first drain region. A channel region of the mold, a gate insulating film provided on the sidewall of the trench along the channel region, a gate electrode provided on the inner side of the trench along the gate insulating film, and a surface of the second mesa region A second drain region of a first conductivity type provided in a layer, and a second mesa region between the second drain region and the first drain region, provided along a sidewall of the trench, and A third drain region of a first conductivity type in contact with both the second drain region and the first drain region; a field insulating film provided on a sidewall of the trench along the third drain region; and the field insulating film A field electrode provided inside the trench along the first drain region, and at the bottom of the trench, and the channel region and the A first floating region of a second conductivity type that is separated from both of the three drain regions and overlaps the gate electrode when viewed from above, and is provided at the bottom of the trench in the first drain region, and the channel region and A second floating region of a second conductivity type that is separated from both of the third drain regions and overlaps the field electrode as viewed from above, a source electrode electrically connected to the source region, and a second drain region And a second drain electrode that is electrically connected.

  According to the fourth aspect of the present invention, since the first floating region and the second floating region are provided, the electric field at the bottom of the trench is alleviated. Therefore, at the bottom of the trench, the gate electrode and the field and the gap therebetween The electric field in the vicinity of the interface with the insulating film is relaxed. Therefore, depletion of the drain region due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed, so that the on-current is stabilized and the reliability is improved.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the well region is of a first conductivity type. A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the well region is of a second conductivity type. A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to any one of the first to sixth aspects, wherein the semiconductor substrate is of a first conductivity type. According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects, the semiconductor substrate is of a second conductivity type. According to the inventions of claims 5 to 8, the same effects as those of claims 1 to 4 can be obtained.

  According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region is divided. Forming a well region in a surface layer of a semiconductor substrate in manufacturing a semiconductor device in which mesa regions and second mesa regions are alternately arranged and current is drawn in the first mesa region and the second mesa region; Forming a trench in a surface layer of the well region to divide the surface layer of the semiconductor substrate into a first mesa region and a second mesa region; a surface layer in the first mesa region; and in the second mesa region Forming a second-conductivity-type first channel region, a second-conductivity-type second channel region, and a first-conductivity-type drain region on the surface layer of the trench and the bottom of the trench, respectively, Forming a first gate insulating film and a second gate insulating film on the side wall along the first channel region and the side wall along the second channel region, respectively, and along the first gate insulating film and the second gate insulating film Forming a first gate electrode and a second gate electrode inside the trench, respectively, and separating from both the first channel region and the second channel region at the bottom of the trench in the drain region; A floating region of the second conductivity type that overlaps both the first gate electrode and the second gate electrode as viewed from above is formed by ion implantation of impurities using the first gate electrode and the second gate electrode as a mask. A first conductivity type first layer on the surface layer of the first mesa region and the surface layer of the second mesa region, respectively. Forming a source region and a second source region of the first conductivity type, filling the trench with an interlayer insulating film, opening a contact hole in the interlayer insulating film, and passing the first hole through the contact hole Forming a first source electrode and a second source electrode that are electrically connected to the source region and the second source region, respectively.

  According to a tenth aspect of the present invention, there is provided a semiconductor device manufacturing method, wherein a surface layer of a semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region is formed. Forming a well region in a surface layer of a semiconductor substrate in manufacturing a semiconductor device in which currents are drawn in the first mesa region and the second mesa region, and the well region Forming a second conductivity type channel region in the inner surface layer, forming an etching mask having a trench pattern on the substrate surface, and forming a trench in the surface layer of the well region using the etching mask. The surface layer of the channel region formed in the well region is divided into a first mesa region and a second mesa region by dividing the surface layer of the semiconductor substrate into a first mesa region and a second mesa region. A first channel region in the first region and a second channel region in the second mesa region, a step of forming a drain region of the first conductivity type at the bottom of the trench, and the first channel of the trench. Forming a first gate insulating film and a second gate insulating film on the side wall along the region and the side wall along the second channel region, and the trench along the first gate insulating film and the second gate insulating film, respectively. Forming a first gate electrode and a second gate electrode on the inner side of the trench, and separating from both the first channel region and the second channel region at the bottom of the trench in the drain region, as viewed from above. A floating region of a second conductivity type that overlaps both the first gate electrode and the second gate electrode. A step of forming ions by implanting impurities using the first gate electrode and the second gate electrode as a mask, and after removing the etching mask, the surface layer of the first mesa region and the second mesa Forming a first conductive type first source region and a first conductive type second source region on the surface layer of the region, filling the trench with an interlayer insulating film, and forming a contact hole in the interlayer insulating film, respectively. Forming a first source electrode and a second source electrode which are opened and electrically connected to the first source region and the second source region through the contact holes, respectively.

  According to the invention of claim 9 or 10, the semiconductor device of claim 1 or 3 can be manufactured only by adding an ion implantation step for forming a floating region to the conventional manufacturing process. According to the invention of claim 10, since the ion implantation for forming the floating region is performed using the etching mask remaining on the substrate surface, the number of masks is reduced by one as compared with the invention of claim 9, The manufacturing process is simplified. Therefore, an increase in manufacturing cost when manufacturing the semiconductor device according to claim 1 or 3 can be minimized.

  In a method of manufacturing a semiconductor device according to an eleventh aspect of the present invention, a surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region And the second mesa region are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region. Forming a trench in a surface layer of the well region, dividing the surface layer of the semiconductor substrate into a first mesa region and a second mesa region, and forming a surface layer in the first mesa region. Forming a second conductivity type channel region; forming a first conductivity type first drain region in a surface layer in the second mesa region; and forming a first conductivity type channel at the bottom of the trench. Second dress Forming a gate region, a step of forming a gate insulating film and a field insulating film on the side wall of the trench along the side wall of the trench and the side of the first drain region, and the gate insulating film and the field of the field, respectively. Forming a gate electrode and a field electrode inside the trench along the insulating film, respectively, at the bottom of the trench in the second drain region, away from both the channel region and the first drain region; Forming a floating region of a second conductivity type that overlaps both the gate electrode and the field electrode as viewed from above by performing ion implantation of impurities using the gate electrode and the field electrode as a mask; A source region of the first conductivity type is formed on the surface layer of the mesa region A step of filling the trench with an interlayer insulating film; a source electrode that opens a contact hole in the interlayer insulating film and is electrically connected to the source region and the first drain region through the contact hole; and Forming a drain electrode.

  According to a semiconductor device manufacturing method of a twelfth aspect of the present invention, a surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region And the second mesa region are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region. Forming a second conductivity type channel region and a first conductivity type first drain region on the surface layer in the well region; forming an etching mask having a trench pattern on the substrate surface; A trench is formed in the surface layer of the well region using the etching mask, and the surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region. A step of separating a channel region in the first mesa region and a first drain region in the second mesa region, a step of forming a second drain region of the first conductivity type at the bottom of the trench, Forming a gate insulating film and a field insulating film on the side wall along the channel region and the side wall along the first drain region, respectively, and forming a gate inside the trench along the gate insulating film and the field insulating film, respectively. A step of forming an electrode and a field electrode; and at the bottom of the trench in the second drain region, apart from both the channel region and the first drain region and as viewed from above, the gate electrode and the field electrode A floating region of the second conductivity type that overlaps both of the etching mask and the front Forming by ion implantation of impurities using the gate electrode and the field electrode as a mask, and forming a first conductivity type source region in the surface layer of the first mesa region after removing the etching mask And a step of filling the trench with an interlayer insulating film; and a source electrode and a drain that open a contact hole in the interlayer insulating film and are electrically connected to the source region and the first drain region through the contact hole, respectively. Forming an electrode.

  According to the invention of claim 11 or 12, the semiconductor device of claim 2 or 4 can be manufactured only by adding an ion implantation step for forming a floating region to the conventional manufacturing process. According to the invention of claim 12, since the ion implantation for forming the floating region is performed using the etching mask remaining on the substrate surface, the number of masks is reduced by one as compared with the invention of claim 11, The manufacturing process is simplified. Therefore, an increase in manufacturing cost when manufacturing the semiconductor device according to claim 2 or 4 can be minimized.

The method of manufacturing a semiconductor device according to the invention of claim 13 is the invention according to claim 9 or 10, the depth of the trench and D _t, the distance between the said first gate electrode and the second gate electrode L _GG, and θ is an angle formed by a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the sidewall surface of the trench,
−L _GG / (2 · D _t ) ≦ tan θ ≦ L _GG / (2 · D _t )
It is characterized by being.

The method of manufacturing a semiconductor device according to the invention of claim 14 is the invention according to claim 9 or 10, the depth of the trench and D _t, the distance between the said first gate electrode and the second gate electrode L _GG, and θ is an angle formed by a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the sidewall surface of the trench,
L _GG / (2 · D _t ) <| tan θ | ≦ L _GG / D _t
It is characterized by being.

The method of manufacturing a semiconductor device according to the invention of claim 15 is the invention according to claim 10, the depth of the trench and D _t, the distance between the said first gate electrode and the second gate electrode L _GG The thickness of the etching mask is T ₁ , the thickness of the first gate electrode and the second gate electrode is T ₃ , respectively, and the thickness of the first gate insulating film and the second gate insulating film is T ₄ is set as T _4, and θ is an angle formed between a tilt plane when impurity ions are implanted to form the floating region and a plane parallel to the sidewall of the trench, and the sum of T ₃ and T ₄ Is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _GG
And- (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} ≦ tan θ ≦ (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )}
It is characterized by being.

The method of manufacturing a semiconductor device according to the invention of claim 16 is the invention according to claim 10, the depth of the trench and D _t, the distance between the said first gate electrode and the second gate electrode L _GG The thickness of the etching mask is T ₁ , the thickness of the first gate electrode and the second gate electrode is T ₃ , respectively, and the thickness of the first gate insulating film and the second gate insulating film is T ₄ is set as T _4, and θ is an angle formed between a tilt plane when impurity ions are implanted to form the floating region and a plane parallel to the sidewall of the trench, and the sum of T ₃ and T ₄ Is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _GG
And (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} <| tan θ | ≦ (2 · T ₂ + L _GG ) / (T ₁ + D _t )
It is characterized by being.

According to a seventeenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the eleventh or twelfth aspect of the present invention, wherein the depth of the trench is D _t , and the distance between the gate electrode and the field electrode is L _FG . When an angle formed by a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the side wall surface of the trench is θ,
−L _FG / (2 · D _t ) ≦ tan θ ≦ L _FG / (2 · D _t )
It is characterized by being.

Method of manufacturing a semiconductor device in the invention of claim 18 is the invention according to claim 11 or 12, the depth of the trench and D _t, the distance between the field electrode and the gate electrode and L _FG, When an angle formed by a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the side wall surface of the trench is θ,
L _FG / (2 · D _t ) <| tan θ | ≦ L _FG / D _t
It is characterized by being.

Method of manufacturing a semiconductor device in the invention of claim 19 is the invention according to claim 12, the depth of the trench and D _t, the distance between the field electrode and the gate electrode and L _FG, the etching the thickness of the mask and T _1, the thickness of the gate electrode and the field electrode and T _3, respectively, the thickness of the gate insulating film and the field insulating film and T _4, respectively, for forming the floating region When the angle formed between the tilt surface when performing impurity ion implantation and the plane parallel to the side wall surface of the trench is θ, and the sum of T ₃ and T ₄ is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _FG
And- (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} ≦ tan θ ≦ (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )}
It is characterized by being.

The method of manufacturing a semiconductor device according to the invention of claim 20 is the invention according to claim 12, the depth of the trench and D _t, the distance between the field electrode and the gate electrode and L _FG, the etching the thickness of the mask and T _1, the thickness of the gate electrode and the field electrode and T _3, respectively, the thickness of the gate insulating film and the field insulating film and T _4, respectively, for forming the floating region When the angle formed between the tilt surface when performing impurity ion implantation and the plane parallel to the side wall surface of the trench is θ, and the sum of T ₃ and T ₄ is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _FG
And (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} <| tan θ | ≦ (2 · T ₂ + L _FG ) / (T ₁ + D _t )
It is characterized by being.

  According to the invention of claims 13 to 20, the floating region can be formed by the oblique ion implantation method. In particular, according to the inventions of claims 14, 16, 18 and 20, the floating region divided into a plurality of regions can be formed in the drain region by the oblique ion implantation method.

  According to a twenty-first aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the ninth to twelfth aspects, wherein the well region is of a first conductivity type. A method of manufacturing a semiconductor device according to a twenty-second aspect of the invention is characterized in that, in the invention according to any one of the ninth to twelfth aspects, the well region is of a second conductivity type. According to a twenty-third aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the ninth to twenty-second aspects, wherein the semiconductor substrate is of a first conductivity type. According to a twenty-fourth aspect of the present invention, there is provided a semiconductor device manufacturing method according to any one of the ninth to twenty-second aspects, wherein the semiconductor substrate is of a second conductivity type.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, the electric field in the vicinity of the electrode formed in the trench can be relaxed at the bottom of the trench without forming a thick LOCOS oxide film at the bottom of the trench. Play.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, in the region where N or P is named, it means that electrons or holes are majority carriers, respectively. Further, + attached to N or P means that the impurity concentration is higher than that in a region where N or P is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, an N-type well region 22 is provided inside a P-type semiconductor substrate 21. For example, two trenches 24 are formed in the N-type well region 22. The trench 24 is shallower than the N-type well region 22.

  By these trenches 24, the surface layer of the P-type semiconductor substrate 21 is divided into a first mesa region 41 and a second mesa region 42. The first mesa region 41 and the second mesa region 42 are alternately arranged. For example, in the example of FIG. 1, the region sandwiched between the two trenches 24 is the first mesa region 41, and the outside of the two trenches 24. This area is the second mesa area 42.

In the surface layer of the first mesa region 41, an N ⁺ type first source region 31 and a P ⁺ type first source region 32 are provided. The N ⁺ -type first source region 31 is provided in contact with one side wall of the trench 24. In the surface layer of the second mesa region 42, an N ⁺ -type second source region 33 and a P ⁺ -type second source region 34 are provided. The N ⁺ -type second source region 33 is provided in contact with the other side wall of the trench 24.

An extended N drain region 25 is provided at the bottom of each trench 24. The extended N drain region 25 surrounds the entire bottom surface and part of the side surface of the trench 24 and is shallower than the N-type well region 22 but may be deeper than the N-type well region 22. When the N-type well region 22 is P-type, the extended N-drain region 25 must be shallower than the P-type well region. When the N-type well region 22 is P-type, adjacent N drain regions 25 are connected to each other in order to separate the first channel region 43 and the second channel region 44. In the first mesa region 41, a P-type first channel region 43 is provided between the extended N drain region 25 and the N ⁺ -type and P ⁺ -type first source regions 31 and 32. In the second mesa region 42, a P-type second channel region 44 is provided between the extended N drain region 25 and the N ⁺ -type and P ⁺ -type second source regions 33 and 34.

  A thin first gate oxide film 26 and a second gate oxide film 27 are provided inside each trench 24. The first gate oxide film 26 is provided along the bottom surface of the trench 24 and the P-type first channel region 43. The second gate oxide film 27 is provided along the bottom surface of the trench 24 and the P-type second channel region 44. In each trench 24, a first gate electrode 28 and a second gate electrode 29 are provided inside the first gate oxide film 26 and the second gate oxide film 27, respectively.

  Inside each extended N drain region 25, a P-type floating region 45 is provided. The P-type floating region 45 is in contact with the center of the bottom of the trench 24 and is separated from both the P-type first channel region 43 and the P-type second channel region 44. However, when viewed from above the element, the P-type floating region 45 is in an overlapping portion where the interface between the first gate electrode 28 and the second gate electrode 29 and the interlayer insulating film 30 filling the gap overlaps with the extended N drain region 25. Furthermore, it forms so that it may overlap.

The interlayer insulating film 30 is also provided on the first mesa region 41 and the second mesa region 42. A first source electrode 35 is electrically connected to the N ⁺ -type first source region 31 and the P ⁺ -type first source region 32 through a contact hole that penetrates the interlayer insulating film 30. Further, the second source electrode 36 is electrically connected to the N ⁺ -type second source region 33 and the P ⁺ -type second source region 34 through a contact hole that penetrates the interlayer insulating film 30. A current flows bidirectionally between the first source electrode 35 and the second source electrode 36.

  FIG. 2 is a diagram showing an electric field distribution in the reliability test of the semiconductor device shown in FIG. The reliability test was performed by setting the first source electrode 35 and the first gate electrode 28 to the ground potential, and applying a high voltage lower than the withstand voltage to the second source electrode 36 and the second gate electrode 29. In the semiconductor device shown in FIG. 1, by optimizing the concentration of the P-type floating region 45, the electric field at the bottom of the trench is relaxed. As a result, the electric field in the overlap portion is relaxed as compared with FIG. 61 as in the electric field distribution indicated by the broken line in FIG. Therefore, depletion of the extended N drain region 25 due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed, so that the on-current is stabilized and the reliability is improved.

  Next, a manufacturing process of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 3 to 11 are longitudinal cross-sectional views showing the main parts of the semiconductor device in the manufacturing stage in the order of processes. First, the N-type well region 22 is formed in the surface layer of the P-type semiconductor substrate 21. Subsequently, a mask 51 made of, for example, an oxide film is formed on the substrate surface, and trench etching is performed to form a trench 24 in the surface layer of the N-type well region 22 (FIG. 3).

After removing the mask 51, buffer oxidation is performed to form a buffer oxide film 52. Then, a mask 53 is put on the inside of the trench 24 and the boundary portion between the P-type semiconductor substrate 21 and the N-type well region 22 on the substrate surface, and P is applied to the surface layers of the first mesa region 41 and the second mesa region 42. For example, boron (B ₁₁ ) is ion-implanted as a type impurity (FIG. 4). After removing the mask 53, the first mesa region 41 and the second mesa region 42 are covered with a mask 54, and phosphorus (P ₃₁ ), for example, is ion-implanted as an N-type impurity on the bottom surface of the trench 24 (FIG. 5). In addition, you may perform the process of FIG. 5 before the process of FIG.

  After removing the mask 54, thermal diffusion is performed to form a P-type first channel region 43 and a P-type at the surface layer in the first mesa region 41, the surface layer in the second mesa region 42, and the bottom of the trench 24, respectively. The second channel region 44 and the extended N drain region 25 are formed. After removing the buffer oxide film 52, oxide films to be the first gate oxide film 26 and the second gate oxide film 27 are formed inside the trench 24, and further, the first gate electrode 28 and the second gate electrode 29 are formed inside thereof. Form. Then, shadow oxidation is performed to form a shadow oxide film 55 (FIG. 6).

Next, a mask 56 is put on the first mesa region 41 and the second mesa region 42, and for example, boron (B ₁₁₎ as a P-type impurity only on the bottom surface of the trench 24 using the first gate electrode 28 and the second gate electrode 29 as a mask. ) Is implanted (FIG. 7). After removing the mask 56, thermal diffusion is performed to form a P-type floating region 45 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 8).

Here, using the first gate electrode 28 and the second gate electrode 29 as a mask secures a margin L _df at the junction end between the P-type floating region 45 and the extended N drain region 25 as shown in FIG. This is to prevent the P-type floating region 45 from being connected to the P-type first channel region 43 and the P-type second channel region 44. Another reason is that both ends of the P-type floating region 45 extend to the lower side of the first gate electrode 28 and the second gate electrode 29 and overlap the overlap portion.

Next, a mask 57 is put on the first mesa region 41 and the second mesa region 42, and arsenic (As, for example) is selectively formed on the surface layer of the first mesa region 41 and the surface layer of the second mesa region 42 as an N-type impurity. ₇₅ ) is ion-implanted (FIG. 9). After removing the mask 57, the first mesa region 41 and the second mesa region 42 are covered with a mask 58, and P-type impurities are selectively applied to the surface layer of the first mesa region 41 and the surface layer of the second mesa region 42. As an example, boron (B ₁₁ ) is ion-implanted (FIG. 10). In addition, you may perform the process of FIG. 10 before the process of FIG.

After removing the mask 58, thermal diffusion is performed to form an N ⁺ -type first source region 31 and a P ⁺ -type first source region on the surface layer of the P-type first channel region 43 (first mesa region 41). 32, and an N ⁺ -type second source region 33 and a P ⁺ -type second source region 34 are formed in the surface layer of the P-type second channel region 44 (second mesa region 42). Subsequently, the interlayer insulating film 30 is deposited on the entire substrate, the trench 24 is filled with the interlayer insulating film 30, and the interlayer insulating film 30 is also deposited on the first mesa region 41 and the second mesa region.

Then, the interlayer insulating film 30 is planarized by CMP (Chemical Mechanical Polishing) or the like (FIG. 11). Finally, a contact hole is opened in the interlayer insulating film 30, and a first source electrode 35 electrically connected to the N ⁺ -type first source region 31 and the P ⁺ -type first source region 32 is formed. ^A second source electrode 36 electrically connected to the ⁺ type second source region 33 and the P ⁺ type second source region 34 is formed. Thereby, the semiconductor device shown in FIG. 1 is completed.

In addition, it may replace with the process of FIGS. 3-6 and the process of FIGS. 12-14 may be performed. First, the N-type well region 22 is formed in the surface layer of the P-type semiconductor substrate 21. Then, a buffer oxide film 63 is formed on the substrate surface. Subsequently, a mask 59 is placed on the boundary between the P-type semiconductor substrate 21 and the N-type well region 22 on the substrate surface, and boron (B ₁₁ ), for example, is ion-implanted as a P-type impurity over the entire surface of the N-type well region 22. (FIG. 12).

After removing the buffer oxide film 63 and the mask 59, a mask 60 made of, for example, an oxide film is formed on the substrate surface, and trench etching is performed to form the trench 24 in the surface layer of the N-type well region 22. Subsequently, buffer oxidation is performed to form a buffer oxide film 61 inside the trench 24. Then, for example, phosphorus (P ₃₁ ) is ion-implanted as an N-type impurity into the bottom surface of the trench 24 (FIG. 13).

  Next, thermal diffusion is performed, and a P-type first channel region 43 and a P-type second channel region are respectively formed on the surface layer in the first mesa region 41, the surface layer in the second mesa region 42, and the bottom of the trench 24. 44 and an extended N drain region 25 are formed. After removing the buffer oxide film 61, an oxide film to be the first gate oxide film 26 and the second gate oxide film 27 is formed inside the trench 24, and further, the first gate electrode 28 and the second gate electrode 29 are formed inside thereof. Is formed (FIG. 14). Although not shown, the mask 60 is removed, shadow oxidation is performed to form a shadow oxide film, and the process proceeds to FIG.

Further, the process of FIG. 15 may be performed instead of the process of FIG. That is, following the process of FIG. 6, the mask 62 is placed on the boundary portion of the P-type semiconductor substrate 21, the N-type well region 22, and the P-type second channel region 44 on the substrate surface, and the first gate electrode 28. As an example, boron (B ₁₁ ) is ionized as a P-type impurity on the bottom surface of the trench 24, the surface layer of the P-type first channel region 43, and the surface layer of the P-type second channel region 44 using the second gate electrode 29 as a mask. Inject (FIG. 15). Then, the mask 62 is removed and the process proceeds to the process of FIG.

  When the process of FIG. 15 is performed, the concentrations of the P-type first channel region 43 and the P-type second channel region 44 are controlled by the amount of ion implantation of the P-type impurity in both the steps of FIGS. The By performing the process of FIG. 15, ion implantation can be performed without concern about the accuracy of mask displacement when miniaturization is performed, so that the manufacturing process is simplified.

  Further, instead of the process of FIG. 7, the processes of FIGS. 16 and 17 may be performed, or instead of the process of FIG. 15, the processes of FIGS. 18 and 19 may be performed. That is, in the process of FIG. 7 or FIG. 15, the ion implantation angle of the P-type impurity is the vertical direction (0 degree). On the other hand, the oblique ion implantation method is applied in the steps of FIGS. 16 and 17, or the steps of FIGS. 18 and 19, and the ion implantation angle of the P-type impurity is inclined from the vertical direction.

In this oblique ion implantation method, if the angle formed between the tilt plane and the plane parallel to the sidewall surface of the trench 24 is θ, the ion is expressed as θ = ± θ ₁ (where θ ₁ > 0). Make an injection. At that time, θ ₁ is set to satisfy the following expression (1). Here, D _t is the depth of the trench 24, and L _GG is the distance between the first gate electrode 28 and the second gate electrode 29.
0 <tan θ ₁ ≦ L _GG / (2 · D _t ) (1)

Then, in the positive direction of the oblique ion implantation step shown in FIG. 16 or 18, ion implantation at an angle of θ = + θ _1, the negative direction of the oblique ion implantation step shown in FIG. 17 or FIG. 19, when the positive direction It is preferable to perform ion implantation at an angle of θ = −θ ₁ at the same concentration. In this way, the profile of the P-type floating region 45 is symmetric with respect to the center line of the trench 24, so that current flows from the first source electrode 35 to the second source electrode 36 and vice versa. This is because the same on / off characteristics can be obtained.

  According to the first embodiment, since the transistor is formed on the sidewall of the trench 24, the channel width per unit area can be increased. Therefore, the degree of integration can be increased and the on-resistance per unit area can be reduced. In addition, since the electric field at the bottom of the trench 24 is relaxed, depletion of the extended N drain region 25 due to electron capture can be suppressed, so that the on-current is stabilized and the reliability is improved. Furthermore, the semiconductor device shown in FIG. 1 can be obtained simply by adding an ion implantation step and a thermal diffusion step for forming the P-type floating region 45 to the conventional manufacturing process, so that a LOCOS oxide film is formed on the bottom surface of the trench. Thus, the manufacturing process is simpler than the configuration of relaxing the electric field at the bottom of the trench.

Embodiment 2. FIG.
FIG. 20 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 20, the semiconductor device of the second embodiment is the following replacement of the semiconductor device of the first embodiment shown in FIG. 1. The first gate oxide film 26, the second gate oxide film 27, the first gate electrode 28, and the second gate electrode 29 are read as a gate oxide film 76, a field oxide film 77, a gate electrode 78, and a field electrode 79, respectively.

Further, the N ⁺ -type first source region 31 and the P ⁺ -type first source region 32 are read as an N ⁺ -type source region 81 and a P ⁺ -type source region 82, respectively. Further, the N ⁺ -type second source region 33 and the P ⁺ -type second source region 34 are both read as the N ⁺ -type drain region 83. That is, in the second embodiment, the N ⁺ -type drain region 83 is provided in the surface layer of the second mesa region 42 and there is no P-type region.

  Further, the first source electrode 35 and the second source electrode 36 are read as the source electrode 85 and the drain electrode 86, respectively. Further, the P-type first channel region 43 and the P-type second channel region 44 are read as a P-type channel region 93 and an N-type drain region 94, respectively. Since other configurations are the same as those in the first embodiment, detailed description thereof is omitted. In the semiconductor device of the second embodiment, a current flows in one direction from the drain electrode 86 to the source electrode 85.

  In the semiconductor device shown in FIG. 20, the concentration of the P-type floating region 45 is optimized, the source electrode 85 and the gate electrode 78 are set to the ground potential, and a high voltage less than the withstand voltage is applied to the drain electrode 86 and the field electrode 79. When tested, the electric field at the bottom of the trench is relaxed. Therefore, as in the first embodiment, the electric field in the overlap portion is relaxed, and depletion of the extended N drain region 25 due to the trapping of electrons in the thin insulating film at the bottom of the trench can be suppressed. The current is stabilized and the reliability is improved.

  Next, a manufacturing process of the semiconductor device shown in FIG. 20 will be described with reference to FIGS. 3 and 21 to 29. 3 and 21 to 29 are longitudinal sectional views showing the main part of the semiconductor device in the manufacturing stage in the order of processes. First, in the same manner as in the first embodiment, the N-type well region 22 is formed in the surface layer of the P-type semiconductor substrate 21, and the trench 24 is formed using the mask 51 (FIG. 3).

After removing the mask 51, buffer oxidation is performed to form a buffer oxide film 101. Then, a mask 102 is placed on the inside of the trench 24 and the second mesa region 42, and boron (B ₁₁ ), for example, is ion-implanted as a P-type impurity into the surface layer of the first mesa region 41 (FIG. 21). After removing the mask 102, the mask 103 is placed on the inside of the trench 24, on the first mesa region 41, and on the boundary between the P-type semiconductor substrate 21 and the N-type well region 22 on the substrate surface, and the second mesa. For example, phosphorus (P ₃₁ ) is ion-implanted as an N-type impurity into the surface layer of the region 42 (FIG. 22).

After the mask 103 is removed, the first mesa region 41 and the second mesa region 42 are covered with the mask 104, and phosphorus (P ₃₁ ), for example, is ion-implanted as an N-type impurity on the bottom surface of the trench 24 (FIG. 23). After the mask 104 is removed, thermal diffusion is performed to form a P-type channel region 93 and an N-type drain region 94 at the surface layer in the first mesa region 41, the surface layer in the second mesa region 42, and the bottom of the trench 24, respectively. And the extended N drain region 25 is formed. After removing the buffer oxide film 101, an oxide film to be a gate oxide film 76 and a field oxide film 77 is formed inside the trench 24, and a gate electrode 78 and a field electrode 79 are further formed inside thereof. Then, shadow oxidation is performed to form a shadow oxide film 105 (FIG. 24).

Next, a mask 106 is put on the first mesa region 41 and the second mesa region 42, and boron (B ₁₁ ), for example, is implanted as a P-type impurity only on the bottom surface of the trench 24 using the gate electrode 78 and the field electrode 79 as a mask. (FIG. 25). After removing the mask 106, thermal diffusion is performed to form a P-type floating region 45 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 26).

Here, the gate electrode 78 and the field electrode 79 to the mask, as shown in FIG. 26, and a margin L _df1 and L _df2 of the joint end of the extension N drain region 25 and the P-type floating region 45, This is to prevent the P-type floating region 45 from being connected to the P-type channel region 93. Another reason is that both ends of the P-type floating region 45 extend below the gate electrode 78 and the field electrode 79 so as to overlap the overlap portion.

Next, a mask 107 is put on the first mesa region 41 and the second mesa region 42, and arsenic (As, for example) is selectively used as an N-type impurity on the surface layer of the first mesa region 41 and the surface layer of the second mesa region 42. ₇₅ ) is ion-implanted (FIG. 27). After the mask 107 is removed, the first mesa region 41 and the second mesa region 42 are covered with the mask 108, and, for example, boron (B ₁₁ ) is selectively ionized as a P-type impurity on the surface layer of the first mesa region 41. Inject (FIG. 28).

After removing the mask 108, thermal diffusion is performed to form an N ⁺ type source region 81 and a P ⁺ type source region 82 in the surface layer of the P type channel region 93 (first mesa region 41), and an N type drain. N ⁺ -type drain region 83 is formed in the surface layer of region 94 (second mesa region 42). Subsequently, an interlayer insulating film 30 is deposited on the entire substrate, and the interlayer insulating film 30 is planarized by CMP (Chemical Mechanical Polishing) or the like (FIG. 29).

Finally, a contact hole is opened in the interlayer insulating film 30 to form a source electrode 85 electrically connected to the N ⁺ type source region 81 and the P ⁺ type source region 82, and to the N ⁺ type drain region 83. A drain electrode 86 connected to is formed. Thereby, the semiconductor device shown in FIG. 20 is completed.

Instead of the steps of FIGS. 3 and 21 to 24, the steps of FIGS. 30 to 33 may be performed. First, the N-type well region 22 is formed in the surface layer of the P-type semiconductor substrate 21. Then, a buffer oxide film 109 is formed on the substrate surface. Subsequently, a mask 110 is put on the region to be the second mesa region, and boron (B ₁₁ ), for example, is ion-implanted as a P-type impurity in the region to be the first mesa region (FIG. 30). Note that the step of FIG. 30 may be performed before the step of FIG.

Next, the region serving as the first mesa region is covered with a mask 111, and phosphorus (P ₃₁ ), for example, is ion-implanted as an N-type impurity into the region serving as the second mesa region (FIG. 31). After removing the buffer oxide film 109 and the mask 111, a mask 112 made of, for example, an oxide film is formed on the substrate surface, and trench etching is performed to form a trench 24 in the surface layer of the N-type well region 22. Subsequently, buffer oxidation is performed to form a buffer oxide film 113 inside the trench 24. Then, for example, phosphorus (P ₃₁ ) is ion-implanted as an N-type impurity into the bottom surface of the trench 24 (FIG. 32).

  Next, thermal diffusion is performed, so that the surface layer in the first mesa region 41, the surface layer in the second mesa region 42, and the bottom of the trench 24 have a P-type channel region 93, an N-type drain region 94, and an extended N-drain region, respectively. 25 is formed. After removing the buffer oxide film 113, an oxide film to be a gate oxide film 76 and a field oxide film 77 is formed inside the trench 24, and a gate electrode 78 and a field electrode 79 are further formed inside thereof (FIG. 33). Although not shown, the mask 112 is removed, shadow oxidation is performed to form a shadow oxide film, and then the process proceeds to the process of FIG.

Further, the step of FIG. 34 may be performed instead of the step of FIG. 24, the second mesa region 42 is covered with the mask 114, and the bottom surface of the trench 24 and the surface layer of the P-type channel region 93 are formed on the surface layer of the P-type channel region 93 using the gate electrode 78 and the field electrode 79 as a mask. For example, boron (B ₁₁ ) is ion-implanted as an impurity (FIG. 34). Then, the mask 114 is removed and the process proceeds to the process of FIG.

  When the process of FIG. 34 is performed, the concentration of the P-type channel region 93 is controlled by the ion implantation amount of the P-type impurity in both the processes of FIGS. By performing the process of FIG. 34, ion implantation can be performed without concern about the accuracy of mask displacement when miniaturization is performed, so that the manufacturing process is simplified.

  Further, instead of the step of FIG. 25, the steps of FIG. 35 and FIG. 36 may be performed, or the steps of FIG. 37 and FIG. 38 may be performed instead of the step of FIG. That is, in the step of FIG. 25 or FIG. 34, the ion implantation angle of the P-type impurity is the vertical direction (0 degree). In contrast, the oblique ion implantation method is applied in the steps of FIGS. 35 and 36 or the steps of FIGS. 37 and 38, and the ion implantation angle of the P-type impurity is inclined from the vertical direction.

In this oblique ion implantation method, as in the first embodiment, ion implantation is performed with θ = ± θ ₁ (where θ ₁ > 0). At that time, θ ₁ is set to satisfy the following expression (2). However, L _FG is the distance between the gate electrode 78 and the field electrode 79.
0 <tan θ ₁ ≦ L _FG / (2 · D _t ) (2)

  Then, it is preferable to perform ion implantation symmetrically in the positive direction shown in FIG. 35 or FIG. 37 and the negative direction shown in FIG. 36 or FIG. This is because, since the profile of the P-type floating region 45 is the same regardless of the trench stripe cross section, variations in device characteristics are reduced. According to the second embodiment, the same effect as in the first embodiment can be obtained.

Embodiment 3 FIG.
FIG. 39 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 39, in the semiconductor device of the third embodiment, the P-type floating region 45 is divided into a plurality of, for example, two P-type floating regions 46 and 47 in the semiconductor device of the first embodiment shown in FIG. The P-type floating region is not provided in the center of the bottom of the trench 24. These P-type floating regions 46 and 47 are separated from both the P-type first channel region 43 and the P-type second channel region 44.

  One P-type floating region 46 is formed so as to further overlap an overlap portion where the interface between the first gate electrode 28 and the interlayer insulating film 30 overlaps the extended N drain region 25 when viewed from above the element. Yes. The other P-type floating region 47 is formed so as to further overlap the overlap portion where the interface between the second gate electrode 29 and the interlayer insulating film 30 overlaps the extended N drain region 25 when viewed from above the element. Since other configurations are the same as those in the first embodiment, detailed description thereof is omitted.

  In the third embodiment, as in the first embodiment, the on-state current is stabilized and the reliability is improved by the electric field relaxation in the overlap portion. In addition, the on-resistance can be made lower than that in the first embodiment. it can. The reason is as follows. In the first embodiment, as shown in FIG. 40, since the P-type floating region 45 covers almost the entire interface between the bottom surface of the trench 24 and the extended N drain region 25, the on-current is increased in the extended N drain region 25. It flows through the high-resistance bulk region (the portion indicated by R1 in the figure).

  On the other hand, in the third embodiment, as shown in FIG. 41, since the P type floating regions 46 and 47 are divided, a part of the extended N drain region 25 is in contact with the bottom surface of the trench 24. For this reason, a resistance component R2 parallel to the resistance R1 of the high resistance bulk region is generated as a resistance component of the extension N drain region 25, and the drift resistance of the extension N drain region 25 is lower than R1. Therefore, the on-resistance is lower in the third embodiment than in the first embodiment.

Next, a manufacturing process of the semiconductor device shown in FIG. 39 will be described with reference to FIGS. 42 to 44 are longitudinal cross-sectional views showing the main parts of the semiconductor device in the manufacturing stage in the order of processes. First, similarly to the first embodiment, the steps of FIGS. Next, a mask 56 is put on the first mesa region 41 and the second mesa region 42, and for example, boron (B ₁₁₎ as a P-type impurity only on the bottom surface of the trench 24 using the first gate electrode 28 and the second gate electrode 29 as a mask. ) Is obliquely implanted (FIGS. 42 and 43).

  Next, after removing the mask 56, thermal diffusion is performed to form P-type floating regions 46 and 47 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 44). Thereafter, as in the first embodiment, the steps of FIGS. 9 to 11 are performed to form the first source electrode 35 and the second source electrode 36.

42 and 43, ion implantation is performed at θ = ± θ ₁ (where θ ₁ > 0). At that time, θ ₁ is set to satisfy the following expression (3). Note that the thickness of the mask 56 does not contribute to the shadow effect.
L _GG / (2 · D _t ) <tan θ ₁ ≦ L _GG / D _t (3)

The reason why the expression (3) needs to be satisfied is as follows. When oblique ion implantation is performed at θ ₁ where tan θ ₁ ≦ L _GG / (2 · D _t ), as shown in FIGS. 16 and 17, the two P-type floating regions 46 and 47 are connected at the bottom surface of the trench 24. Because it will end up. Further, when oblique ion implantation is performed with θ ₁ satisfying tan θ ₁ > L _GG / D _t , P-type impurities do not reach the bottom surface of the trench 24 due to the shadow effect, so that P-type floating regions 46 and 47 may be formed. It is not possible.

  According to the third embodiment, the same effect as in the first embodiment can be obtained. Further, since the P-type floating regions 46 and 47 can be formed using the shadow effect, it is not necessary to form a mask on the bottom surface of the trench 24 in order to form the P-type floating regions 46 and 47 separately. Therefore, the manufacturing process becomes simple. Note that three or more P-type floating regions may be formed inside the extended N drain region 25.

Embodiment 4 FIG.
FIG. 45 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 45, the semiconductor device of the fourth embodiment is similar to the third embodiment in the semiconductor device of the second embodiment shown in FIG. 20, and a plurality of, for example, two P-type floating regions 45 are provided. The floating regions 46 and 47 are divided so that there is no P-type floating region at the center of the bottom of the trench 24.

  One P-type floating region 46 is formed so as to further overlap an overlap portion where the interface between the gate electrode 78 and the interlayer insulating film 30 overlaps the extended N drain region 25 when viewed from above the element. The other P-type floating region 47 is formed so that the interface between the field electrode 79 and the interlayer insulating film 30 further overlaps with the overlapping portion where the extended N drain region 25 overlaps when viewed from above the element.

  Since other configurations are the same as those in the second embodiment, detailed description thereof is omitted. In the fourth embodiment, the on-resistance can be made lower than that in the second embodiment. The reason is as described in the third embodiment.

Next, a manufacturing process of the semiconductor device shown in FIG. 45 will be described with reference to FIGS. 46 to 48 are longitudinal sectional views showing the main parts of the semiconductor device in the manufacturing stage in the order of processes. First, similarly to the second embodiment, the steps of FIGS. 3 and 21 to 24 are performed. Next, the first mesa region 41 and the second mesa region 42 are covered with a mask 106, and for example, boron (B ₁₁ ) is obliquely ionized as a P-type impurity only on the bottom surface of the trench 24 using the gate electrode 78 and the field electrode 79 as a mask. Inject (FIGS. 46 and 47).

  Next, after removing the mask 106, thermal diffusion is performed to form P-type floating regions 46 and 47 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 48). Thereafter, as in the second embodiment, the steps of FIGS. 27 to 29 are performed to form the source electrode 85 and the drain electrode 86.

46 and 47, ion implantation is performed at θ = ± θ ₁ (where θ ₁ > 0). At that time, θ ₁ is set to satisfy the following expression (4). The reason why the expression (4) needs to be satisfied is as described in the third embodiment. Note that the thickness of the mask 106 does not contribute to the shadow effect.
L _FG / (2 · D _t ) <tan θ ₁ ≦ L _FG / D _t (4)

  According to the fourth embodiment, the same effect as in the second embodiment can be obtained. Further, since the P-type floating regions 46 and 47 are formed using the shadow effect as in the third embodiment, the manufacturing process is simplified. Note that three or more P-type floating regions may be formed inside the extended N drain region 25.

Embodiment 5. FIG.
The fifth embodiment is another method for manufacturing the semiconductor device of the first embodiment shown in FIG. A manufacturing process according to the fifth embodiment will be described with reference to FIGS. 49 and 50 are longitudinal sectional views showing the main part of the semiconductor device in the manufacturing stage in the order of processes.

First, similarly to the first embodiment, the steps of FIGS. 12 to 14 are performed. Next, with the mask 60 placed on the first mesa region 41 and the second mesa region 42, boron (for example, boron (P) as a P-type impurity only on the bottom surface of the trench 24 using the first gate electrode 28 and the second gate electrode 29 as a mask. B ₁₁ ) is ion-implanted (FIG. 49). Next, thermal diffusion is performed to form a P-type floating region 45 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 50). Thereafter, as in the first embodiment, the steps of FIGS. 9 to 11 are performed to form the first source electrode 35 and the second source electrode 36. Although not shown in the drawing, before proceeding to the step of FIG. 9, the mask 60 is removed and shadow oxidation is performed to form a shadow oxide film.

In the step of FIG. 49, the ion implantation angle of the P-type impurity is in the vertical direction (0 degree), but an oblique ion implantation method may be applied. In this oblique ion implantation method, ion implantation is performed with θ = ± θ ₁ (where θ ₁ > 0). At that time, the following expression (5) or (6) is satisfied. However, T ₁ is the thickness of the mask 60, and T ₂ is the sum of the thicknesses of the first gate oxide film 26 and the first gate electrode 28, or the second gate oxide film 27 and the second gate electrode 29. is there.

T ₁ ≦ (D _t · T ₂ ) / L _GG
When,
0 <tan θ ₁ ≦ L _GG / (2 · D _t ) (5)
T ₁ > (D _t · T ₂ ) / L _GG
When,
0 <tan θ ≦ (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} (6)

  According to the fifth embodiment, the same effect as in the first embodiment can be obtained. Further, by performing ion implantation for forming the P-type floating region 45 with the mask 60 left, it is not necessary to form the mask 56 before performing ion implantation as shown in FIG. It becomes.

Embodiment 6 FIG.
The sixth embodiment is another method for manufacturing the semiconductor device of the second embodiment shown in FIG. The manufacturing process of the sixth embodiment will be described with reference to FIGS. 51 and 52 are longitudinal sectional views showing the main parts of the semiconductor device in the manufacturing stage in the order of processes.

First, similarly to the second embodiment, the steps of FIGS. 30 to 33 are performed. Next, with the mask 112 placed on the first mesa region 41 and the second mesa region 42, for example, boron (B ₁₁ ) as a P-type impurity only on the bottom surface of the trench 24 using the gate electrode 78 and the field electrode 79 as a mask. Ions are implanted (FIG. 51). Next, thermal diffusion is performed to form a P-type floating region 45 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 52). Thereafter, as in the second embodiment, the steps of FIGS. 27 to 29 are performed to form the source electrode 85 and the drain electrode 86. Although not shown, before proceeding to the step of FIG. 27, the mask 112 is removed and shadow oxidation is performed to form a shadow oxide film.

In the process of FIG. 51, the ion implantation angle of the P-type impurity is in the vertical direction (0 degree), but an oblique ion implantation method may be applied. In this oblique ion implantation method, ion implantation is performed with θ = ± θ ₁ (where θ ₁ > 0). At that time, the following expression (7) or (8) is satisfied. However, T ₁ is the thickness of the mask 112, and T ₂ is the sum of the thicknesses of the gate oxide film 76 and the gate electrode 78, or the field oxide film 77 and the field electrode 79.

T ₁ ≦ (D _t · T ₂ ) / L _FG
When,
0 <tan θ ≦ L _FG / (2 · D _t ) (7)
T ₁ > (D _t · T ₂ ) / L _FG
When,
0 <tan θ ≦ (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} (8)

  According to the sixth embodiment, the same effect as in the second embodiment can be obtained. In addition, by performing ion implantation for forming the P-type floating region 45 while leaving the mask 112, it is not necessary to form the mask 106 before performing ion implantation as shown in FIG. It becomes.

Embodiment 7 FIG.
The seventh embodiment is another method for manufacturing the semiconductor device of the third embodiment shown in FIG. A manufacturing process according to the seventh embodiment will be described with reference to FIGS. 53 to 55 are longitudinal sectional views showing the main part of the semiconductor device in the manufacturing stage in the order of processes.

First, the steps of FIGS. 12 to 14 are performed as in the first or fifth embodiment. Next, with the mask 60 placed on the first mesa region 41 and the second mesa region 42, boron (for example, boron (P) as a P-type impurity only on the bottom surface of the trench 24 using the first gate electrode 28 and the second gate electrode 29 as a mask. B ₁₁ ) is implanted obliquely (FIGS. 53 and 54). Next, thermal diffusion is performed to form P-type floating regions 46 and 47 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 55). Thereafter, as in the first embodiment, the steps of FIGS. 9 to 11 are performed to form the first source electrode 35 and the second source electrode 36. Although not shown in the drawing, before proceeding to the step of FIG. 9, the mask 60 is removed and shadow oxidation is performed to form a shadow oxide film.

53 and 54, ion implantation is performed with θ = ≦ θ ₁ (where θ ₁ > 0). At that time, the following expression (9) or (10) is satisfied. However, T ₁ is the thickness of the mask 60, and T ₂ is the sum of the thicknesses of the first gate oxide film 26 and the first gate electrode 28, or the second gate oxide film 27 and the second gate electrode 29. is there.

T ₁ ≦ (D _t · T ₂ ) / L _GG
When,
L _GG / (2 · D _t ) <tan θ ₁ ≦ L _GG / D _t (9)
T ₁ > (D _t · T ₂ ) / L _GG
When,
(2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} <tan θ ₁ ≦ (2 · T ₂ + L _GG ) / (T ₁ + D _t ) (10)

Equation (9) corresponds to the case where the thickness T ₁ of the mask 60 is thin and the mask 60 does not contribute to the shadow effect. On the other hand, equation (10) corresponds to the case where the thickness T ₁ of the mask 60 is thick and the mask 60 contributes to the shadow effect.

  According to the seventh embodiment, the same effect as in the third embodiment can be obtained. Further, by performing ion implantation for forming the P-type floating regions 46 and 47 while leaving the mask 60, it is not necessary to form the mask 56 before performing ion implantation as shown in FIG. Becomes simple. Note that three or more P-type floating regions may be formed inside the extended N drain region 25.

Embodiment 8 FIG.
The eighth embodiment is another method for manufacturing the semiconductor device of the fourth embodiment shown in FIG. A manufacturing process according to the eighth embodiment will be described with reference to FIGS. 56 to 58 are longitudinal sectional views showing the main parts of the semiconductor device in the manufacturing stage in the order of processes.

First, similarly to the second or sixth embodiment, the steps of FIGS. 30 to 33 are performed. Next, with the mask 112 placed on the first mesa region 41 and the second mesa region 42, for example, boron (B ₁₁ ) as a P-type impurity only on the bottom surface of the trench 24 using the gate electrode 78 and the field electrode 79 as a mask. Diagonal ion implantation is performed (FIGS. 56 and 57). Next, thermal diffusion is performed to form P-type floating regions 46 and 47 at the bottom of the trench 24 in the extended N drain region 25 (FIG. 58). Thereafter, as in the second embodiment, the steps of FIGS. 27 to 29 are performed to form the source electrode 85 and the drain electrode 86. Although not shown, before proceeding to the step of FIG. 27, the mask 112 is removed and shadow oxidation is performed to form a shadow oxide film.

56 and 57, ion implantation is performed at θ = ± θ ₁ (where θ ₁ > 0). At that time, the following expression (11) or (12) is satisfied. However, T ₁ is the thickness of the mask 112, and T ₂ is the sum of the thicknesses of the gate oxide film 76 and the gate electrode 78, or the field oxide film 77 and the field electrode 79.

T ₁ ≦ (D _t · T ₂ ) / L _FG
When,
L _FG / (2 · D _t ) <tan θ ₁ ≦ L _FG / D _t (11)
T ₁ > (D _t · T ₂ ) / L _FG
When,
(2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} <tan θ ₁ ≦ (2 · T ₂ + L _FG ) / (T ₁ + D _t ) (12)

Equation (11) corresponds to the case where the thickness T ₁ of the mask 112 is thin and the mask 112 does not contribute to the shadow effect. On the other hand, equation (12) corresponds to the case where the thickness T ₁ of the mask 112 is thick and the mask 112 contributes to the shadow effect.

  According to the eighth embodiment, the same effect as in the fourth embodiment can be obtained. Further, by performing ion implantation for forming the P-type floating regions 46 and 47 while leaving the mask 112, it is not necessary to form the mask 106 before performing ion implantation as shown in FIG. Becomes simple. Note that three or more P-type floating regions may be formed inside the extended N drain region 25.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the first to eighth embodiments, the conductivity of the well region 22 may be P-type. In that case, in the first, third, fifth or seventh embodiment, it is desirable that the conductivity of the semiconductor substrate 21 be N-type. The reason for this is that if the semiconductor substrate 21 and the well region 22 are both P-type, the P-type first channel region 43 and the second channel region 44 and the P-type semiconductor substrate 21 have the same potential. This is because the electrode 35 and the second source electrode 36 have the same potential and do not function as a bidirectional MOSFET. However, the conductivity of the semiconductor substrate 21 may be P-type as long as the two extended N drain regions 25 sandwiching the first mesa region 41 are electrically connected.

  In the first to eighth embodiments, the conductivity of the semiconductor substrate 21 may be either P-type or N-type. Furthermore, in Embodiments 1 to 8, the conductivity of all semiconductors may be reversed.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a low on-resistance power MOSFET suitable for an integrated circuit that controls a large current with a high breakdown voltage, and in particular, an IC for a switching power supply, an automobile power system It is suitable for power MOSFETs integrated in driving ICs, flat panel display driving ICs, and the like.

It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing explaining the electric field distribution of the semiconductor device shown in FIG. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing explaining the drift resistance of the semiconductor device shown in FIG. FIG. 40 is a cross-sectional view illustrating drift resistance of the semiconductor device shown in FIG. 39. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 3 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device concerning Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 4 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 5 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 5 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 6 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 7 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 8 of this invention. It is a longitudinal cross-sectional view which shows the principal part in the manufacture stage of the semiconductor device concerning Embodiment 8 of this invention. It is sectional drawing which shows an example of the horizontal type power element to which the conventional trench structure is applied. It is sectional drawing which shows the other example of the horizontal type power element to which the conventional trench structure is applied. FIG. 60 is a cross-sectional view illustrating an electric field distribution of the horizontal power element shown in FIG. 59.

Explanation of symbols

21 Semiconductor substrate 22 Well region 24 Trench 25, 83, 94 Drain region 26, 27, 76 Gate insulating film 28, 29, 78 Gate electrode 30 Interlayer insulating film 31, 33, 81 Source region 35, 36, 85 Source electrode 41 First 1 mesa region 42 second mesa region 43, 44, 93 channel region 45 floating region 77 field oxide film 79 field electrode 86 drain electrode

Claims (24)

A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa A semiconductor device that draws current in a region and a second mesa region,
A well region formed in a surface layer of a semiconductor substrate;
A drain region of a first conductivity type provided at a bottom portion of a trench formed in the well region in the well region;
A first source region of a first conductivity type provided in a surface layer of the first mesa region;
A second conductivity type second electrode provided along the sidewall of the trench and in contact with both the first source region and the drain region in the first mesa region between the first source region and the drain region. One channel region;
A first gate insulating film provided on a sidewall of the trench along the first channel region;
A first gate electrode provided inside the trench along the first gate insulating film;
A second source region of the first conductivity type provided in the surface layer of the second mesa region;
A second conductivity type second electrode provided along the sidewall of the trench and in contact with both the second source region and the drain region in the second mesa region between the second source region and the drain region. A two-channel region;
A second gate insulating film provided on a sidewall of the trench along the second channel region;
A second gate electrode provided inside the trench along the second gate insulating film;
Within the drain region, provided at the bottom of the trench and away from both the first channel region and the second channel region, and when viewed from above, on both the first gate electrode and the second gate electrode Overlapping floating regions of the second conductivity type;
A first source electrode electrically connected to the first source region;
A second source electrode electrically connected to the second source region;
A semiconductor device comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa A semiconductor device that draws a source current in a region and draws a drain current in a second mesa region,
A well region formed in a surface layer of a semiconductor substrate;
A first drain region of a first conductivity type provided at a bottom of a trench formed in the well region in the well region;
A source region of a first conductivity type provided in a surface layer of the first mesa region;
A channel of a second conductivity type provided along the sidewall of the trench and in contact with both the source region and the first drain region in the first mesa region between the source region and the first drain region Area,
A gate insulating film provided on a sidewall of the trench along the channel region;
A gate electrode provided inside the trench along the gate insulating film;
A second drain region of the first conductivity type provided in the surface layer of the second mesa region;
The first mesa region between the second drain region and the first drain region is provided along a side wall of the trench and is in contact with both the second drain region and the first drain region. A third drain region of conductivity type;
A field insulating film provided on a sidewall of the trench along the third drain region;
A field electrode provided inside the trench along the field insulating film;
Second conductivity in the first drain region, which is provided at the bottom of the trench and is separated from both the channel region and the third drain region and overlaps both the gate electrode and the field electrode when viewed from above. A floating area of the mold,
A source electrode electrically connected to the source region;
A second drain electrode electrically connected to the second drain region;
A semiconductor device comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa A semiconductor device that draws current in a region and a second mesa region,
A well region formed in a surface layer of a semiconductor substrate;
A drain region of a first conductivity type provided at a bottom portion of a trench formed in the well region in the well region;
A first source region of a first conductivity type provided in a surface layer of the first mesa region;
A second conductivity type second electrode provided along the sidewall of the trench and in contact with both the first source region and the drain region in the first mesa region between the first source region and the drain region. One channel region;
A first gate insulating film provided on a sidewall of the trench along the first channel region;
A first gate electrode provided inside the trench along the first gate insulating film;
A second source region of the first conductivity type provided in the surface layer of the second mesa region;
A second conductivity type second electrode provided along the sidewall of the trench and in contact with both the second source region and the drain region in the second mesa region between the second source region and the drain region. A two-channel region;
A second gate insulating film provided on a sidewall of the trench along the second channel region;
A second gate electrode provided inside the trench along the second gate insulating film;
In the drain region, a first of the second conductivity type is provided at the bottom of the trench and is separated from both the first channel region and the second channel region and overlaps the first gate electrode when viewed from above. A floating area,
In the drain region, a second conductivity type second layer is provided at the bottom of the trench and is separated from both the first channel region and the second channel region and overlaps the second gate electrode when viewed from above. A floating area,
A first source electrode electrically connected to the first source region;
A second source electrode electrically connected to the second source region;
A semiconductor device comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa A semiconductor device that draws a source current in a region and draws a drain current in a second mesa region,
A well region formed in a surface layer of a semiconductor substrate;
A first drain region of a first conductivity type provided at a bottom of a trench formed in the well region in the well region;
A source region of a first conductivity type provided in a surface layer of the first mesa region;
A channel of a second conductivity type provided along the sidewall of the trench and in contact with both the source region and the first drain region in the first mesa region between the source region and the first drain region Area,
A gate insulating film provided on a sidewall of the trench along the channel region;
A gate electrode provided inside the trench along the gate insulating film;
A second drain region of the first conductivity type provided in the surface layer of the second mesa region;
The first mesa region between the second drain region and the first drain region is provided along a side wall of the trench and is in contact with both the second drain region and the first drain region. A third drain region of conductivity type;
A field insulating film provided on a sidewall of the trench along the third drain region;
A field electrode provided inside the trench along the field insulating film;
In the first drain region, a first floating region of a second conductivity type that is provided at the bottom of the trench and is separated from both the channel region and the third drain region and overlaps the gate electrode when viewed from above. When,
In the first drain region, a second floating region of a second conductivity type provided at the bottom of the trench and is separated from both the channel region and the third drain region and overlaps the field electrode when viewed from above. When,
A source electrode electrically connected to the source region;
A second drain electrode electrically connected to the second drain region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the well region is of a first conductivity type.   The semiconductor device according to claim 1, wherein the well region is of a second conductivity type.   The semiconductor device according to claim 1, wherein the semiconductor substrate is of a first conductivity type.   The semiconductor device according to claim 1, wherein the semiconductor substrate is of a second conductivity type. A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa In manufacturing a semiconductor device that draws current in the region and the second mesa region,
Forming a well region in a surface layer of a semiconductor substrate;
Forming a trench in the surface layer of the well region and dividing the surface layer of the semiconductor substrate into a first mesa region and a second mesa region;
A surface layer in the first mesa region, a surface layer in the second mesa region, and a bottom portion of the trench have a second conductivity type first channel region, a second conductivity type second channel region, and a first conductivity type, respectively. Forming a drain region of
Forming a first gate insulating film and a second gate insulating film on the side wall along the first channel region and the side wall along the second channel region of the trench, respectively;
Forming a first gate electrode and a second gate electrode inside the trench along the first gate insulating film and the second gate insulating film, respectively;
Second conductivity that is separated from both the first channel region and the second channel region at the bottom of the trench in the drain region and overlaps both the first gate electrode and the second gate electrode when viewed from above. Forming a floating region of the mold by ion implantation of impurities using the first gate electrode and the second gate electrode as a mask;
Forming a first conductivity type first source region and a first conductivity type second source region on a surface layer of the first mesa region and a surface layer of the second mesa region, respectively;
Filling the trench with an interlayer insulating film;
Opening a contact hole in the interlayer insulating film, and forming a first source electrode and a second source electrode that are electrically connected to the first source region and the second source region, respectively, through the contact hole;
A method for manufacturing a semiconductor device, comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa In manufacturing a semiconductor device that draws current in the region and the second mesa region,
Forming a well region in a surface layer of a semiconductor substrate;
Forming a second conductivity type channel region in a surface layer in the well region;
An etching mask having a trench pattern is formed on the substrate surface, a trench is formed in the surface layer of the well region using the etching mask, and the surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region Dividing the surface layer of the channel region formed in the well region into a first channel region in the first mesa region and a second channel region in the second mesa region;
Forming a drain region of a first conductivity type at the bottom of the trench;
Forming a first gate insulating film and a second gate insulating film on the side wall along the first channel region and the side wall along the second channel region of the trench, respectively;
Forming a first gate electrode and a second gate electrode inside the trench along the first gate insulating film and the second gate insulating film, respectively;
Second conductivity that is separated from both the first channel region and the second channel region at the bottom of the trench in the drain region and overlaps both the first gate electrode and the second gate electrode when viewed from above. Forming a floating region of a mold by ion implantation of impurities using the etching mask, the first gate electrode and the second gate electrode as a mask;
After removing the etching mask, forming a first conductivity type first source region and a first conductivity type second source region on the surface layer of the first mesa region and the surface layer of the second mesa region, respectively. When,
Filling the trench with an interlayer insulating film;
Opening a contact hole in the interlayer insulating film, and forming a first source electrode and a second source electrode that are electrically connected to the first source region and the second source region, respectively, through the contact hole;
A method for manufacturing a semiconductor device, comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa In manufacturing a semiconductor device that draws a source current in a region and draws a drain current in a second mesa region,
Forming a well region in a surface layer of a semiconductor substrate;
Forming a trench in the surface layer of the well region and dividing the surface layer of the semiconductor substrate into a first mesa region and a second mesa region;
Forming a second conductivity type channel region on a surface layer in the first mesa region;
Forming a first drain region of the first conductivity type on a surface layer in the second mesa region;
Forming a first conductivity type second drain region at the bottom of the trench;
Forming a gate insulating film and a field insulating film on the sidewall of the trench along the channel region and the sidewall of the first drain region, respectively;
Forming a gate electrode and a field electrode inside the trench along the gate insulating film and the field insulating film, respectively;
A floating region of a second conductivity type at the bottom of the trench in the second drain region that is separated from both the channel region and the first drain region and overlaps both the gate electrode and the field electrode when viewed from above Forming by ion implantation of impurities using the gate electrode and the field electrode as a mask,
Forming a first conductivity type source region in a surface layer of the first mesa region;
Filling the trench with an interlayer insulating film;
Forming a contact hole in the interlayer insulating film, and forming a source electrode and a drain electrode that are electrically connected to the source region and the first drain region through the contact hole, respectively;
A method for manufacturing a semiconductor device, comprising: A surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, and the first mesa In manufacturing a semiconductor device that draws a source current in a region and draws a drain current in a second mesa region,
Forming a well region in a surface layer of a semiconductor substrate;
Forming a second conductivity type channel region and a first conductivity type first drain region on a surface layer in the well region;
An etching mask having a trench pattern is formed on the substrate surface, a trench is formed in the surface layer of the well region using the etching mask, and the surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region Separating the channel region in the first mesa region and the first drain region in the second mesa region;
Forming a first conductivity type second drain region at the bottom of the trench;
Forming a gate insulating film and a field insulating film on the sidewall of the trench along the channel region and the sidewall of the first drain region, respectively;
Forming a gate electrode and a field electrode inside the trench along the gate insulating film and the field insulating film, respectively;
A floating region of a second conductivity type at the bottom of the trench in the second drain region that is separated from both the channel region and the first drain region and overlaps both the gate electrode and the field electrode when viewed from above Forming by ion implantation of impurities using the etching mask, the gate electrode and the field electrode as a mask;
Forming a first conductivity type source region on a surface layer of the first mesa region after removing the etching mask;
Filling the trench with an interlayer insulating film;
Forming a contact hole in the interlayer insulating film, and forming a source electrode and a drain electrode that are electrically connected to the source region and the first drain region through the contact hole, respectively;
A method for manufacturing a semiconductor device, comprising: The depth of the trench is D _t , the distance between the first gate electrode and the second gate electrode is L _GG, and the tilt plane and the trench when performing ion implantation of impurities to form the floating region If the angle formed by a plane parallel to the side wall surface is θ,
−L _GG / (2 · D _t ) ≦ tan θ ≦ L _GG / (2 · D _t )
The method of manufacturing a semiconductor device according to claim 9, wherein the method is a semiconductor device manufacturing method. The depth of the trench is D _t , the distance between the first gate electrode and the second gate electrode is L _GG, and the tilt plane and the trench when performing ion implantation of impurities to form the floating region If the angle formed by a plane parallel to the side wall surface is θ,
L _GG / (2 · D _t ) <| tan θ | ≦ L _GG / D _t
The method of manufacturing a semiconductor device according to claim 9, wherein the method is a semiconductor device manufacturing method. The depth of the trench is D _t , the distance between the first gate electrode and the second gate electrode is L _GG , the thickness of the etching mask is T _1, and the first gate electrode and the second gate Tilt planes when ion implantation of impurities is performed to form the floating region, where the thickness of each electrode is T ₃ and the thickness of each of the first gate insulating film and the second gate insulating film is T _4. And an angle formed by a plane parallel to the side wall surface of the trench is θ, and the sum of T ₃ and T ₄ is T ₂ .
T ₁ > (D _t · T ₂ ) / L _GG
And- (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} ≦ tan θ ≦ (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )}
The method of manufacturing a semiconductor device according to claim 10, wherein: The depth of the trench is D _t , the distance between the first gate electrode and the second gate electrode is L _GG , the thickness of the etching mask is T _1, and the first gate electrode and the second gate Tilt planes when ion implantation of impurities is performed to form the floating region, where the thickness of each electrode is T ₃ and the thickness of each of the first gate insulating film and the second gate insulating film is T _4. And an angle formed by a plane parallel to the side wall surface of the trench is θ, and the sum of T ₃ and T ₄ is T ₂ .
T ₁ > (D _t · T ₂ ) / L _GG
And (2 · T ₂ + L _GG ) / {2 · (T ₁ + D _t )} <| tan θ | ≦ (2 · T ₂ + L _GG ) / (T ₁ + D _t )
The method of manufacturing a semiconductor device according to claim 10, wherein: The depth of the trench is D _t , the distance between the gate electrode and the field electrode is L _FG, and the tilt surface and the side wall surface of the trench are used when ion implantation of impurities is performed to form the floating region. Assuming that the angle between the parallel surfaces is θ,
−L _FG / (2 · D _t ) ≦ tan θ ≦ L _FG / (2 · D _t )
The method of manufacturing a semiconductor device according to claim 11, wherein the method is a semiconductor device manufacturing method. The depth of the trench is D _t , the distance between the gate electrode and the field electrode is L _FG, and the tilt surface and the side wall surface of the trench are used when ion implantation of impurities is performed to form the floating region. Assuming that the angle between the parallel surfaces is θ,
L _FG / (2 · D _t ) <| tan θ | ≦ L _FG / D _t
The method of manufacturing a semiconductor device according to claim 11, wherein the method is a semiconductor device manufacturing method. The depth of the trench and D _t, said distance between the gate electrode and the field electrode is L _FG, the thickness of the etching mask and T _1, the gate electrode and the field thickness of each T ₃ electrodes The thicknesses of the gate insulating film and the field insulating film are each T _4, and a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the sidewall of the trench If the angle formed is θ and the sum of T ₃ and T ₄ is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _FG
And- (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} ≦ tan θ ≦ (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )}
The method of manufacturing a semiconductor device according to claim 12, wherein: The depth of the trench and D _t, said distance between the gate electrode and the field electrode is L _FG, the thickness of the etching mask and T _1, the gate electrode and the field thickness of each T ₃ electrodes The thicknesses of the gate insulating film and the field insulating film are each T _4, and a tilt plane when performing ion implantation of impurities to form the floating region and a plane parallel to the sidewall of the trench If the angle formed is θ and the sum of T ₃ and T ₄ is T ₂ ,
T ₁ > (D _t · T ₂ ) / L _FG
And (2 · T ₂ + L _FG ) / {2 · (T ₁ + D _t )} <| tan θ | ≦ (2 · T ₂ + L _FG ) / (T ₁ + D _t )
The method of manufacturing a semiconductor device according to claim 12, wherein:   The method of manufacturing a semiconductor device according to claim 9, wherein the well region is of a first conductivity type.   The method of manufacturing a semiconductor device according to claim 9, wherein the well region is of a second conductivity type.   The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor substrate is of a first conductivity type. The method for manufacturing a semiconductor device according to claim 9, wherein the semiconductor substrate is of a second conductivity type.

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