JPH11284187A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lateral double diffusion MOSFET of low on resistance. SOLUTION: A lateral double diffusion MOSFET 100 comprises a substrate comprising a main surface 34, a gate electrode 32 provided in a recess 31 formed in a specified region of the main surface 34, a source electrode, a drain electrode, a base 36, and a channel formed near the gate electrode 32 among the base 36.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to semiconductor devices, and more particularly to a lateral double-diffused MOSFET.

[0002]

2. Description of the Related Art Field-effect transistors (MOSFETs) can be roughly classified according to whether a current flows in a vertical direction or in a surface direction of the element. The former is called a vertical element and the latter is called a horizontal element.
In vertical devices, one of the main electrodes is on the back of the semiconductor device,
Since it has excellent current-carrying capacity per unit area, it is often used as an individual element that handles particularly high power. On the other hand, a horizontal element is suitable for integration since all electrodes can be arranged on one surface, and is often used as a component element of an integrated circuit. Lateral double diffused MOSFET as lateral element
(LDMOSFET) are known.

FIG. 1 shows a conventional lateral double-diffused MOSF.
The plan view 10 of the ET 50 is shown.

FIG. 2 is a sectional view 20 taken along the line XX in FIG.
Is shown. In the LDMOS 50, the p-type diffusion layer 26 and the n-type source diffusion layer are double-diffused on the surface by a self-alignment (self-alignment) technique, and the channel 23 is formed on the surface of the p-type diffusion layer 26 immediately below the gate electrode 22. Things. A region from one end of the channel 23 to one end of the drain diffusion layer is called a drift region in a broad sense. Since the drift region in a broad sense is essentially an n-type, it becomes an accumulation region when a positive voltage is applied to the gate (hereinafter, a “drift (accumulation) region”).
), The n-type channel region 2 where the p-type diffusion layer 26 is inverted.
The resistance becomes lower than that of 3. Generally, as the drift length increases, the on-resistance increases, and as the gate width and the drift (accumulation) region width increase, the on-resistance decreases. Here, the drift length refers to the channel 23
Of the n-type well from one end to the end of the drain diffusion layer (see FIG. 2), gate width and drift (accumulation)
The region width refers to a width w (see FIG. 4) between fields (not shown).

Both the n-type source diffusion layer and the n-type drain diffusion layer are formed by implanting ions into the substrate surface and then thermally diffusing them, and are connected to the source and drain electrodes, respectively.

FIG. 2 shows a structure in the case where the gate 22 and the drain diffusion layer overlap each other. However, the drain and the gate may be offset to increase the breakdown voltage (not shown). In this structure, the resistance of the drift (accumulation) region is low as described above, but the resistance is high in the drift region having no gate on the top because no accumulation occurs.

The LDMOS is suitable for realizing a high-speed operation with an increase in alternate conductance and power because the channel structure can be easily formed by a self-alignment technique.
Often used for intelligent power ICs.

[0008]

[Problem to be Solved] In general, when an LDMOS is used in an intelligent power IC, it is important to reduce the resistance (on-resistance) during conduction in order to reduce the Joule heat loss. .

Hitherto, to reduce the on-resistance, optimization of impurity distribution, improvement of gate electrode arrangement, shrinkage of unit element size, and the like have been performed.

However, in the conventional LDMOS, since the channel is formed only in a two-dimensional plane, there is a problem that these methods have limitations.

It is, therefore, an object of the present invention to provide an LDMOS in which a channel is formed three-dimensionally, the channel density is increased, and the on-resistance per unit area is reduced.

Another object of the present invention is to increase the channel width and the drift (accumulation) region width even when the gate arrangement when the LDMOS wafer is viewed from above is the same, so that the unit area per unit area is increased. An object of the present invention is to provide an LDMOS with a reduced on-resistance.

A further object of the present invention is to provide a low on-resistance LDMOS which can use all conventional techniques for reducing on-resistance.
It is to provide.

Another object of the present invention is to reduce the chip cost by reducing the area of the LDMOS section and the element size of the intelligent power IC.

Another object of the present invention is to reduce the output loss of an LDMOS.

[0016]

SUMMARY OF THE INVENTION The above and other objects are to provide a lateral double-diffused MOSFET (100) having an n-type well having a main surface (34) and a predetermined region on the main surface (34). A gate (32) provided on the recess (31) formed at a predetermined interval, a p-type base (36), a channel (33) formed near the gate (32) of the p-type base (36), and This is realized by a lateral double-diffused MOSFET having a drift (accumulation) region (35).

[0017]

FIG. 3 is a cross-sectional view of an LDMOS 100 having a drain metal, a source metal, a trench 31, a gate electrode 32, and a drift (accumulation) region 35 according to an embodiment of the present invention. Compared to FIG. 2, FIG.
It should be noted that 1 and the gate electrode 32 are formed. Further, while the channel 23 and the drift (accumulation) region 25 of FIG. 2 are formed in a two-dimensional plane along the main surface 23 of the substrate, the channel 33 and the drift (accumulation) region 35 of the present invention are It should be noted that it is formed three-dimensionally.

FIG. 4 shows an LDMOS 10 according to an embodiment of the present invention.
0 shows a plan view 40 of the gate electrode 32. Hereinafter, a detailed description will be given with reference to an enlarged view of the vicinity of the gate electrode 32 of the LDMOS 100 according to one embodiment of the present application. In the present application, a ladder-like trench 31 is formed in a predetermined region on a main surface 34 of a substrate at a predetermined interval, and a gate electrode 32 is provided along the ladder-like trench 31. Trench 31 may be provided using any technique known to those skilled in the art. Hereinafter, the trench 31 will be described as an example.
Is described as an example, but the shape is not limited to a rectangle, and may be any shape such as a square, a sphere, a rectangle, and a spherical corner. Furthermore, the main surface 34 may be made wavy by a selective oxidation method (LOCOS: local oxidation of silicon) or the like. Accordingly, the term depression as used in the claims of this application is intended to include trenches and any grooves and depressions formed by chemical and mechanical methods, which are provided using techniques widely known to those skilled in the art. Further, the length, width, and depth of the trench 31 are not particularly limited. The shape of the gate electrode 32 is not limited to the concave shape, but may be any shape such as a vertically inverted convex shape or a square shape. After forming the trench 31 and the gate,
The LDMOS 100 is formed by ion-implanting the n-type source diffusion layer and the n-type drain diffusion layer into the substrate main surface 34 and then thermally diffusing the same by a method known to those skilled in the art.

FIG. 5 is a sectional view taken along the line DD in FIG.
Indicates 0. Although the depth of the trench 31 is not particularly limited, preferably, the bottom surface of the gate electrode 32 is
The p-type diffusion layer 36 is deeper than the main surface 34 (see FIG. 7)
(See FIG. 6).

FIG. 6 is a sectional view taken along the line AA in FIG.
Indicates 0. A trench 31 is formed in a predetermined region on the main surface 34 of the LDMOS 100 in a concave shape, and the gate electrode 32 is formed in a concave shape along the trench 31. The channel 33 is formed vertically in the p-type diffusion layer 36 near the side surface of the trench 31, and the drift (accumulation) region 35 is near the side surface and bottom surface of the trench 31 from one end of the channel 33 to the end of the drain diffusion layer. Are formed in the vertical and horizontal directions in the n-type well.

FIG. 7 is a sectional view taken along the line BB in FIG.
Indicates 0. There is no trench between BB and it is the same as the sectional view of the gate electrode of the conventional LDMOS. Therefore, in this case,
The channel 33 and the drift (accumulation) region 35 are formed two-dimensionally in the lateral direction in the p-type diffusion layer 36 and the n-type well below the gate electrode.

FIG. 8 is a sectional view taken along the line CC in FIG.
Indicates 0. In this case, the channel 33 is formed vertically in the p-type diffusion layer 36 near the trench side surface, and the drift (accumulation) region 35 is formed in the n-type well near the side surface of the trench 31 in the vertical direction. Thus, by providing the trench 31, the channel 33 and the drift (accumulation) region 35 can be three-dimensionally formed so as to surround the trench 31.

The operation will be described below.

In the present application, the channel 33 and the drift (accumulation) region 35 are formed three-dimensionally, so that the LDMOS 1
It is verified below whether or not there is a problem with the operation of 00.

FIG. 9 is a graph showing the operation of the LDMOS 50 according to the prior art. This graph shows the drain voltage (Vd
rain) is shown when the drain current (Idrain) is changed. This graph shows a case where the gate voltage (Vgate) is reduced by 2 volts in order from 12 volts and 10 volts from the top.

FIG. 10 shows an LDMOS 1 according to an embodiment of the present invention.
13 is a graph showing the operation of the 00. This graph is shown in FIG.
7 is a graph showing a drain current (Idrain) when the drain voltage (Vdrain) is changed between A, that is, in the case of FIG. 6. This graph shows a case where the gate voltage is reduced in order of 12 volts and 10 volts from the top in steps of 2 volts, similarly to FIG. As shown in the graph of FIG. 10, even if the gate electrode 32 is formed in a concave shape and the channel 33 is formed in a three-dimensional three-dimensional manner, the operation of the LDMOS 100 itself differs only in the value of the drain current as compared with the LDMOS 50 according to the related art. It was confirmed that there was no problem.

Comparing FIG. 9 with FIG. 10, in the former case, for example, when Vgate = 12v and Vdrain = 12v, I
drain is about 1.2 mA / um, whereas in the latter case,
Idrain is about 0.36 mA / um. From this trench 3
It can be seen that the drain current flows more easily in the region having no 1. This is because the provision of the trench 31 increases the length of the drift (accumulation) region, thereby acting as a series resistance, thereby increasing the on-resistance.

Next, the change in the on-resistance of the LDMOS per unit area due to the difference in the shape of the trench 31, that is, the difference in the channel length and the drift (accumulation) region length will be examined below.

FIG. 11 shows a sectional view of an LDMOS 50 according to the prior art. The channel 23 and the drift (accumulation) region 25 are formed two-dimensionally in the lateral direction in the p-type diffusion layer 36 and the n-type well below the gate electrode.

FIG. 12 shows an LDMOS 1 according to an embodiment of the present invention.
00 shows a sectional view. In this case, the channel 33 and the drift (accumulation) region 35 are formed in the p-type diffusion layer 36 and the n-type well so as to surround the vicinity of the side surface and the bottom surface of the trench 31, respectively.

FIG. 13 shows an LDMOS 1 according to an embodiment of the present invention.
12 is a sectional view of the LDMOS 100 when only the width of the trench 31 is smaller than that of the embodiment of FIG. In this case, the channel 33 and the drift (accumulation) region 35
Are formed in the p-type diffusion layer 36 and the n-type well so as to surround the vicinity of the side surface and the bottom surface of the trench 31, respectively.

FIG. 14 shows an LDMOS 1 according to an embodiment of the present invention.
12 is a sectional view of the LDMOS 100 when only the depth of the trench 31 is smaller than that of the embodiment of FIG.
In this case, the channel 33 and the drift (accumulation) region 3
5 is formed in the p-type diffusion layer 36 and the n-type well so as to surround the vicinity of the side surface and the bottom surface of the trench 31, respectively.

FIG. 15 shows each LDMOS of FIGS.
3 is a graph showing the on-resistance per unit area (RonA). According to this, the on-resistance of the LDMOS 50 according to the prior art is the lowest, followed by the shallow trench 31 of FIG. 14, the narrow trench 31 of FIG. 13, and the case of the highest on-resistance is the example of FIG. Was. This indicates that simply forming the trench 31 increases the on-resistance.

Next, the effect when the gate width w and the drift (accumulation) region width (see FIG. 4) are taken into consideration will be verified below.

FIG. 16 shows an LDMOS 1 according to an embodiment of the present invention.
10 is a graph showing the effect of the on-resistance (Ron) of 00.
When obtaining the on-resistance of the LDMOS 100 according to the embodiment of the present application, the variables cannot be easily verified because the three-dimensional channel 33 and the drift (accumulation) region 35 of the LDMOS 100 are used. So, taking a standard trench as an example, the conventional LDMOS50
The on-resistance of the LDMOS 100 of the present application when the on-resistance of the LDMOS is set to 1 is expressed using a coefficient k. The on-resistance of the gate width in a region not having the trench 31 is referred to as Rc as a unit width,
The resistance of the side surface of the trench 31 is called Rsw, and the resistance of the bottom surface of the trench 31 is called Rt. In one embodiment, the depth and width of the trench 31 are the same and the channel width is 5
The case where 0% is the trench 31, that is, the case where the width of Rc = the depth of Rsw = the width of Rt will be described below.

From the correlation between the drift (accumulation) region length and the on-resistance and the results of the experiments shown in FIGS. 9, 10, and 15, the relationship between Rc, Rsw, and Rt can be expressed by the following equation.

Rc ≦ Rsw ≦ Rt 2Rt = k × 2Rc Here, k is a coefficient of the ON resistance of the trench 31.

The solid line in FIG. 16 shows the case where Rsw and Rc are the same. The dashed line indicates the case where Rsw and Rt are the same. Rc ≦ R
From the relationship sw ≦ Rt, the on-resistance (Ro
The range of possible coefficients for n) is indicated by the shaded area. k = 1
In other words, when Rc = Rsw = Rt, assuming that the on-resistance of the conventional LDMOS 50 is 1, the on-resistance (Ron) of the LDMOS 100
Can be reduced to 50%. When k = 2, that is, when Rt has twice the on-resistance of Rc, the conventional
The total on-resistance of about 40% to 20% of the total on-resistance of the LDMOS can be reduced. Thus, the shaded region where the index of the total on-resistance in FIG. 16 is 1 (the on-resistance of the LDMOS 50 according to the related art) or less is the region where the on-resistance (Ron) of the LDMOS 100 of the present invention is reduced. By determining the shape and arrangement of the trench 31 of the LDMOS 100 so that the coefficient k of the on-resistance of the trench 31 falls within this region, the channel width and the drift (accumulation) region width can be effectively increased, and the on-resistance is reduced. It became clear that it could be made smaller. In other words, when a trench is provided on the entire surface of the gate, only the drift length increases,
As a result, the on-resistance increases, but by providing the trenches 31 in a ladder shape at predetermined intervals, the channel width and the drift (accumulation) region width can be effectively increased even if the channel length and the drift length increase. Therefore, the on-resistance can be reduced. Therefore,
The arrangement and shape of the trench 31 can be freely formed as long as the index of the total on-resistance in FIG.

[0039]

The present invention has the following effects.

According to the present invention, even if the gate arrangement in the plan view of the LDMOS portion is the same, the channel width and the drift (accumulation) region width can be increased, so that the on-resistance per unit area is reduced. be able to.

According to the present invention, the trench density is doubled at the maximum by providing the trenches 31 in a ladder shape at predetermined intervals on the main surface of the LDMOS 100 at predetermined intervals so that the bottom and side surfaces of the trenches are also channels. Can be As a result, the on-resistance per unit area can be reduced to a maximum of about 1/2.

In addition, the present invention can use all the conventional techniques for reducing the on-resistance.

Further, as the on-resistance decreases,
The chip cost can be reduced by reducing the area of the LDMOS section of the intelligent power IC and the corresponding reduction in element size.

Further, as the on-resistance decreases,
Output loss can be reduced.

The LDMOS of intelligent power IC
When the area of the portion is reduced, the resistance of the metal wiring portion is also reduced, so that there is a synergistic effect that the overall on-resistance can be further reduced.

Although the structure of the invention has been described herein with reference to specific embodiments, those skilled in the art will be able to modify and modify the structure of the invention. However, the structure of the present invention is not limited to the specific embodiments disclosed herein. For example, although the embodiment has been described by taking the LDMOS as an example, the present invention can be applied to other semiconductor devices requiring low on-resistance, and the device of the present invention is not limited to the LDMOS. Further, in the embodiment, the case of the structure in which the gate and the drain overlap is described as an example, but the present invention is also effective in a structure in which the gate and the drain are offset. That is, in the drift region where no gate is present, the resistance does not increase because the accumulation does not occur. This is because it is also possible to reduce the on-resistance. Further, it is not intended to specify the breakdown voltage of the element, the shape of the trench, the width, the depth, the ratio, and the like. Such modifications and changes are also within the scope of the technical idea of the present invention, and are included in the scope of the claims.

[Brief description of the drawings]

FIG. 1 is a plan view of a conventional LDMOSFET 50. FIG.

FIG. 2 is a cross-sectional view taken along line X-X in FIG.

FIG. 3 is a cross-sectional view of an LDMOS 100 according to one embodiment of the present application.

FIG. 4 is a plan view of a gate electrode 32 of the LDMOS 100 according to one embodiment of the present application.

FIG. 5 is a sectional view taken along line D-D in FIG. 4;

FIG. 6 is a sectional view taken along the line AA in FIG. 4;

FIG. 7 is a sectional view taken along the line BB of FIG. 4;

FIG. 8 is a sectional view taken along the line CC of FIG. 4;

FIG. 9 is a graph showing an operation of the LDMOS 50 according to the related art.

FIG. 10 is a graph showing the operation of the LDMOS 100 according to one embodiment of the present application.

FIG. 11 is a sectional view of an LDMOS 50 according to the related art.

FIG. 12 is a sectional view of an LDMOS 100 according to an embodiment of the present application.

FIG. 13 is an LDMOS 100 according to an embodiment of the present application, in which only the width of the trench 31 is reduced.
0 is a sectional view.

FIG. 14 is an LDMOS 100 according to an embodiment of the present application, in which only the depth of the trench 31 is reduced.
It is sectional drawing of 00.

FIG. 15 is a graph showing the on-resistance of each LDMOS of FIGS. 11 to 14;

FIG. 16 is a graph showing the effect of the on-resistance of the LDMOS 100 according to one embodiment of the present application.

[Explanation of symbols]

 31 Trench 22, 32 Gate electrode 23, 33 Channel 25, 35 Drift (accumulation) region 26, 36p-type diffusion layer 50, 100 Lateral double-diffusion MOSFET

Claims (8)

[Claims] 1. A semiconductor device (100) comprising: a substrate having a main surface (34); a gate electrode (3) provided in a depression (31) formed in a predetermined region of the main surface (34).
2) a source electrode; a drain electrode; a base (36); and the gate electrode (32) of the base (36).
A semiconductor device, comprising: a channel formed in the vicinity. 2. A drift region (3) formed in contact with the channel (33) in the vicinity of the gate electrode (32).
2. The semiconductor device according to claim 1, further comprising: (5). 3. A semiconductor device (100) having a channel (33) formed three-dimensionally and three-dimensionally. 4. A semiconductor device (100) having a gate electrode provided in a depression (31) formed in a predetermined region of a main surface (34) of the semiconductor device (100). Semiconductor device. 5. The semiconductor device according to claim 1, wherein said gate electrode is provided on said main surface.
5. The semiconductor device according to claim 1, wherein said semiconductor device is provided in a plurality of recesses formed at predetermined intervals in said predetermined region. 6. The semiconductor device according to claim 1, wherein said semiconductor device is a lateral double diffusion MOSFET. 7. A gate electrode (3) of a semiconductor device (100).
2) wherein the gate electrode (32) is provided in a depression (31) formed in a predetermined region of the main surface (34) of the semiconductor device (100). 8. A method of manufacturing a semiconductor device (100), comprising: providing a substrate having a main surface (34); forming a depression (31) in a predetermined region on the main surface (34) of the substrate. Providing a gate electrode (32) in the depression (31); providing a base (36) on the substrate; and providing a channel (33) in the base (36) near the gate electrode (32). A method for manufacturing a semiconductor device (100).