CN203800036U - Source and drain leakage current testing structure - Google Patents
Source and drain leakage current testing structure Download PDFInfo
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- CN203800036U CN203800036U CN201420147276.8U CN201420147276U CN203800036U CN 203800036 U CN203800036 U CN 203800036U CN 201420147276 U CN201420147276 U CN 201420147276U CN 203800036 U CN203800036 U CN 203800036U
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- source
- doped region
- leakage current
- drain electrode
- test structure
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Abstract
The utility model relates to a source and drain leakage current testing structure which comprises multiple isolation grooves formed in a semiconductor substrate, filling layers formed in the isolation grooves, first doped regions between the isolation grooves, and a second doped region, wherein the filling layers are of bending structures. Corners of the bending structures tend to cause dislocation; when dislocation occurs, the drain and source leakage current of the substrate and an active region can be tested; and further the testing structure can determine whether electric leakage occurs in the source and drain electrodes of a device area as well as the severity of electric leakage.
Description
Technical field
The utility model relates to integrated circuit and manufactures field, particularly a kind of source-drain electrode leakage current test structure.
Background technology
In wafer manufacture process, because the physical damage in crystal lattice stress variation and manufacture process in crystal growth condition, crystal all may produce dislocation.
The dislocation of active area (Active Area, AA) silicon crystal is common problem during integrated circuit is manufactured.Specifically, in wafer production process, in Semiconductor substrate, etching forms isolated groove, because manufacturing process is limit, often cause the corner of isolated groove sufficiently oily, therefore in the time that forming packed layer, grow oxide in isolated groove can not form a good pattern follow-up, cause isolated groove corner easily to occur dislocation, , defect usually occurs in the place having a common boundary near silicon-silica (Si-SiO2), if isolated groove is near the corner of active area, these defects can Adsorption of Heavy Metals impurity, these impurity will play complex centre, cause the excessive electric leakage in device.In practice, find, just because of a large amount of lattice dislocations at active area marginal existence, produced the path of electric leakage, finally caused the increase of static father drain leakage, cause the appearance of defective products.
In order to pick out defective products, in semicon industry, carrying out wafer can acceptance test (wafer acceptance test, WAT), described wafer can acceptance test be on processing procedure in test wafer device whether have a test of normal ability to work.Its measuring object is single device, as single NMOS or PMOS etc., instead of the logical circuit having combined.Conventionally, WAT is after device has all been manufactured, and prepares before wafer cutting and encapsulation, to carry out.The device that WAT tests not is the device on wafer, but test structure (Test structure or test key) above Cutting Road, so both can effectively utilize the space of Cutting Road, can, via the test structure above the each Cutting Road of test, go to infer whether the device near chip (chip) electrically meets the requirements again.
But, the test parameter of existing WAT refers to, these test structures are carried out to the electrical parameter data that electrical property measurement obtains, and such as connectivity test, threshold voltage, drain saturation current etc., do not have effective test structure and detect active area dislocation and the order of severity thereof.Therefore, need badly a kind of test structure that can detect source-drain electrode leakage current is provided.
Summary of the invention
The purpose of this utility model provides a kind of source-drain electrode leakage current test structure, is used for the order of severity whether test component source-drain electrode leak electricity and leak electricity.
In order to solve the problems of the technologies described above, the utility model provides a kind of source-drain electrode leakage current test structure, comprise: be formed at some isolated grooves in semi-conductive substrate, be formed at packed layer in described isolated groove, be formed at the first doped region and the second doped region between described isolated groove, described packed layer is bending structure.
The packed layer of optionally, described source-drain electrode leakage current test structure is bar shaped bending structure.
Optionally, the bending angle of described bar shaped bending structure is 30～100 degree.
Optionally, the bending angle of described bar shaped bending structure is 70～90 degree.
Optionally, adjacent packed layer mirror image symmetry.Optionally, source-drain electrode leakage current test structure also comprises the well region being formed in described Semiconductor substrate, and described the first doped region and the second doped region are formed in described well region.
Optionally, described the first WeiNXing heavily doped region, doped region, described the second doped region is P type heavily doped region.
Optionally, source-drain electrode leakage current test structure also comprises and is formed at the insulating medium layer in described Semiconductor substrate and is formed at the first connector and the second connector in described insulating medium layer, described the first connector is connected with described the first doped region, and described the second connector is connected with described the second doped region.
Optionally, described the first doped region and the second doped region are electrically connected with an additional test circuit.
Optionally, described source-drain electrode leakage current test structure is positioned on the Cutting Road of Semiconductor substrate.
Compared with prior art, the utility model provides a kind of source-drain electrode leakage current test structure, can acceptance test for wafer, described source-drain electrode leakage current test structure comprises the some isolated grooves that are formed in Semiconductor substrate, be formed at the packed layer in described isolated groove, be formed at the first doped region between described isolated groove, and second doped region, described packed layer is bending structure, the corner of bending structure the most easily produces dislocation, in the time producing dislocation, just can measure the source-drain electrode leakage current of active area and substrate, and then the order of severity of whether leaking electricity and leaking electricity by described test structure test component source-drain electrode.
Brief description of the drawings
Fig. 1 is the source-drain electrode leakage current test structure schematic top plan view of the utility model one embodiment;
Fig. 2 is the schematic cross-section of Fig. 1 along AA ' direction.
Embodiment
Below in conjunction with schematic diagram, the utility model is described in more detail, wherein represent preferred embodiment of the present utility model, should be appreciated that those skilled in the art can revise the utility model described here, and still realize advantageous effects of the present utility model.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as to restriction of the present utility model.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
Fig. 1 is the source-drain electrode leakage current test structure schematic top plan view of the utility model one embodiment, and Fig. 2 is the schematic cross-section of Fig. 1 along AA ' direction.As depicted in figs. 1 and 2, the source-drain electrode leakage current test structure that the utility model provides, comprise: be formed at some isolated grooves 20 in semi-conductive substrate 10, be formed at packed layer 25 in described isolated groove 20, be formed at the first doped region 60 and the second doped region 70 between described isolated groove 20, described packed layer 25 is bending structure.The corner 40 of described bending structure 25, due to sufficiently oily, the most easily produces dislocation, in the time there is dislocation, just can measure the source-drain electrode leakage current of active area and substrate 10.
As shown in Figure 1, packed layer 25 is bent to form by bar shaped, adjacent packed layer mirror image symmetry.Wherein, bending angle is 30～100 degree, and in preferred version, bending angle is selected 70～90 degree.Certainly, the utility model does not limit concrete shape and the quantity of isolated groove, as long as bending structure all can be realized the purpose of this utility model.
Described source-drain electrode leakage current test structure also comprises the well region 50 being formed in described Semiconductor substrate 10, and described the first doped region 60 and the second doped region 70 are formed in described well region 50.
Wherein, described the first 60WeiNXing heavily doped region, doped region, described the second doped region 70 is the heavy doping of P type, vice versa.
Described source-drain electrode leakage current test structure also comprises and is formed at the insulating medium layer 80 in described Semiconductor substrate 10 and is formed at the first connector 90 and the second connector 95 in described insulating medium layer 80, described the first connector 90 is connected with described the first doped region 60, and described the second connector 95 is connected with described the second doped region 70.When test, by described the first connector 90 and the second connector 95, described the first doped region 60 and the second doped region 70 are electrically connected with an additional test circuit.
Wherein, described source-drain electrode leakage current test structure is positioned on the Cutting Road of Semiconductor substrate 10, can with wafer device region on device together form.
Specifically, the source-drain electrode leakage current test structure that the utility model provides can form in the following way: first, in Semiconductor substrate, form the first shallow trench isolation groove 20 and the second shallow trench isolation groove 30, and be packed layer 25 and 35 at the first shallow trench isolation groove 20 and the interior fill oxide of the second shallow trench isolation groove 30; The first shallow trench isolation groove 20 and the second shallow trench isolation groove 30 bending structure of mirror image symmetry each other.Then carry out light dope and form well region 50, then carry out heavy doping and form the first doped region 60 and the second doped region 70, described the first doped region 60 is for example N-type heavily doped region, and described the second doped region 70 is for example P type heavily doped region.Then, on substrate, deposition forms insulating medium layer 80, and described in etching, insulating medium layer 80 forms contact hole (contact hole), then in contact hole, fill metal and form metal plug (plug), be connected in first connector 90 and the second connector 95 that is connected in the second doped region 70 of the first doped region 60; Finally, carry out metal interconnection wire manufacture craft, metal plug is connected with metal interconnecting wires electricity.
When carrying out wafer can acceptance test time, by described the first connector 90 and the second connector 95, described the first doped region 60 and the second doped region 70 are electrically connected with an additional test circuit, PN junction conducting, P type heavily doped region one terminal voltage is 0 volt.Bending structure corner 40 the most easily produces dislocation, if test structure does not produce dislocation situation, dislocation can not occur the device in its annex chip (chip) substantially, and leaky just can not occur yet.If record the source-drain electrode leakage current of active area and substrate, illustrate that active area dislocation is serious.If dislocation occurs for test structure and chip device simultaneously, the result of leaking electricity can worsen, and test result can be very obvious.If do not leak electricity generation, product is non-defective unit, if there is electric leakage to produce, is defective products.
In sum, the utility model provides a kind of source-drain electrode leakage current test structure, can be used for wafer can acceptance test in the test component source-drain electrode order of severity of whether leaking electricity and leaking electricity, described source-drain electrode leakage current test structure comprises the some isolated grooves that are formed in Semiconductor substrate, be formed at the packed layer in described isolated groove, be formed at the first doped region between described isolated groove, and second doped region, described packed layer is bending structure, the corner of bending structure the most easily produces dislocation, in the time producing dislocation, just can measure the source-drain electrode leakage current of active area and substrate, and then the order of severity of whether leaking electricity and leaking electricity by described test structure test component source-drain electrode.
Obviously, foregoing description is only the description to the utility model preferred embodiment, and those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model the utility model.Like this, if these amendments of the present utility model and within modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (10)
1. a source-drain electrode leakage current test structure, it is characterized in that, comprise: be formed at some isolated grooves in semi-conductive substrate, be formed at packed layer in described isolated groove, be formed at the first doped region and the second doped region between described isolated groove, wherein said packed layer is bending structure.
2. source-drain electrode leakage current test structure as claimed in claim 1, is characterized in that, described packed layer is bar shaped bending structure.
3. source-drain electrode leakage current test structure as claimed in claim 2, is characterized in that, the bending angle of described bar shaped bending structure is 30～100 degree.
4. source-drain electrode leakage current test structure as claimed in claim 3, is characterized in that, the bending angle of described bar shaped bending structure is 70～90 degree.
5. source-drain electrode leakage current test structure as claimed in claim 2, is characterized in that, adjacent packed layer mirror image symmetry.
6. source-drain electrode leakage current test structure as claimed in claim 1, is characterized in that, also comprises the well region being formed in described Semiconductor substrate, and described the first doped region and the second doped region are formed in described well region.
7. source-drain electrode leakage current test structure as claimed in claim 6, is characterized in that, described the first WeiNXing heavily doped region, doped region, and described the second doped region is P type heavily doped region.
8. source-drain electrode leakage current test structure as claimed in claim 1, it is characterized in that, also comprise and be formed at the insulating medium layer in described Semiconductor substrate and be formed at the first connector and the second connector in described insulating medium layer, described the first connector is connected with described the first doped region, and described the second connector is connected with described the second doped region.
9. source-drain electrode leakage current test structure as claimed in claim 1, is characterized in that, described the first doped region and the second doped region are electrically connected with an additional test circuit.
10. source-drain electrode leakage current test structure as claimed in claim 1, is characterized in that, described source-drain electrode leakage current test structure is positioned on the Cutting Road of Semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420147276.8U CN203800036U (en) | 2014-03-28 | 2014-03-28 | Source and drain leakage current testing structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420147276.8U CN203800036U (en) | 2014-03-28 | 2014-03-28 | Source and drain leakage current testing structure |
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| CN203800036U true CN203800036U (en) | 2014-08-27 |
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| CN201420147276.8U Expired - Fee Related CN203800036U (en) | 2014-03-28 | 2014-03-28 | Source and drain leakage current testing structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112768366A (en) * | 2021-01-22 | 2021-05-07 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
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2014
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112768366A (en) * | 2021-01-22 | 2021-05-07 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
| CN112768366B (en) * | 2021-01-22 | 2024-02-23 | 长江存储科技有限责任公司 | Semiconductor structure and preparation method thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140827 Termination date: 20190328 |