CN103822948B - The testing method of semiconducter device - Google Patents
The testing method of semiconducter device Download PDFInfo
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- CN103822948B CN103822948B CN201410081201.9A CN201410081201A CN103822948B CN 103822948 B CN103822948 B CN 103822948B CN 201410081201 A CN201410081201 A CN 201410081201A CN 103822948 B CN103822948 B CN 103822948B
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Abstract
A testing method for semiconducter device, comprising: providing semiconducter device, described semiconducter device comprises: semiconducter substrate; The metal pattern being positioned in described semiconducter substrate, described metal pattern comprises the first electrode and the 2nd electrode; Dielectric layer between described first electrode and described 2nd electrode in described semiconducter substrate; There is provided the electric capacity standard value between described first electrode and described 2nd electrode, and the electric capacity detected between described first electrode and described 2nd electrode is truly worth; When described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, judge that described dielectric layer exists clearance. The present invention can with low cost, high-level efficiency, without destructive the accurate detection that all semiconducter device are carried out dielectric layer air gap.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the testing method of a kind of semiconducter device.
Background technology
Along with the sustainable development of semiconductor fabrication so that semiconducter device has trickleer pattern and higher integrated level (integration). Between various patterns in semiconducter device, usually use metal interconnect structure (comprising metal plug and metal interconnecting wires) to provide the electrical contact between circuit assembly or interior articulamentum.
Forming method for aluminium connector is described below.
Shown in figure 1, it is provided that semiconducter substrate 10, and form aluminum metal layer 20 in described semiconducter substrate 10.
Shown in figure 2, described aluminum metal layer 20 is etched, form multiple aluminium connector 30, between adjacent aluminium connector 30, there is through hole 40.
Shown in figure 3, forming dielectric layer 50 between the aluminium connector 30 in described semiconducter substrate 10, dielectric layer 50 can fill up the described through hole 40 in Fig. 2.
But, shown in figure 4, along with the dark width of through hole 40 between aluminium connector 30 in Fig. 2 is than increasing, when forming dielectric layer 50 in through hole 40, it is easy in dielectric layer 50 and forms clearance 60, thus dielectric layer 50 cannot fill up through hole 40.
For filling (gapfill) situation of the different dielectric layer 50 of two shown in Fig. 3 and Fig. 4 kind, it is necessary to whether dielectric layer 50 exists clearance 60 detect.
Prior art is all adopt FA(failureanalysis, failure analysis) physical method detect the filling situation of above-mentioned dielectric layer 50, specifically: after the semiconducter device on silicon chip completes, silicon chip is cut open, then SEM(sweep electron microscope is adopted) observe, thus range estimation determines whether to exist in dielectric layer 50 clearance 60.
But there is following shortcoming in above-mentioned FA method: testing cost height, and detection efficiency is low; Only the silicon chip of a seldom part can be detected, thus sampling Detection rate is low, causes whole detection accuracy rate low; Product qualified after testing is owing to being destroyed, thus cannot use, and further increases cost.
Therefore, how to detect simply and effectively and whether the dielectric layer between metal pattern exists clearance just become one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide the testing method of a kind of semiconducter device, it is possible to low cost, high-level efficiency, without destructive the accurate detection that all semiconducter device are carried out dielectric layer air gap.
For solving the problem, the present invention provides the testing method of a kind of semiconducter device, comprising:
Thering is provided semiconducter device, described semiconducter device comprises: semiconducter substrate; The metal pattern being positioned in described semiconducter substrate, described metal pattern comprises the first electrode and the 2nd electrode; Dielectric layer between described first electrode and described 2nd electrode in described semiconducter substrate;
There is provided the electric capacity standard value between described first electrode and described 2nd electrode, and the electric capacity detected between described first electrode and described 2nd electrode is truly worth;
When described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, judge that described dielectric layer exists clearance.
Optionally, the material of described metal pattern comprises aluminium or tungsten.
Optionally, the material of described dielectric layer is low-k materials or super low-k materials.
Optionally, described metal pattern is pectination capacitance structure.
Optionally, the testing method of described semiconducter device also comprises: described semiconducter device carries out wafer and permits Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, and test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure.
Optionally, described dielectric layer adopts high density plasma CVD method to be formed.
Optionally, described threshold value is more than or equal to 10%.
Optionally, described electric capacity standard value is obtained by the mode calculated.
Optionally, described electric capacity standard value is obtained by the mode measured.
Optionally, after judging to there is clearance in described dielectric layer, the testing method of described semiconducter device also comprises: adopt the method for failure analysis to be detected by described semiconducter device.
Compared with prior art, the technical scheme of the present invention has the following advantages:
In the testing method of semiconducter device provided by the invention, whether clearance is there is in order between the dielectric layer tested between metal pattern, the metal pattern comprising the first electrode and the 2nd electrode can be formed on a semiconductor substrate, when the factor such as material and size of dielectric layer is determined and be there is not clearance in dielectric layer, the electric capacity standard value between described first electrode and described 2nd electrode can be obtained, and when dielectric layer exists clearance, electric capacity between described first electrode and described 2nd electrode is truly worth and will inevitably change, and clearance is more big, capacitance variations is more big, thus when described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, just can learn in described dielectric layer to there is clearance.The testing method testing cost of above-mentioned electricity is lower, but detection efficiency is very high; All semiconducter device can be detected, thus improve the accuracy rate of whole detection; Without the need to destroying semiconducter device, thus do not affect the follow-up normal use of semiconducter device, reduce further testing cost.
Further, described metal pattern is pectination capacitance structure, such that it is able to increase the area of metal pattern, increase the capacitance between the first electrode and the 2nd electrode, make the difference that electric capacity is truly worth between electric capacity theoretical value more obvious, reduce the difficulty of detection, it is to increase the accuracy judged.
Further, the testing method of described semiconducter device also comprises: described semiconducter device carries out wafer and permits Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure, thus achieve the multiplexing of test structure, without the need to changing the existing test structure of semiconducter device, method is simple, and cost is low.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the schematic diagram of the forming method of aluminium connector;
Fig. 5 is the schematic flow sheet of the testing method of the semiconducter device that the embodiment of the present invention provides;
Fig. 6 is the structural representation of metal pattern in Fig. 5.
Embodiment
As described in background, prior art adopting, whether the physical method of FA exists clearance in the dielectric layer testing between metal pattern. But the testing cost of this kind of detection mode is higher, detection efficiency is lower; Only being detected by the silicon chip of a seldom part, therefore sampling Detection rate is low, reduces whole detection accuracy rate; Qualified product are caused irrecoverable destructiveness, further increases testing cost.
For the problems referred to above, the present invention provides in the testing method of a kind of semiconducter device, formed on a semiconductor substrate and comprise the first electrode and the metal pattern of the 2nd electrode, whether clearance is there is in order between the dielectric layer tested between the first electrode and the 2nd electrode, electric capacity standard value between first electrode and the 2nd electrode is provided, and the electric capacity detected between the first electrode and the 2nd electrode is truly worth, when described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, then judge to draw in described dielectric layer to there is clearance. the testing method testing cost of this kind of electricity is lower, but detection efficiency is very high, all semiconducter device can be detected, thus improve the accuracy rate of whole detection, without the need to destroying semiconducter device, thus do not affect the follow-up normal use of semiconducter device, reduce further testing cost.
For enabling above-mentioned purpose, the feature and advantage of the present invention more become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Shown in figure 5, present embodiments provide the testing method of a kind of semiconducter device, comprise the following steps:
Step S1, it is provided that semiconducter substrate, and form metal level on the semiconductor substrate;
Step S2, etches described metal level, is formed and comprises the first electrode and the metal pattern of the 2nd electrode;
Step S3, the described semiconducter substrate between described first electrode and described 2nd electrode forms dielectric layer;
Step S4, it is provided that the electric capacity standard value between described first electrode and described 2nd electrode;
Step S5, the electric capacity detected between described first electrode and described 2nd electrode is truly worth;
Step S6, compares described electric capacity and is truly worth and whether ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, when described ratio is greater than described threshold value, perform step S7; When described ratio is less than described threshold value, perform step S8;
Step S7, judges to draw in described dielectric layer to there is clearance;
Step S8, judges to draw there is not clearance in described dielectric layer.
The present embodiment judges whether there is clearance in dielectric layer by measuring the electrical method of electric capacity, and Comparison between detecting methods is simple, and testing cost is very low, and detection efficiency is very high; And all semiconducter device can be detected, instead of only its small portion is inspected by random samples, it is to increase the accuracy rate of the whole detection of semiconducter device; And without the need to destroying semiconducter device in whole testing process, thus do not affect the follow-up normal use of semiconducter device, finally reduce testing cost further.
First, it is provided that semiconducter substrate.
The material of described semiconducter substrate can be silicon single crystal, monocrystalline germanium, germanium silicon or silicon carbide, it is possible to thinks silicon-on-insulator or germanium on insulator, it is also possible to is the III-V such as gallium arsenide.
In the present embodiment, described semiconducter substrate can be formed with the electronic components such as MOS pipe, diode, electric capacity, inductance.
Then, metal level is formed on the semiconductor substrate.
The material of described metal level can be aluminium or tungsten, and it is for the formation of interconnecting construction.
Metal level described in the present embodiment is aluminium layer, and it can adopt but be not limited to sputtering technology and formed.
It should be noted that, in other embodiments of the invention, before forming described metal level, it is also possible to first forming blocking layer (as: silicon nitride) on the semiconductor substrate, it does not affect protection scope of the present invention.
Then, adopt dry etch process to etch described metal level, make remaining described metal level form metal pattern.
Shown in figure 6, metal pattern described in the present embodiment can be pectination capacitance structure, comprises the first electrode 100 and the 2nd electrode 200.
It should be noted that, in other embodiments of the invention, described metal pattern can also be other arbitrary capacitance structure, as only comprised two parallel metal line as the first electrode and the 2nd electrode.
It should be noted that, when metal pattern adopts different capacitance structure, relative area or distance between described first electrode and described 2nd electrode can be different.
Due to the restriction of processing condition, minor deviations may be there is between the size of described metal pattern and physical size, thus the actual relative area between described first electrode and described 2nd electrode may be different from design relative area, the actual range between described first electrode and described 2nd electrode also may be different from designed distance.
Then, the dielectric layer covering described metal pattern is formed on the semiconductor substrate.
Described dielectric layer can be single layer structure, it is also possible to be rhythmo structure, and it is for isolating described first electrode and described 2nd electrode.
The material of described dielectric layer can be low-k materials or super low-k materials, as: one or more in carbon doping dielectric material, carbon-doped organic glass, carbon doped silicon dioxide, fluorine silex glass (FSG), silicon oxide carbide, it is also possible to be the common dielectric materials such as silicon oxide.
Described dielectric layer can be formed by the method such as chemical gaseous phase depositing process or growth method.
It should be noted that, when described dielectric layer adopts differing materials, the specific inductivity of described dielectric layer is different.
Dielectric layer described in the present embodiment can be the fluorine silex glass material of individual layer, and it passes through HDPCVD(HighDensityPlasmaChemicalVaporDeposition, high density plasma CVD method) formed.
Follow-up described dielectric layer planarization be can also be carried out, the upper surface of described dielectric layer and the upper surface flush of described metal pattern made.
In addition, after follow-up semiconducter device completes, in addition it is also necessary to semiconducter device carries out wafer and permits Acceptance Tests (WaferAcceptanceTest, WAT), described WAT comprises insulativity test between metal wire, namely tests whether there is short circuit phenomenon between metal wire. The test of described metal line piece insulativity can also form the metal pattern shown in Fig. 6 as test structure in the semiconducter substrate of semiconducter device, and forming the dielectric layer covering described metal pattern on a semiconductor substrate, test structure and described metal pattern that namely between described metal wire, insulativity test adopts can be same structure. Therefore, thus achieve the multiplexing of test structure, it is not necessary to changing the existing structure of semiconducter device, method is simple, and cost is low.
When adopting the metal pattern shown in Fig. 6 to carry out insulativity test between metal wire, it is necessary to testing the electric current between the first electrode 100 and the 2nd electrode 200, it is known for those skilled in the art, does not repeat them here; When adopting the metal pattern shown in Fig. 6 to carry out dielectric layer air clearance test, it is necessary to test the electric capacity between the first electrode 100 and the 2nd electrode 200, can describe in detail below.
Owing to dielectric layer is formed between the first electrode and the 2nd electrode, the size of the through hole formed between the first electrode and the 2nd electrode is very little, is therefore easy in dielectric layer produce clearance. When there is not clearance in dielectric layer or clearance is very little, the present embodiment can think that the dielectric layer in semiconducter device is up-to-standard; Then think that the dielectric layer in semiconducter device is off quality when the dimension ratio in dielectric layer air gap is bigger, thus this semiconducter device is defective.
Then, it is provided that the electric capacity standard value between described first electrode and described 2nd electrode.
Capacitance between first electrode and described 2nd electrode described in when described electric capacity standard value refers to not exist in dielectric layer clearance or clearance is negligible, capacitance between the first electrode and the 2nd electrode when namely the dielectric layer in semiconducter device is up-to-standard.
In one example in which, described electric capacity standard value can be obtained by the mode calculated, and specifically can be calculated by formula below:
Wherein, C represents the electric capacity between the first electrode and the 2nd electrode, and �� represents the dielectric constant of dielectric layer, and S represents the first electrode and the relative area of the 2nd electrode, and k represents electrostatic force constant, and d is the distance between the first electrode and the 2nd electrode.
In another example, described electric capacity standard value can be obtained by the mode measured, specifically can by capacitance between the first electrode and the 2nd electrode in the test up-to-standard semiconducter device of dielectric layer as described electric capacity standard value.
Further, it is also possible to test the capacitance between the first electrode and the 2nd electrode in the up-to-standard multiple semiconducter device of dielectric layer, and using the mean value of multiple capacitance as described electric capacity standard value, thus improve test accuracy rate further.
Then, the electric capacity detected between described first electrode and described 2nd electrode is truly worth.
Described electric capacity is truly worth the capacitance referring to be measured between described first electrode of acquisition and described 2nd electrode by reality, and its concrete measuring method is known for those skilled in the art, does not repeat them here.
It should be noted that, it is possible to adjusting described electric capacity and be truly worth the order of the acquisition with described electric capacity standard value, it does not limit the scope of the invention.
Then, compare described electric capacity to be truly worth and whether ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value.
When there is clearance in described dielectric layer, the electric capacity between described first electrode and described 2nd electrode is truly worth and will inevitably change, and clearance is more big, and capacitance variations is more big.
The present embodiment considers there is minor deviations between the size of metal pattern and physical size, and can also think that the dielectric layer in semiconducter device is up-to-standard when the clearance existed in dielectric layer is very little, as long as therefore described electric capacity is truly worth and when ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is less than threshold value, so that it may to think there is not clearance in described dielectric layer; When described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, there is clearance in described dielectric layer.
It should be noted that, when described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value equals threshold value, both can judge to draw in described dielectric layer to there is clearance, it is also possible to judge to draw that described dielectric layer does not exist clearance.
Threshold value described in the present embodiment can be more than or equal to 10%, as: 10%, 12%, 15%, 18% or 20% etc.
It should be noted that, in other embodiments of the invention, described threshold value can select other value, and it does not limit the scope of the invention.
Further, after adopting above-mentioned electrical method to judge that described dielectric layer exists clearance, the present embodiment can also adopt the method for failure analysis to be detected further by described semiconducter device, thus verify the accuracy of described electrical method, and according to verifying the value of threshold value described in result optimizing, the accuracy of detection finally can be improved further.
Owing to metal pattern in the present embodiment is pectination capacitance structure, such that it is able to increase the area of metal pattern, increase the capacitance between the first electrode and the 2nd electrode, the difference making electric capacity truly be worth between electric capacity theoretical value is more obvious, reduce the difficulty of detection, it is to increase the accuracy judged.
The test structure and the described metal pattern that adopt due to insulativity test between described metal wire are same structure, thus achieve the multiplexing of test structure, it is not necessary to changing the existing test structure of semiconducter device, method is simple, and cost is low.
Although present disclosure is as above, but the present invention is not defined in this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. the testing method of a semiconducter device, it is characterised in that, comprising:
Thering is provided semiconducter device, described semiconducter device comprises: semiconducter substrate; The metal pattern being positioned in described semiconducter substrate, described metal pattern comprises the first electrode and the 2nd electrode; Dielectric layer between described first electrode and described 2nd electrode in described semiconducter substrate;
There is provided the electric capacity standard value between described first electrode and described 2nd electrode, and the electric capacity detected between described first electrode and described 2nd electrode is truly worth;
When described electric capacity is truly worth and ratio between the absolute value of difference of described electric capacity standard value and described electric capacity standard value is greater than threshold value, judge that described dielectric layer exists clearance;
Described metal pattern is pectination capacitance structure;
Described semiconducter device carrying out wafer and permits Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, and test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure.
2. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, the material of described metal pattern comprises aluminium or tungsten.
3. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, the material of described dielectric layer is low-k materials or super low-k materials.
4. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, described dielectric layer adopts high density plasma CVD method to be formed.
5. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, described threshold value is more than or equal to 10%.
6. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, described electric capacity standard value is obtained by the mode calculated.
7. the testing method of semiconducter device as claimed in claim 1, it is characterised in that, described electric capacity standard value is obtained by the mode measured.
8. the testing method of semiconducter device as claimed in claim 1, it is characterized in that, after judging to there is clearance in described dielectric layer, the testing method of described semiconducter device also comprises: adopt the method for failure analysis to be detected by described semiconducter device.
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| CN106595975B (en) * | 2016-10-28 | 2019-07-26 | 中国科学院微电子研究所 | Device and method for detecting air tightness of wafer-level sensor |
| CN107607595B (en) * | 2017-09-21 | 2020-05-12 | 京东方科技集团股份有限公司 | Optical filter detection device and method |
| CN110887877A (en) * | 2019-11-22 | 2020-03-17 | 中国人民解放军国防科技大学 | Railway contact line defect detection sensor and detection method |
| CN112103202B (en) * | 2020-11-10 | 2021-02-12 | 晶芯成(北京)科技有限公司 | Semiconductor test structure and quality test method of semiconductor passivation layer |
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