CN103822948A - Testing method for semiconductor - Google Patents
Testing method for semiconductor Download PDFInfo
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- CN103822948A CN103822948A CN201410081201.9A CN201410081201A CN103822948A CN 103822948 A CN103822948 A CN 103822948A CN 201410081201 A CN201410081201 A CN 201410081201A CN 103822948 A CN103822948 A CN 103822948A
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Abstract
A testing method for a semiconductor includes the following steps: providing a semiconductor, wherein the semiconductor includes a semiconductor substrate, a metal pattern designed on the semiconductor substrate and comprising a first electrode and a second electrode, and a dielectric layer positioned between the first electrode and the second electrode on the semiconductor substrate; providing a standard capacitance value between the first electrode and the second electrode, and testing an actual capacitance value between the first electrode and the second electrode; confirming that air gaps exist in the dielectric layer when a specific value between an absolute value of a difference value between the actual capacitance value and the standard capacitance value, and the standard capacitance value is larger than a threshold value. The testing method for the semiconductor can be used for accurately testing the air gaps in the dielectric layers of all the semiconductors with low cost, high efficiency and no damage.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of method of testing of semiconductor devices.
Background technology
Along with the sustainable development of semiconductor fabrication, make semiconductor devices there is trickleer pattern and higher integrated level (integration).Between various patterns in semiconductor devices, conventionally use metal interconnect structure (comprising metal plug and metal interconnecting wires) so that electrically contacting between circuit arrangement or interior articulamentum to be provided.
Describe as an example of the formation method of aluminium connector example below.
Shown in figure 1, Semiconductor substrate 10 is provided, and forms aluminum metal layer 20 in described Semiconductor substrate 10.
Shown in figure 2, described aluminum metal layer 20 is carried out to etching, form multiple aluminium connectors 30, between adjacent aluminium connector 30, there is through hole 40.
Shown in figure 3, between the aluminium connector 30 in described Semiconductor substrate 10, form dielectric layer 50, dielectric layer 50 can fill up the described through hole 40 in Fig. 2.
But, shown in figure 4, along with the depth-to-width ratio of the through hole 40 between aluminium connector 30 in Fig. 2 is increasing, form dielectric layer 50 in through hole 40 time, be easy in dielectric layer 50, form clearance 60, thereby dielectric layer 50 cannot fill up through hole 40.
For filling (gap fill) situation of the different dielectric layer 50 of two kinds shown in Fig. 3 and Fig. 4, need to whether existing clearance 60 to detect in dielectric layer 50.
In prior art, be all to adopt FA(failure analysis, failure analysis) physical method detect the filling situation of above-mentioned dielectric layer 50, particularly: after the semiconductor devices on silicon chip completes, silicon chip is cut open, then adopt SEM(sweep electron microscope) observe, thus range estimation determines in dielectric layer 50 whether have clearance 60.
But there is following shortcoming in above-mentioned FA method: testing cost is high, and detection efficiency is low; Only can detect the silicon chip of a little part, thereby sampling Detection rate is low, causes whole detection accuracy rate low; Qualified product is owing to going to pot after testing, thereby cannot use, and further improved cost.
Therefore, how to detect simply and effectively in the dielectric layer between metal pattern and whether exist clearance just to become one of those skilled in the art's problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of method of testing of semiconductor devices, can carry out devastatingly the accurate detection of clearance in dielectric layer to all semiconductor devices with low cost, high-level efficiency, nothing.
For addressing the above problem, the invention provides a kind of method of testing of semiconductor devices, comprising:
Semiconductor devices is provided, and described semiconductor devices comprises: Semiconductor substrate; Be positioned at the metal pattern in described Semiconductor substrate, described metal pattern comprises the first electrode and the second electrode; Dielectric layer between the above first electrode of described Semiconductor substrate and described the second electrode;
Capacity standard value between described the first electrode and described the second electrode is provided, and detects the electric capacity actual value between described the first electrode and described the second electrode;
In the time that the ratio between absolute value and the described capacity standard value of the difference of described electric capacity actual value and described capacity standard value is greater than threshold value, judges in described dielectric layer and have clearance.
Optionally, the material of described metal pattern comprises aluminium or tungsten.
Optionally, the material of described dielectric layer is low-k materials or super low-k materials.
Optionally, described metal pattern is comb capacitance structure.
Optionally, the method of testing of described semiconductor devices also comprises: described semiconductor devices is carried out to wafer and permit Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, and test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure.
Optionally, described dielectric layer employing high density plasma CVD method formation.
Optionally, described threshold value is more than or equal to 10%.
Optionally, described capacity standard value is obtained by the mode of calculating.
Optionally, described capacity standard value is obtained by the mode of measuring.
Optionally, after judging and having clearance in described dielectric layer, the method for testing of described semiconductor devices also comprises: adopt the method for failure analysis to detect described semiconductor devices.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the method for testing of semiconductor devices provided by the invention, in order to test whether there is clearance between the dielectric layer between metal pattern, can in Semiconductor substrate, form the metal pattern that comprises the first electrode and the second electrode, when the factor such as material and size of dielectric layer determine and dielectric layer in while there is not clearance, can obtain the capacity standard value between described the first electrode and described the second electrode, and in the time there is clearance in dielectric layer, electric capacity actual value between described the first electrode and described the second electrode will inevitably change, and clearance is larger, capacitance variations is larger, thereby in the time that the ratio between absolute value and the described capacity standard value of the difference of described electric capacity actual value and described capacity standard value is greater than threshold value, just can learn in described dielectric layer and have clearance.The method of testing testing cost of above-mentioned electricity is lower, but detection efficiency is very high; Can detect all semiconductor devices, thereby improve the accuracy rate of whole detection; Without destroying semiconductor devices, thereby do not affect the follow-up normal use of semiconductor devices, further reduced testing cost.
Further, described metal pattern is comb capacitance structure, thereby can increase the area of metal pattern, increase the capacitance between the first electrode and the second electrode, make the difference between electric capacity actual value and electric capacity theoretical value more obvious, reduced the difficulty detecting, improved the accuracy of judgement.
Further, the method of testing of described semiconductor devices also comprises: described semiconductor devices is carried out to wafer and permit Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure, thereby realize the multiplexing of test structure, without the existing test structure that changes semiconductor devices, method is simple, and cost is low.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the schematic diagram of the formation method of aluminium connector;
Fig. 5 is the schematic flow sheet of the method for testing of the semiconductor devices that provides of the embodiment of the present invention;
Fig. 6 is the structural representation of metal pattern in Fig. 5.
Embodiment
As described in background, the physical method of available technology adopting FA tests in the dielectric layer between metal pattern, whether there is clearance.But the testing cost of this kind of detection mode is higher, detection efficiency is lower; Only can detect the silicon chip of a little part, therefore sampling Detection rate is low, has reduced whole detection accuracy rate; Specification product are caused to expendable destructiveness, further improved testing cost.
For the problems referred to above, the invention provides in a kind of method of testing of semiconductor devices, in Semiconductor substrate, form the metal pattern that comprises the first electrode and the second electrode, in order to test between the dielectric layer between the first electrode and the second electrode whether have clearance, capacity standard value between the first electrode and the second electrode is provided, and detect the electric capacity actual value between the first electrode and the second electrode, in the time that the ratio between absolute value and the described capacity standard value of the difference of described electric capacity actual value and described capacity standard value is greater than threshold value, judgement draws in described dielectric layer and has clearance.The method of testing testing cost of this electricity is lower, but detection efficiency is very high; Can detect all semiconductor devices, thereby improve the accuracy rate of whole detection; Without destroying semiconductor devices, thereby do not affect the follow-up normal use of semiconductor devices, further reduced testing cost.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Shown in figure 5, the present embodiment provides a kind of method of testing of semiconductor devices, comprises the following steps:
Step S1, provides Semiconductor substrate, and forms metal level in described Semiconductor substrate;
Step S2, carries out etching to described metal level, forms the metal pattern that comprises the first electrode and the second electrode;
Step S3 forms dielectric layer in the described Semiconductor substrate between described the first electrode and described the second electrode;
Step S4, provides the capacity standard value between described the first electrode and described the second electrode;
Step S5, detects the electric capacity actual value between described the first electrode and described the second electrode;
Step S6, whether the ratio between the absolute value of the difference of more described electric capacity actual value and described capacity standard value and described capacity standard value is greater than threshold value, in the time that described ratio is greater than described threshold value, execution step S7; In the time that described ratio is less than described threshold value, execution step S8;
Step S7, judgement draws in described dielectric layer and has clearance;
Step S8, judgement draws and in described dielectric layer, does not have clearance.
The present embodiment judges in dielectric layer whether have clearance by the electrical method of measuring electric capacity, and detection method is fairly simple, and testing cost is very low, and detection efficiency is very high; And can detect all semiconductor devices, rather than only fraction is wherein inspected by random samples, improve the accuracy rate of the whole detection of semiconductor devices; And in whole testing process without destroying semiconductor devices, thereby do not affect the follow-up normal use of semiconductor devices, finally further lowered testing cost.
First, provide Semiconductor substrate.
The material of described Semiconductor substrate can be monocrystalline silicon, monocrystalline germanium, germanium silicon or silit, can be also silicon-on-insulator or germanium on insulator, can also be the III-V compounds of group such as gallium arsenide.
In the present embodiment, in described Semiconductor substrate, can be formed with the electronic components such as metal-oxide-semiconductor, diode, electric capacity, inductance.
Then, in described Semiconductor substrate, form metal level.
The material of described metal level can be aluminium or tungsten, and it is used to form interconnecting construction.
Metal level described in the present embodiment is aluminium lamination, and it can adopt but be not limited to sputtering technology and form.
It should be noted that, in other embodiments of the invention, before forming described metal level, can also first in described Semiconductor substrate, form restraining barrier (as: silicon nitride), it does not affect protection scope of the present invention.
Then, adopt metal level described in dry etch process etching, make remaining described metal level form metal pattern.
Shown in figure 6, metal pattern described in the present embodiment can be comb capacitance structure, comprises the first electrode 100 and the second electrode 200.
It should be noted that, in other embodiments of the invention, described metal pattern can also be other capacitance structure arbitrarily, and as only comprised, two parallel metal line are as the first electrode and the second electrode.
It should be noted that, in the time that metal pattern adopts different capacitance structures, the relative area between described the first electrode and described the second electrode or distance can be different.
Due to the restriction of process conditions, between the design size of described metal pattern and physical size, may there is minor deviations, thereby the actual relative area between described the first electrode and described the second electrode may be different from design relative area, the actual range between described the first electrode and described the second electrode also may be different from designed distance.
Then, in described Semiconductor substrate, form the dielectric layer that covers described metal pattern.
Described dielectric layer can be single layer structure, can be also rhythmo structure, and it is for isolating described the first electrode and described the second electrode.
The material of described dielectric layer can be low-k materials or super low-k materials, as: one or more in carbon doped dielectric material, carbon-doped organic glass, carbon doped silicon dioxide, fluorine silex glass (FSG), silicon oxide carbide can be also the common dielectric materials such as monox.
Described dielectric layer can form by methods such as chemical gaseous phase depositing process or growing methods.
It should be noted that, in the time that described dielectric layer adopts different materials, the specific inductive capacity difference of described dielectric layer.
Dielectric layer described in the present embodiment can be the fluorine silex glass material of individual layer, and it is by HDPCVD(High Density Plasma Chemical Vapor Deposition, high density plasma CVD method) form.
Follow-uply can also carry out planarization to described dielectric layer, make the upper surface flush of upper surface and the described metal pattern of described dielectric layer.
In addition, after follow-up semiconductor devices completes, also need that semiconductor devices is carried out to wafer and permit Acceptance Tests (Wafer Acceptance Test, WAT), described WAT comprises between metal wire insulativity test, tests between metal wire, whether there is short circuit phenomenon.Described metal wire part insulativity test also can form the metal pattern shown in Fig. 6 as test structure in the Semiconductor substrate of semiconductor devices, and in Semiconductor substrate, forming the dielectric layer that covers described metal pattern, test structure and described metal pattern that between described metal wire, insulativity test adopts can be same structure.Therefore, thereby realized the multiplexing of test structure, without the existing structure that changes semiconductor devices, method is simple, and cost is low.
In the time adopting the metal pattern shown in Fig. 6 to carry out between metal wire insulativity test, need to test the electric current between the first electrode 100 and the second electrode 200, it is known for those skilled in the art, does not repeat them here; In the time adopting the metal pattern shown in Fig. 6 to carry out in dielectric layer air clearance test, need to test the electric capacity between the first electrode 100 and the second electrode 200, can describe in detail in the back.
Because dielectric layer is formed between the first electrode and the second electrode, the size of the through hole forming between the first electrode and the second electrode is very little, therefore in dielectric layer, is easy to produce clearance.The present embodiment is when not existing clearance or clearance very hour can think that the dielectric layer in semiconductor devices is up-to-standard in dielectric layer; In the time that the size of clearance in dielectric layer is larger, think that the dielectric layer in semiconductor devices is off quality, thereby this semiconductor devices is defective.
Then, provide the capacity standard value between described the first electrode and described the second electrode.
Described capacity standard value refer in dielectric layer, do not exist clearance or clearance when negligible described in capacitance between the first electrode and described the second electrode, capacitance when the dielectric layer in semiconductor devices is up-to-standard between the first electrode and the second electrode.
In an example, described capacity standard value can be obtained by the mode of calculating, and specifically can calculate by formula below:
Wherein, C represents the electric capacity between the first electrode and the second electrode, and ε represents the dielectric constant of dielectric layer, and S represents the relative area of the first electrode and the second electrode, and k represents electrostatic force constant, and d is the distance between the first electrode and the second electrode.
In another example, described capacity standard value can be obtained by the mode of measuring, specifically can be by the capacitance between the first electrode and the second electrode in the up-to-standard semiconductor devices of test dielectric layer as described capacity standard value.
Further, can also test the capacitance between the first electrode and the second electrode in the up-to-standard multiple semiconductor devices of dielectric layer, and using the mean value of multiple capacitances as described capacity standard value, thereby test accuracy rate further improved.
Then, detect the electric capacity actual value between described the first electrode and described the second electrode.
Described electric capacity actual value refers to the capacitance between described the first electrode and described the second electrode obtaining by actual measurement, and its concrete measuring method is known for those skilled in the art, does not repeat them here.
It should be noted that, can adjust the order of obtaining of described electric capacity actual value and described capacity standard value, it does not limit the scope of the invention.
Then, whether the ratio between the absolute value of the difference of more described electric capacity actual value and described capacity standard value and described capacity standard value is greater than threshold value.
In the time there is clearance in described dielectric layer, the electric capacity actual value between described the first electrode and described the second electrode will inevitably change, and clearance is larger, and capacitance variations is larger.
The present embodiment is considered between the design size of metal pattern and physical size may there is minor deviations, and when the clearance that exists in dielectric layer very hour also can think that the dielectric layer in semiconductor devices is up-to-standard, therefore as long as when the ratio between absolute value and the described capacity standard value of the difference of described electric capacity actual value and described capacity standard value is less than threshold value, just can thinks in described dielectric layer and not have clearance; When ratio between the absolute value of the difference of described electric capacity actual value and described capacity standard value and described capacity standard value is greater than threshold value, in described dielectric layer, there is clearance.
It should be noted that, when ratio between the absolute value of the difference of described electric capacity actual value and described capacity standard value and described capacity standard value equals threshold value, both can judge to draw in described dielectric layer and have clearance, and also can judge to draw and in described dielectric layer, do not have clearance.
Threshold value described in the present embodiment can be more than or equal to 10%, as: 10%, 12%, 15%, 18% or 20% etc.
It should be noted that, in other embodiments of the invention, described threshold value can be selected other value, and it does not limit the scope of the invention.
Further, after adopting above-mentioned electrical method to judge to have clearance in described dielectric layer, the present embodiment can also adopt the method for failure analysis further to detect described semiconductor devices, thereby verify the accuracy of described electrical method, and optimize the value of described threshold value according to the result, finally can further improve the accuracy of detection.
Because metal pattern in the present embodiment is comb capacitance structure, thereby can increase the area of metal pattern, increase the capacitance between the first electrode and the second electrode, make the difference between electric capacity actual value and electric capacity theoretical value more obvious, reduce the difficulty detecting, improved the accuracy of judgement.
Because test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure, thereby realized the multiplexing of test structure, without the existing test structure that changes semiconductor devices, method is simple, and cost is low.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a method of testing for semiconductor devices, is characterized in that, comprising:
Semiconductor devices is provided, and described semiconductor devices comprises: Semiconductor substrate; Be positioned at the metal pattern in described Semiconductor substrate, described metal pattern comprises the first electrode and the second electrode; Dielectric layer between the above first electrode of described Semiconductor substrate and described the second electrode;
Capacity standard value between described the first electrode and described the second electrode is provided, and detects the electric capacity actual value between described the first electrode and described the second electrode;
In the time that the ratio between absolute value and the described capacity standard value of the difference of described electric capacity actual value and described capacity standard value is greater than threshold value, judges in described dielectric layer and have clearance.
2. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, the material of described metal pattern comprises aluminium or tungsten.
3. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, the material of described dielectric layer is low-k materials or super low-k materials.
4. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, described metal pattern is comb capacitance structure.
5. the method for testing of semiconductor devices as claimed in claim 4, it is characterized in that, also comprise: described semiconductor devices is carried out to wafer and permit Acceptance Tests, described wafer permits Acceptance Tests to comprise insulativity test between metal wire, and test structure and described metal pattern that between described metal wire, insulativity test adopts are same structure.
6. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, described dielectric layer adopts high density plasma CVD method to form.
7. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, described threshold value is more than or equal to 10%.
8. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, described capacity standard value is obtained by the mode of calculating.
9. the method for testing of semiconductor devices as claimed in claim 1, is characterized in that, described capacity standard value is obtained by the mode of measuring.
10. the method for testing of semiconductor devices as claimed in claim 1, it is characterized in that, after judging and having clearance in described dielectric layer, the method for testing of described semiconductor devices also comprises: adopt the method for failure analysis to detect described semiconductor devices.
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