CN204088304U - Semi-conductor test structure - Google Patents
Semi-conductor test structure Download PDFInfo
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- CN204088304U CN204088304U CN201420547260.6U CN201420547260U CN204088304U CN 204088304 U CN204088304 U CN 204088304U CN 201420547260 U CN201420547260 U CN 201420547260U CN 204088304 U CN204088304 U CN 204088304U
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- trap
- doped region
- heavily doped
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- type heavily
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Abstract
The utility model discloses a kind of semi-conductor test structure.Described semi-conductor test structure is for detecting the reliability of gate oxide, comprise: substrate, multiple detection block and grid structure, in described substrate, be formed with adjacent N trap and P trap, described multiple detection block is formed in N trap and P trap, and grid structure comprises the gate oxide across adjacent N trap and P trap.Test structure of the present utility model is by combining N trap and P trap, effectively save layout (layout) space, and, the relevant parameter of N well region and P well area directly can be obtained when testing, compared to existing technology, decrease the workload of test, shorten the testing time, be conducive to increasing work efficiency.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly relates to a kind of semi-conductor test structure about GOI (gate oxide integrality).
Background technology
Along with the development of technology, the thickness of the gate oxide of integrated circuit is also down to below 1nm by 20 ~ 30nm.Gate oxide is constantly to film future development, and supply voltage should not reduce.Under higher electric field strength, the performance of gate oxide certainly will be made to become distinct issues.Grid oxygen resistance to voltage is bad will cause MOS device electrical quantity not quietly, such as threshold voltage shift, and mutual conductance declines, and leakage current increase etc., can cause puncturing of grid oxygen further, cause the inefficacy of device.
To a kind of measuring technology of GOI be Vrmap (ramp voltage) test, this method on grid, applies linear ramp until oxide layer is breakdown.Vramp test is mainly for assessment of the defect concentration problem of gate oxide.
Please refer to Fig. 1 a and Fig. 1 b, which respectively show structure required when a kind of Vramp tests.Shown in Fig. 1 a, structure is N-type test structure, comprises the N trap be formed in substrate 1, is formed with P type heavily doped region (P in N trap
+) and N-type heavily doped region (N
+) and isolation structure, substrate 1 is formed with grid structure, comprise gate oxide 4 and grid polycrystalline silicon 5, the P type heavily doped region external connection being positioned at grid structure both sides draws formation source and drain 3, and N-type heavily doped region is then drawn by external connection and formed test section (bulk) 2.Structure shown in Fig. 2 a is P type test structure, similar with Fig. 1 a, and difference is that the doping type of trap and heavily doped region thickness that is different and gate oxide 4 is different.
At present when carrying out Vramp test, need respectively to the bulk of N trap and P trap, polysilicon border (poly edge) and border, field (field edge) totally six parts test.Because the structure on N trap and P trap has difference, the thickness of such as gate oxide is different, also causes the GOI performance of N trap and P trap inconsistent.Based on these factors, cause circulation timei when testing, test area size, the quantity of feeler switch and the workload of test to be also all restricted, the object of High-efficient Production cannot be reached.
Utility model content
The purpose of this utility model is, provides a kind of semi-conductor test structure, to save the testing time, simplifies test structure, improves testing efficiency.
For solving the problems of the technologies described above, the utility model provides a kind of semi-conductor test structure, for detecting the reliability of gate oxide, comprising:
Substrate, is formed with adjacent N trap and P trap in described substrate;
Multiple detection block, described multiple detection block is formed in N trap and P trap; And
Grid structure, comprises the gate oxide across adjacent N trap and P trap.
Optionally, for described semi-conductor test structure, be formed with multiple N trap and P trap in described substrate, described N trap and P trap are alternately arranged.
Optionally, for described semi-conductor test structure, be formed with multiple N trap and P trap in described substrate, described N trap and P trap are spaced in sphere of movements for the elephants type.
Optionally, for described semi-conductor test structure, described gate oxide above N trap is different with the thickness of the gate oxide above P trap.
Optionally, for described semi-conductor test structure, described multiple detection block is included in the N-type heavily doped region and P type heavily doped region that are all formed in N trap and P trap, and described N-type heavily doped region and P type heavily doped region are by shallow trench isolation interval.
Optionally, for described semi-conductor test structure, the P type heavily doped region in described N trap than N-type heavily doped region near grid structure, the N-type heavily doped region in described P trap than P type heavily doped region near grid structure.
Optionally, for described semi-conductor test structure, the P type heavily doped region in described N trap is formed with drain electrode, and the N-type heavily doped region in described P trap is formed with source electrode.
Optionally, for described semi-conductor test structure, the P type heavily doped region in the N-type heavily doped region in described N trap and described P trap is formed with test section.
Optionally, for described semi-conductor test structure, described grid structure also comprises the grid polycrystalline silicon covered on described gate oxide.
The semi-conductor test structure that the utility model provides, by being formed with adjacent N trap and P trap in described substrate, by needing two structures formed to be combined into a structure in prior art, therefore effectively saves layout (layout) space; Further, by N trap and P trap are combined, making the relevant parameter that directly can obtain N well region and P well area when testing, compared to existing technology, decreasing the workload of test, shortening the testing time, being conducive to increasing work efficiency.
Accompanying drawing explanation
Fig. 1 a is a kind of structural representation of semi-conductor test structure in prior art;
Fig. 1 b is the another kind of structural representation of semi-conductor test structure in prior art;
Fig. 2 is the schematic diagram of semi-conductor test structure in the utility model embodiment;
Fig. 3 is a kind of vertical view of semi-conductor test structure in the utility model embodiment;
Fig. 4 is the another kind of vertical view of semi-conductor test structure in the utility model embodiment.
Embodiment
Below in conjunction with schematic diagram, semi-conductor test structure of the present utility model is described in more detail, which show preferred embodiment of the present utility model, should be appreciated that those skilled in the art can revise the utility model described here, and still realize advantageous effects of the present utility model.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as to restriction of the present utility model.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the utility model chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the utility model is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
As stated in the Background Art, test structure of the prior art comprises N-type test structure and P type test structure two kinds of structures, and this causes testing efficiency low.For this reason, the utility model provides a kind of semi-conductor test structure, comprising:
One substrate, is formed with adjacent N trap and P trap in described substrate;
Multiple detection block, described multiple detection block is formed in N trap and P trap; And
Grid structure, comprises the gate oxide across adjacent N trap and P trap.
Please refer to Fig. 2, semi-conductor test structure of the present utility model, comprising: substrate, adjacent N trap 21 and P trap 22 is formed in described substrate, although as test structure, described N trap 21 and P trap 22 can adopt and be formed with the same process of device region, and can be together formed with device region.Described N trap 21 and P trap 22 are doped region, and this doping situation is conventionally known to one of skill in the art, and description will be omitted.
Incorporated by reference to Fig. 3, described N trap 21 and P trap 22 are multiple, and in a preferred embodiment, described N trap 21 and P trap 22 are arranged alternately, and are arranged in order.When testing, multiple N trap 21 can be drawn together, same also can draw multiple P trap together, once tests to facilitate.
N-type test structure of the prior art and P type test structure can occupy very large space, and also there is idle area therebetween.And in the present embodiment, just avoid this situation, save arrangement space to a great extent, thus be conducive to improving integrated level.
Another kind of preferred embodiment please refer to Fig. 4, and described N trap 21 and P trap 22 are multiple, and described N trap and P trap are spaced in sphere of movements for the elephants type.Certainly, as being only respectively illustrate two N traps 21 and two P traps 22 in Fig. 4, in fact, described N trap 21 and P trap 22 can recline the form of a P trap to any one Directional Extension according to a N trap.Same, this embodiment also also exists very large advantage compared to existing technology in space layout.
Please continue to refer to Fig. 2, grid structure is formed above the N trap 21 and P trap 22 of substrate, concrete, there is shown gate oxide 26 and cover the grid polycrystalline silicon 27 of described gate oxide 26, eliminate other retes of grid structure, described gate oxide 26 is across above N trap 21 and P trap 22.
In the N trap 21 and P trap 22 of described grid structure both sides, be formed with multiple detection block respectively, comprise the P type heavily doped region (P of the close grid structure be formed in N trap 21
+) and away from the N-type heavily doped region (N of grid structure
+), and, be formed at the N-type heavily doped region (N near grid structure in P trap 22
+) and away from the P type heavily doped region (P of grid structure
+).
Preferably, doped with P (phosphorus) or As (arsenic) in N-type heavily doped region, doped with B (boron) in P type heavily doped region.Due to the difference of doping, in the utility model, make the two-part thickness of described gate oxide 26 above N trap 21 with P trap 22 different.This by by detecting after block picks out accordingly, can detect the situation of each autodoping, to learn whether existing defects.
As shown in Figure 2, kept apart from 28 by shallow trench isolation between described P type heavily doped region and N-type heavily doped region.Preferably, the degree of depth of described shallow trench isolation from 28 exists
between.
In the utility model, in the described P type heavily doped region of N trap 21, form drain region, picked out by external connection, and form weld pad 24; Form source area in described N-type heavily doped region in P trap 22, picked out by external connection, and form weld pad 23; N-type heavily doped region in N trap 21 and the P type heavily doped region in P trap 22 then form test section, picked out, and form weld pad 25 by external connection.The formation of described drain region, source area and test section can be applied with extra doping, and preferably, concrete doping situation can be adjusted according to the situation of the device region of different process, and the utility model does not make particular determination to this.
Utilizing this structure, when testing, by applying test voltage on weld pad and on grid structure, the parameter of N trap part and the parameter of P trap part can be obtained simultaneously.Concrete, for structure shown in Fig. 3, once can record the parameter of multiple N trap part and P trap part, therefore compared to existing technology, simplify test process.In addition, after once testing, the parameter of N trap part and the parameter of P trap part are compared, the exception that may exist can be found, again can measure the structure of a certain N trap 21 or the structure of P trap 22 separately according to analysis afterwards.
As can be seen here, test structure provided by the utility model, not only obtains simplification in layout, can save space, also simplify test process, can either obtain more data, can reduce again the number of times of test, improve testing efficiency when testing.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (9)
1. a semi-conductor test structure, for detecting the reliability of gate oxide, is characterized in that, comprising:
Substrate, is formed with adjacent N trap and P trap in described substrate;
Multiple detection block, described multiple detection block is formed in N trap and P trap; And
Grid structure, comprises the gate oxide across adjacent N trap and P trap.
2. semi-conductor test structure as claimed in claim 1, it is characterized in that, be formed with multiple N trap and P trap in described substrate, described N trap and P trap are alternately arranged.
3. semi-conductor test structure as claimed in claim 1, it is characterized in that, be formed with multiple N trap and P trap in described substrate, described N trap and P trap are spaced in sphere of movements for the elephants type.
4. semi-conductor test structure as claimed in claim 1, it is characterized in that, described gate oxide above N trap is different with the thickness of the gate oxide above P trap.
5. semi-conductor test structure as claimed in claim 1, it is characterized in that, described multiple detection block is included in the N-type heavily doped region and P type heavily doped region that are all formed in N trap and P trap, and described N-type heavily doped region and P type heavily doped region are by shallow trench isolation interval.
6. semi-conductor test structure as claimed in claim 5, is characterized in that, the P type heavily doped region in described N trap than N-type heavily doped region near grid structure, the N-type heavily doped region in described P trap than P type heavily doped region near grid structure.
7. semi-conductor test structure as claimed in claim 6, it is characterized in that, be formed with drain electrode in the P type heavily doped region in described N trap, the N-type heavily doped region in described P trap is formed with source electrode.
8. semi-conductor test structure as claimed in claim 6, is characterized in that, the P type heavily doped region in the N-type heavily doped region in described N trap and described P trap is formed with test section.
9. semi-conductor test structure as claimed in claim 1, is characterized in that, described grid structure also comprises the grid polycrystalline silicon covered on described gate oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420547260.6U CN204088304U (en) | 2014-09-22 | 2014-09-22 | Semi-conductor test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420547260.6U CN204088304U (en) | 2014-09-22 | 2014-09-22 | Semi-conductor test structure |
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| Publication Number | Publication Date |
|---|---|
| CN204088304U true CN204088304U (en) | 2015-01-07 |
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ID=52180984
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420547260.6U Expired - Fee Related CN204088304U (en) | 2014-09-22 | 2014-09-22 | Semi-conductor test structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504184A (en) * | 2019-08-27 | 2019-11-26 | 上海华力集成电路制造有限公司 | Aoxidize layer defects phenomenon risk assessment feeler switch and the test method using it |
| CN112490216A (en) * | 2020-11-27 | 2021-03-12 | 上海华力微电子有限公司 | WAT test structure and method for characterizing PN junction depletion region |
-
2014
- 2014-09-22 CN CN201420547260.6U patent/CN204088304U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504184A (en) * | 2019-08-27 | 2019-11-26 | 上海华力集成电路制造有限公司 | Aoxidize layer defects phenomenon risk assessment feeler switch and the test method using it |
| CN112490216A (en) * | 2020-11-27 | 2021-03-12 | 上海华力微电子有限公司 | WAT test structure and method for characterizing PN junction depletion region |
| CN112490216B (en) * | 2020-11-27 | 2023-09-19 | 上海华力微电子有限公司 | WAT test structure and method for characterizing PN junction depletion region |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150107 Termination date: 20190922 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |