CN110504184A - Aoxidize layer defects phenomenon risk assessment feeler switch and the test method using it - Google Patents
Aoxidize layer defects phenomenon risk assessment feeler switch and the test method using it Download PDFInfo
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- CN110504184A CN110504184A CN201910794555.0A CN201910794555A CN110504184A CN 110504184 A CN110504184 A CN 110504184A CN 201910794555 A CN201910794555 A CN 201910794555A CN 110504184 A CN110504184 A CN 110504184A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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Abstract
The present invention relates to oxidation layer defects phenomenon risk assessment feeler switch and utilize its test method, it is related to semiconductor integrated circuit reliability test, by the way that multiple test structures are arranged in oxidation layer defects phenomenon risk assessment feeler switch, the gate regions of each test structure are arranged in a matrix by multiple sub- gate regions to be constituted, therefore the gate regions of different area can be obtained by the way that the number of gate regions neutron gate regions is arranged, cooperate the metal wire and diode of periphery again, the test structure different to size can be achieved and carry out grid oxygen layer defects risk assessment simultaneously, to reduce quantity and the testing time of conventional geodesic structure.
Description
Technical field
The present invention relates to semiconductor integrated circuit reliability test more particularly to a kind of oxidation layer defects phenomenon risk assessment
Feeler switch and the test method for utilizing it.
Background technique
With the development of semi-conductor industry, integrated circuit is to small in size, speed is fast, low-power consumption direction is developed.Semiconductor device
The characteristic size of part is constantly scaled, and size is smaller, and a possibility that integrity problem occur bigger, therefore in semiconductor collection
At field of circuit technology, semiconductor integrated circuit reliability test is more and more important.
In the development process of the platforms such as 28HKMG, since metal gates (Metal Gate) are generally ground using chemical machinery
Grinding process CMP is thinned to carry out, and CMP process has serious load effect (loading effect) phenomenon, in different gold
Belonging to the region gate densities (metal gate density) has different performances.It is eventually exhibited as overground or has metal gates metal
Residual, has a large amount of defect, so that primary failure occur when thus will lead to gate breakdown.Specifically, seeing Fig. 1, Fig. 1 is
The schematic diagram of metal gate structure defect.Metal gate structure include bulk substrate (bulk) 110, active area (AA) 120 and
Polysilicon (poly) 130 will meet between usual bulk substrate and active area with the raising of semiconductor integrated circuit integrated level
The width of Minimal rule (i.e. spacing minimum), active area and polysilicon gate not lap will also meet Minimal
rule.The size of aforementioned two o'clock is smaller, and defect (Defect) 140 more be easy to cause short circuit, then is easier discovery defect.
Therefore need to design different test structures to detect the health degree of metal gates CMP process.Due to general survey
Trying structure is all that a structure contains only a kind of design, determines that the CMP process risk under which kind of design is higher with this, therefore meeting
There is multiple and different test structures.It is also required to repeatedly be tested accordingly in test, and then needs the more testing time.
Specifically, seeing Fig. 2, Fig. 2 is the schematic diagram of the grid oxide layer breakdown test structure of the prior art, punctures test knot in grid oxide layer
In structure design, including test structure 100 and metal connecting line 200 and pad 300, wherein test structure TK (Test Key) is by leading
The structure compositions such as body substrate (bulk) 110, active area 120 and polysilicon 130 are used to Analogous Integrated Electronic Circuits device and are accelerating in fact
A kind of oxide layer breakdown of reliable life in testing tests structure.Need to design multiple and different test knots in the prior art
Structure detects the health degree of metal gates CMP process, needs the more testing time.
Summary of the invention
The purpose of the present invention is to provide a kind of oxidation layer defects phenomenon risk assessment feeler switch, to realize to size difference
Test structure simultaneously carry out grid oxygen layer defects risk assessment, to reduce quantity and the testing time of conventional geodesic structure.
Oxidation layer defects phenomenon risk assessment feeler switch provided by the invention, comprising: multiple test structures, wherein each survey
Trying structure includes a gate regions, and in bulk substrate, gate regions are arranged in a matrix by multiple sub- gate regions and are constituted gate region,
In each sub- gate regions be made of active area and the polysilicon on active area, in bulk substrate include base stage, source electrode and leakage
Pole, gate regions include grid, grid, base stage, source electrode and drain electrode through-hole draw, and source electrode, drain electrode through-hole and grid between
Away from the minimum range allowed for design rule；After base stage, the source electrode and drain electrode of multiple test structures are drawn by metal wire respectively
It is connected in parallel to the same detection welding pad PADB, the gate regions of multiple test structures are distinguished with a Diode series again later respectively
Same detection welding pad PADA is connected in parallel to after drawing by metal wire, and the gate regions of multiple test structures pass through metal respectively
Line is connected to detection welding pad PADx corresponding with each test gate regions of structure after drawing, and for x from 1 to n etc., n is test knot
The number of structure.
Further, the active area that the sub- gate regions in different gate regions are arranged is different with the arrangement of polysilicon.
Further, sub- gate regions include active area and the polysilicon on active area, wherein active area and polycrystalline
Silicon is all block structure.
Further, sub- gate regions include active area and the polysilicon on active area, and wherein active area is bulk
Structure, polysilicon are strip structure.
Further, meet spacing minimum principle between a polysilicon and adjacent strip polysilicon.
Further, sub- gate regions include active area and the polysilicon on active area, and wherein polysilicon is bulk
Structure, active area are strip structure.
Further, the width of active area and polysilicon not lap meets spacing minimum principle.
Further, each sub- gate regions constitute a square structure, have a long and width, wherein long and wide value model
It encloses for 1um to any value between 30um.
Further, each sub- gate regions constitute a square structure, have a long and width, wherein long and wide value model
It encloses for 1um to any value between 30um.
Further, each gate regions include c sub- gate regions in the X-axis direction, are wrapped in the Y-axis vertical with X-axis
D sub- gate regions are included, wherein the value range of c is any value between 1 to 30, and the value range of d is any between 1 to 30
Value.
Further, the number of the sub- gate regions of each gate regions in the X-axis direction is equal to the sub- gate regions in Y-axis
Number.
Further, the number of the sub- gate regions of each gate regions in the X-axis direction is not equal to the sub- grid in Y-axis
The number in area.
The present invention also provides a kind of test method using above-mentioned oxidation layer defects phenomenon risk assessment feeler switch, packets
It includes: S1: obtaining judgment basis of the predetermined current as oxidation layer defects risk, be then grounded PADB, in PADA and PADB
Between making alive, and the voltage being applied between PADA and PADB is stepped up from low to high, until the leakage current measured reaches
Predetermined current, record are applied to the voltage Vbd between PADA and PADB at this time, and test terminates；S2: judging voltage Vbd, if electric
It presses Vbd to be greater than or equal to preset value, is then tested key and defect problem is not present, if voltage Vbd is less than preset value, be tested key
Existing defects problem.
Further, further includes: S3: PADB being grounded, PADA is in hanging, successively in the grid with each test structure
Making alive on the corresponding detection welding pad PADx in polar region, diode plays the role of the different test structures of separation at this time, while real
Now test interstructural mutual open circuit, if it find that it is any test structure the corresponding detection welding pad PADx in gate regions and PADB it
Between branch be abnormal, then illustrate the detection welding pad it is corresponding test structure be defect occur position, x is from 1 to n etc., n
For the number for testing structure.
Further, the mode of a predetermined current is obtained in step S1 are as follows: predetermined current is according to JEDEC-35a standard
In formulaIt calculates and obtains, wherein predetermined current is referred to when Slopenew is greater than 3
Leakage current value I (n), wherein Slopenew refers to slope, and V (n)-V (n-1) refers to unit stepped voltage, abs (ln (abs (I
(n)))-ln (abs (I (n-1)))) it refers to a bit new absolute value of logarithm of leakage current absolute value and subtracts older electric leakage
Flow the difference of the absolute value of the logarithm of absolute value.
Further, the leakage current in step S1 is obtained by the electric current on measurement PADA or PADB.
Further, the preset value in step S2 is 2.3 times of device operating voltages.
Further, in step s3 by measuring the branch for flowing through any of detection welding pad PADx between PADB
Electric current judge whether branch generation of any of the detection welding pad PADx between PADB is abnormal, judge that this is tested with this
Trying key whether there is defect problem, and for x from 1 to n etc., n is the number for testing structure.
Further, it is stepped up from low to high in step s3 and is applied to any of detection welding pad PADx and PADB
Between voltage, until the leakage current that measures has reached predetermined current, record be applied at this time detection welding pad PADx and PADB it
Between voltage Vbd, judge voltage Vbd, if voltage Vbd is greater than or equal to preset value, which is not present defect problem,
If voltage Vbd is less than preset value, the tested key existing defects problem, for x from 1 to n etc., n is the number for testing structure.
Oxidation layer defects phenomenon risk assessment feeler switch provided by the invention and the operating method using it, by aoxidizing
Multiple test structures are set in layer defects phenomenon risk assessment feeler switch, and the gate regions of each test structure are by multiple sub- gate regions
Composition is arranged in a matrix, therefore the gate regions of different area can be obtained by the way that the number of gate regions neutron gate regions is arranged, then match
Close periphery metal wire with diode, it can be achieved that the test structure different to size simultaneously carry out grid oxygen layer defects risk assessment,
To reduce quantity and the testing time of conventional geodesic structure.
Detailed description of the invention
Fig. 1 is the schematic diagram of metal gate structure defect.
Fig. 2 is the schematic diagram of the grid oxide layer breakdown test structure of the prior art.
Fig. 3 is the schematic diagram of oxidation layer defects phenomenon risk assessment feeler switch of the invention.
Fig. 4 is the different designs mode of the test structural sub-units of one embodiment of the invention and its carries out showing for matrix arrangement
It is intended to.
Fig. 5 is the schematic diagram using the feeler switch shown in Fig. 3 test test whether defective risk of structure.
The reference numerals are as follows for main element in figure:
210, metal wire；102, bulk substrate；100, structure is tested；101, gate regions；410, metal wire；510, two pole
Pipe；310, metal wire.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In order to realize to including the different test structure of different designs mode, size while carrying out grid oxygen layer defects risk and comment
Estimate, to reduce quantity and the testing time of conventional geodesic structure.In one embodiment of the invention, it is to provide a kind of oxidation break
Fall into phenomenon risk assessment feeler switch.Referring to Fig. 3, Fig. 3 is showing for oxidation layer defects phenomenon risk assessment feeler switch of the invention
It is intended to, and referring to Fig. 4, Fig. 4 is the different designs mode of the test structural sub-units of one embodiment of the invention and its carries out square
The schematic diagram of battle array arrangement.Specifically, the oxidation layer defects phenomenon risk assessment feeler switch, comprising: multiple test structures 100,
In each test structure 100 include a gate regions 101, gate regions 101 are located in bulk substrate (bulk) 102, and gate regions are by more
Composition is arranged in a matrix in a sub- gate regions 600, as shown in Fig. 4 d, Fig. 4 e and Fig. 4 f, wherein each sub- gate regions 600 are by active area
120 and polysilicon 130 on active area 120 constitute, include base stage, source electrode and drain electrode, grid in bulk substrate (bulk) 102
Polar region 101 includes grid, the through-hole extraction of grid, base stage, source electrode and drain electrode, and the spacing of source electrode, the through-hole of drain electrode and grid
The minimum range allowed for design rule；And base stage, the source electrode and drain electrode of multiple test structures pass through metal wire 210 respectively and draw
After be connected in parallel to the same detection welding pad PADB, it is connected with a diode 510 respectively in the gate regions 101 of multiple test structures
Same detection welding pad PADA, and the gate regions of multiple test structures are connected in parallel to after drawing respectively by metal wire 410 again afterwards
101 respectively by being connected to detection welding pad PADx, x corresponding with each test gate regions 101 of structure after the extraction of metal wire 310
From 1 to n etc., n is the number for testing structure 100, also the as number of gate regions 101, as shown in figure 3, n=3, x 1,2 or
3。
As described above, the present invention by oxidation layer defects phenomenon risk assessment feeler switch in multiple test structures are set,
The gate regions of each test structure are arranged in a matrix by multiple sub- gate regions to be constituted, therefore can be by the way that gate regions neutron grid is arranged
The number in area obtains the gate regions of different area, then cooperates the metal wire of periphery with diode, it can be achieved that the survey different to size
Examination structure carries out grid oxygen layer defects risk assessment simultaneously, to reduce quantity and the testing time of conventional geodesic structure.
Specifically, in an embodiment of the present invention, the sub- gate regions in gate regions are according to gate structure in actual process
Difference can have different structures, to cover gate structure different in actual process.In an embodiment of the present invention, it is arranged not
It is different with the arrangement of the active area 120 and polysilicon 130 of the sub- gate regions 600 in gate regions 101, to realize sub- gate regions not
The arrangement of the active area 120 and polysilicon 130 of same design method namely the sub- gate regions 600 in a settable gate regions 101 with
The arrangement of the active area 120 of sub- gate regions 600 in another gate regions 101 and polysilicon 130 is different.Specifically, in the present invention
In one embodiment, the structure of a sub- gate regions sees Fig. 4 a, and sub- gate regions include active area 120 and are located on active area 120
Polysilicon 130, wherein active area 120 and polysilicon 130 are all block structure.Specifically, in an embodiment of the present invention,
The structure of neutron gate regions sees Fig. 4 b, and sub- gate regions include active area 120 and the polysilicon 130 on active area 120,
Wherein active area 120 is block structure, and polysilicon 130 is strip structure.More specifically, for structure shown in Fig. 4 b, one
Meet minimum (the i.e. Minimal rule) principle of spacing between polysilicon and adjacent strip polysilicon, its purpose is to obtain to the greatest extent may be used
The big effective dimensions of energy.Specifically, in an embodiment of the present invention, the structure of neutron gate regions sees Fig. 4 c, sub- grid
Area includes active area 120 and the polysilicon 130 on active area 120, and wherein polysilicon 130 is block structure, active area 120
For strip structure, more specifically, for structure shown in Fig. 4 c, the width of active area 120 and polysilicon 130 not lap is accorded with
It closes spacing minimum principle (i.e. Minimal rule).Can so it make in oxidation layer defects phenomenon risk assessment feeler switch of the invention
Test structure include the sub- gate regions of different arrangements, it can be achieved that test structure to different designs mode while carrying out grid oxide layer
Defect risk assessment, to reduce quantity and the testing time of conventional geodesic structure.
Specifically, in an embodiment of the present invention, each sub- gate regions 600 constitute a square structure, there is a long and width,
Wherein long and wide value range is 1um to any value between 30um.
Specifically, in an embodiment of the present invention, each gate regions 101 include c sub- gate regions 600 in the X-axis direction,
It include d sub- gate regions in the Y-axis vertical with X-axis, wherein the value range of c is any value between 1 to 30, the value of d
Range is any value between 1 to 30.Specifically, in an embodiment of the present invention, each gate regions 101 are in the X-axis direction
The number of sub- gate regions 600 is equal to the number of the sub- gate regions in Y-axis.Or, in an embodiment of the present invention, each gate regions
Number of the number of 101 sub- gate regions 600 in the X-axis direction not equal to the sub- gate regions in Y-axis.It can be according to actual
Testing requirement change, then cooperate above-mentioned each sub- gate regions 600 length and wide value range be 1um between 30um appoint
One value, the area that the gate regions in test structure as shown in Figure 3 can be obtained is different, as shown in Figure 3 from left to right, gate regions
Area can be to be gradually reduced.
In an embodiment of the present invention, the test using above-mentioned oxidation layer defects phenomenon risk assessment feeler switch is also provided
Method, comprising:
S1: judgment basis of the predetermined current as oxidation layer defects risk is obtained, is then grounded PADB (base stage), In
Making alive between PADA (grid) and PADB (base stage), and be stepped up be applied to PADA (grid) and PADB (base from low to high
Pole) between voltage, until the leakage current that measures has reached predetermined current, record is applied to PADA (grid) and PADB at this time
Voltage Vbd between (base stage), test terminates at this time；
S2: judging voltage Vbd, if voltage Vbd is greater than or equal to preset value, is tested key and defect problem is not present, if
Voltage Vbd is less than preset value, then is tested key existing defects problem.
It is above-mentioned for the gate regions of further positioning defect problem in the case where judging tested key existing defects problem
The test method using above-mentioned oxidation layer defects phenomenon risk assessment feeler switch, further includes:
S3: PADB (base stage) is grounded, and PADA is in hanging, successively corresponding with each test gate regions 101 of structure
Detection welding pad PADx on making alive, diode 510 plays the role of the different test structures 100 of separation at this time, realizes simultaneously
Interstructural mutual open circuit is tested, if it find that the corresponding detection welding pad PADx and PADB in gate regions 101 of any test structure
Between branch be abnormal, then illustrate the PAD it is corresponding test structure be defect occur position, from 1 to n etc., n is x
The number of structure 100 is tested, also the as number of gate regions 101.
In an embodiment of the present invention, the mode of a predetermined current is obtained in step S1 are as follows: according to predetermined current
Formula in JEDEC-35a standardIt calculates and obtains, wherein predetermined current reference is worked as
Slopenew is greater than the leakage current value I (n) when 3, and wherein Slopenew refers to slope, and V (n)-V (n-1) refers to unit stepping electricity
Pressure, the absolute value that abs (ln (abs (I (n)))-ln (abs (I (n-1)))) refers to the newly logarithm of the leakage current absolute value of any subtract
Go the difference of the absolute value of the logarithm of older leakage current absolute value.
In an embodiment of the present invention, the leakage current in step S1 is obtained by the electric current on measurement PADA or PADB.
In an embodiment of the present invention, the preset value in step S2 is 2.3 times of device operating voltages (Vop).
In an embodiment of the present invention, in step s3 by measure flow through any of detection welding pad PADx and PADB it
Between branch electric current judge any of detection welding pad PADx between PADB branch generation whether be abnormal, sentenced with this
The tested key break with the presence or absence of defect problem.Or be stepped up from low to high be applied to any of detection welding pad PADx with
Voltage between PADB, until the leakage current that measures has reached predetermined current, record be applied at this time detection welding pad PADx and
Voltage Vbd between PADB (base stage), judges voltage Vbd, if voltage Vbd is greater than or equal to preset value, the tested key is not
Existing defects problem, if voltage Vbd is less than preset value, the tested key existing defects problem, for x from 1 to n etc., n is test
The number of structure 100, the also as number of gate regions 101.
Referring to Fig. 5, Fig. 5 is the schematic diagram that the whether defective risk of structure is tested using feeler switch shown in Fig. 3 test,
The defect of gate regions and base stage short circuit occurs for first test structure in left side as shown in Figure 5, then in test, by PADB (base
Pole) ground connection, PADA (grid) it is additional be initially 0V until leakage current reach predetermined current until when record be applied to PADA (grid
Pole) voltage Vbd.One batch has several feeler switch to carry out above-mentioned test, and wherein the Vbd of feeler switch is standard compliant, then should
Partial test is completed, and means that the part does not have defect, the Vbd of another part feeler switch is non-compliant, then the part
Feeler switch needs to carry out second test, means the defective risk in the part；Secondary survey is carried out to the non-compliant feeler switch of Vbd
Examination, PADB first is grounded at this time, recording voltage outside the end PAD1 plus when being initially 0V until leakage current reaches predetermined current
Vbd judges that Vbd is complied with standard, then structure is tested under the area does not have defect risk, then outside the end PAD2 plus to be initially 0V straight
Recording voltage Vbd when until leakage current reaching predetermined current, judges that Vbd is complied with standard, then structure is tested under the area does not have
Defect risk, then recording voltage Vbd, judgement outside the end PAD3 plus when being initially 0V until leakage current reaches predetermined current
If short circuit occurs or Vbd is not inconsistent standardization, the defective risk of structure is tested under the area, so far navigates to defective risk
Test structure.
In conclusion the present invention by oxidation layer defects phenomenon risk assessment feeler switch in multiple test structures are set,
The gate regions of each test structure are arranged in a matrix by multiple sub- gate regions to be constituted, therefore can be by the way that gate regions are arranged
The number of neutron gate regions obtains the gate regions of different area, then cooperates the metal wire and diode of periphery, can pass through test
As soon as test structure, is provided with and carries out oxide layer breakdown risk and defect risk to the structure of sizes and design method
The ability of assessment, and the prior art needs a plurality of (usually 3~5 or more) various sizes of test structure that could complete defect
Risk assessment and single test structure can only test a kind of structure, therefore the present invention can be generated quickly to due to defective workmanship
Grid oxygen layer defects carry out overall risk assessment, and distinguish the highest design scheme of risk in subsequent can be convenient.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (19)
1. a kind of oxidation layer defects phenomenon risk assessment feeler switch characterized by comprising
Multiple test structures, wherein each test structure includes a gate regions, gate region is in bulk substrate, and gate regions are by more
Composition is arranged in a matrix in a sub- gate regions, wherein each sub- gate regions are made of active area and the polysilicon on active area,
Include base stage, source electrode and drain electrode in bulk substrate, gate regions include grid, grid, base stage, source electrode and drain electrode through-hole draw,
And the spacing of source electrode, the through-hole of drain electrode and grid is the minimum range that design rule allows；
Base stage, the source electrode and drain electrode of multiple test structures are connected in parallel to the same detection welding pad after drawing respectively by metal wire
The gate regions of PADB, multiple test structures are connected in parallel with after being drawn respectively by metal wire again after a Diode series respectively
It is connected to and each test after being drawn respectively by metal wire to the gate regions of same detection welding pad PADA, and multiple test structures
From 1 to n etc., n is the number for testing structure by the corresponding detection welding pad PADx in the gate regions of structure, x.
2. oxidation layer defects phenomenon risk assessment feeler switch according to claim 1, which is characterized in that different grids are arranged
The arrangement of the active area of sub- gate regions in area and polysilicon is different.
3. oxidation layer defects phenomenon risk assessment feeler switch according to claim 2, which is characterized in that sub- gate regions include
Active area and the polysilicon on active area, wherein active area and polysilicon are all block structure.
4. oxidation layer defects phenomenon risk assessment feeler switch according to claim 2, which is characterized in that sub- gate regions include
Active area and the polysilicon on active area, wherein active area is block structure, and polysilicon is strip structure.
5. oxidation layer defects phenomenon risk assessment feeler switch according to claim 4, which is characterized in that polysilicon with
Meet spacing minimum principle between adjacent strip polysilicon.
6. oxidation layer defects phenomenon risk assessment feeler switch according to claim 2, which is characterized in that sub- gate regions include
Active area and the polysilicon on active area, wherein polysilicon is block structure, and active area is strip structure.
7. oxidation layer defects phenomenon risk assessment feeler switch according to claim 6, which is characterized in that active area and polycrystalline
The width of silicon not lap meets spacing minimum principle.
8. oxidation layer defects phenomenon risk assessment feeler switch according to claim 1, which is characterized in that each sub- gate regions
A square structure is constituted, it is long and wide to have one, wherein long and wide value range is 1um to any value between 30um.
9. oxidation layer defects phenomenon risk assessment feeler switch according to claim 2, which is characterized in that each sub- gate regions
A square structure is constituted, it is long and wide to have one, wherein long and wide value range is 1um to any value between 30um.
10. according to claim 1, the described in any item oxidation layer defects phenomenon risk assessment feeler switch in 2,8 or 9, feature exist
In, it includes d sub- gate regions in the Y-axis vertical with X-axis that each gate regions include c sub- gate regions in the X-axis direction,
The value range of middle c is any value between 1 to 30, and the value range of d is any value between 1 to 30.
11. oxidation layer defects phenomenon risk assessment feeler switch according to claim 10, which is characterized in that each gate regions
The number of sub- gate regions in the X-axis direction is equal to the number of the sub- gate regions in Y-axis.
12. oxidation layer defects phenomenon risk assessment feeler switch according to claim 10, which is characterized in that each gate regions
Number of the number of sub- gate regions in the X-axis direction not equal to the sub- gate regions in Y-axis.
13. a kind of test method using oxidation layer defects phenomenon risk assessment feeler switch described in claim 1, feature exist
In, comprising:
S1: judgment basis of the predetermined current as oxidation layer defects risk is obtained, is then grounded PADB, in PADA and PADB
Between making alive, and the voltage being applied between PADA and PADB is stepped up from low to high, until the leakage current measured reaches
Predetermined current, record are applied to the voltage Vbd between PADA and PADB at this time, and test terminates；
S2: judging voltage Vbd, if voltage Vbd is greater than or equal to preset value, is tested key and defect problem is not present, if voltage
Vbd is less than preset value, then is tested key existing defects problem.
14. test method according to claim 13, which is characterized in that further include:
S3: PADB is grounded, and PADA is in hanging, successively in detection welding pad PADx corresponding with each test gate regions of structure
Upper making alive, diode plays the role of the different test structures of separation at this time, while realizing the interstructural mutual open circuit of test,
If it find that the branch between the corresponding detection welding pad PADx and PADB in gate regions of any test structure is abnormal, then illustrate
The corresponding test structure of the detection welding pad is the position that defect occurs, and for x from 1 to n etc., n is the number for testing structure.
15. test method according to claim 13, which is characterized in that obtain the mode of a predetermined current in step S1
Are as follows: predetermined current is according to the formula in JEDEC-35a standardIt calculates and obtains, wherein in advance
If electric current refers to the leakage current value I (n) when Slopenew is greater than 3, wherein Slopenew refers to slope, and V (n)-V (n-1) refers to
For unit stepped voltage, abs (ln (abs (I (n)))-ln (abs (I (n-1)))) refers to pair of the newly leakage current absolute value of a bit
Several absolute values subtracts the difference of the absolute value of the logarithm of older leakage current absolute value.
16. test method according to claim 13, which is characterized in that obtained by the electric current on measurement PADA or PADB
Leakage current in step S1.
17. test method according to claim 13, which is characterized in that the preset value in step S2 is device operating voltages
2.3 times.
18. test method according to claim 14, which is characterized in that flow through detection welding pad by measuring in step s3
The electric current of branch between any of PADx and PADB judges branch hair of any of the detection welding pad PADx between PADB
Whether life is abnormal, and judges the tested key with the presence or absence of defect problem with this, for x from 1 to n etc., n is for testing structure
Number.
19. test method according to claim 14, which is characterized in that be stepped up application from low to high in step s3
In voltage of any of the detection welding pad PADx between PADB, until the leakage current measured has reached predetermined current, this is recorded
When be applied to voltage Vbd between detection welding pad PADx and PADB, judge voltage Vbd, if voltage Vbd be greater than or equal to it is default
Value, then defect problem is not present in the tested key, if voltage Vbd is less than preset value, the tested key existing defects problem, and x
From 1 to n etc., n is the number for testing structure.
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