CN103605064B - Prevent the method for electric leakage of probe test carrier - Google Patents
Prevent the method for electric leakage of probe test carrier Download PDFInfo
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- CN103605064B CN103605064B CN201310505133.XA CN201310505133A CN103605064B CN 103605064 B CN103605064 B CN 103605064B CN 201310505133 A CN201310505133 A CN 201310505133A CN 103605064 B CN103605064 B CN 103605064B
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Abstract
The invention discloses a kind of method preventing electric leakage of probe test carrier, adopt following steps: S1, a device under test is provided; S2, adopts the mode of insulation isolation to be placed in probe test carrier by described device under test; S3, carries out probe scanning to the region to be measured of described device under test, obtains a feature image; Two probes to be put according to described feature image and are pressed on any two traps contact electrode of described device under test by S4 respectively, check and adjust two probes to make it contact electrode with two traps all to contact well; S5, will wherein remove from trap contact electrode by a probe, and point is pressed on the electrode to be measured of described device under test, the bias voltage of the trap contact electrode then pressed by another root probe is set to zero volt, then tests the electrode to be measured of described device under test.The present invention enables the test of the test of device under test especially leakage current carry out more accurately, substantially increases the reliability of test data.
Description
Technical field
The present invention relates to semiconductor test technical field, particularly relate to atomic force nano probe test, a kind of specifically method preventing electric leakage of probe test carrier.
Background technology
Atomic force nano probe (AtomicForcenano-Probe, AFP) test confirm probe to contact with test electrode whether well time, will based on the electric leakage of device under test to objective table, when the electric leakage that probe test obtains is identical with ideal state, namely judge that probes touch is good, thus make the data of test have reliability, repeatability.But the drawback of this principle is, this electric leakage all exists in the overall process of test, when needs judge element leakage failure mechanism, the data of leakage current will be no longer accurate, for field effect transistor, the electric current that source, leakage, grid, trap detect and non-vanishing, proves really have electric current flow to objective table from the substrate of device under test and effectively cannot be collected by probe.Current data is as following table:
| IS | IG | ID | IW |
| 6.58E-10 | 5E-14 | 7.27E-10 | -3.5E-07 |
In upper table, IS, IG, ID, IW are respectively the electric current of source (source), grid (gate), leakage (drain), trap (well) four pole, visible four electric current sums are also non-vanishing, and IW trap electric current is large especially, illustrate that trap exists leaking electricity comparatively by force of 350nA and leaks between silicon substrate to objective table, this electric leakage will cause the test data of device under test not accurate enough and reliable.Therefore, how to prevent the electric current in the substrate of device under test from being leaked by probe test carrier, affecting test data accuracy is problem demanding prompt solution.
Chinese patent (publication number: CN102109569A) discloses a kind of method for dielectric breakdown test on gate oxide adopting, comprises the following steps: choose the test probe for testing in probe on the probe card; Described test probe is connected with test machine, and connecting path between test probe with test machine is connected current-limiting resistance; By on described test probe engaged test sample with the solder joint of gate oxide conducting; Applied the voltage increased linearly over time from zero volt to the gate oxide on described test sample by described test machine, meanwhile record the current value on gate oxide under each magnitude of voltage, until the current value measured increases to certain threshold value, represent that gate oxide is breakdown.The larger leakage current produced when the probe that this invention provides and method for dielectric breakdown test on gate oxide adopting can prevent gate oxide breakdown when testing effectively to the damage of probe and test machine, and still can accurately test out the voltage breakdown of gate oxide after can ensureing to add current-limiting resistance.
Chinese patent (publication number: CN101424705A) discloses a kind of probe column, for wafer sort, comprises: a circular body, is configured with LCD test section and I/O test section, and circular body has seat under a body seat of honour and a body; Most group's probe aperture, is configured in LCD test section and I/O test section, vertically runs through seat under the body seat of honour and body simultaneously; And most group's test probe, to be configured in etc. in probe aperture, to pass through the test signal of circular body; Most group's ground hole is configured in I/O test section; Most group's grounding pin, is embedded in one of them most group's ground holes of seat under the body seat of honour and body in close-fitting mode, and electrically conducts to circular body, with the noise of test probe that will be contiguous and leakage current ground connection; Most group's spaced ring, makes with insulating material, is configured at the end of probe aperture, with fixing test probe in circular body, and provides being electrically insulated of test probe and circular body.
Above-mentioned two patents electric current in the unexposed substrate how solving device under test in prior art are leaked by probe test carrier, affect the problem of test data accuracy.
Summary of the invention
For above-mentioned Problems existing, the present invention discloses a kind of method preventing electric leakage of probe test carrier, by the isolation of device under test and probe test carrier, the electric current effectively overcome in the substrate of device under test in prior art is leaked by probe test carrier, affects the problem of test data accuracy; In addition, be biased by carrying out zero potential to trap contact electrode, also effectively overcome due to after device under test and probe test carrier isolate, skin peace electric current (picocurrent) detector probe contacts the problem being difficult to realization.
To achieve these goals, the present invention adopts following technical scheme:
Prevent a method for electric leakage of probe test carrier, be applied in atomic force nano probe test, wherein, adopt following steps:
S1, provides a device under test;
S2, adopts the mode of insulation isolation to be placed in probe test carrier by described device under test;
S3, carries out probe scanning to the region to be measured of described device under test, obtains a feature image;
Two probes to be put according to described feature image and are pressed on any two traps contact electrode of described device under test by S4 respectively, check and adjust two probes to make it contact electrode with two traps all to contact well;
S5, will wherein remove from trap contact electrode by a probe, and point is pressed on the electrode to be measured of described device under test, the bias voltage of the trap contact electrode then pressed by another root probe is set to zero volt, then tests the electrode to be measured of described device under test.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, in described step S1, the described device under test provided is ground to layer to be measured by the method that de-layer is secondary.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, in described step S2, the mode of insulation isolation is adopted to be specially: by the bottom of described device under test by being placed in described probe test carrier after nonconductive adhesive material adhesion one chip fragment, the bottom of device under test and described probe test carrier to be insulated and isolates.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, in described step S4, the region to be measured of described device under test is provided with N number of trap contact electrode, and N is natural number; Check and adjust two probes and make it contact electrode with two traps all to contact well, concrete grammar is: inspection is pressed in the skin peace electric current between two probes on two traps contact electrodes respectively, and adjust the dynamics that presses and the position of two probes, contact good time obtain short-circuit current curve and skin peace electric current reach maximal value.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, the electrode to be measured of described device under test comprises source, leakage, gate electrode.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, described device under test comprises integrated circuit (IC)-components.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, described device under test comprises floating structural semiconductor device.
The above-mentioned method preventing electric leakage of probe test carrier, wherein, described floating structural semiconductor device comprises SOI device, electrically programmable fuse and polysilicon gate.
Tool of the present invention has the following advantages or beneficial effect:
1. device under test is placed in probe test carrier by the mode of insulation isolation, solve the electric leakage of substrate to probe test carrier of device under test, thus the test of the test of device under test especially leakage current is carried out more accurately, substantially increase the reliability of test data.
2. first probe points being pressed in the trap easily pressed contacts on electrode, and to this trap contact electrode carry out zero potential be biased, thus after solving device under test and probe test carrier being isolated, skin peace electric current cannot be detected thus the problem of probes touch situation cannot be judged.
3. method of the present invention can be applied to SOI(Silicon-On-Insulator, the silicon in dielectric substrate) device, E-fuse(electrically programmable fuse) and PolyGate(polysilicon gate) etc. floating (floating) structure.
4. because the probe Main Function on trap contact electrode is that trap contact electrode arranges bias voltage, therefore the new probe (ClassA) not needing situation best, the probe of surface oxidized (contact resistance is large) or needle point comparatively thick (feature image is inaccurate) can be used, thus save testing cost.
Concrete accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is that in first embodiment of the invention, device under test and probe test carrier insulate the structural representation of isolating;
Fig. 2 is the structural representation of device under test in first embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
First embodiment of the present invention relates to a kind of method preventing electric leakage of probe test carrier, is applied in atomic force nano probe test, wherein, adopts following steps:
S1, provides a device under test, and device under test is ground to layer to be measured by the method that de-layer is secondary.
S2, adopts the mode of insulation isolation to be placed in probe test carrier by device under test, the mode of insulation isolation is adopted to be specially: the bottom of device under test to be passed through nonconductive adhesive material (as double faced adhesive tape, solid gum, liquid glue etc.) adhere to a chip fragment after be placed in probe test carrier, the bottom of device under test and probe test carrier are insulated isolate, as shown in Figure 1, device under test and chip fragment are fixed together by nonconductive adhesive material, the fragment that this chip fragment selects front and back all smooth, thus, the mode of probe test carrier just by inhaling vacuum firmly fixes chip fragment, thus fixing device under test, prevent the slip of device under test during probe test, make test result more accurate.
Device under test is placed in probe test carrier by the mode of insulation isolation by present embodiment, solve the electric leakage of substrate to probe test carrier of device under test, thus the test of the test of device under test especially leakage current is carried out more accurately, substantially increase the reliability of test data.If but the substrate of isolation device under test and probe test carrier, can produce and cannot detect skin peace electric current thus the problem that cannot judge probes touch situation, the following steps of present embodiment can solve this problem.
S3, probe scanning is carried out in the region to be measured of device under test, obtains a feature image.
Two probes to be put according to feature image and are pressed on any two traps contact electrode of device under test by S4 respectively, check and adjust two probes to make it contact electrode with two traps all to contact well; The region to be measured of device under test is provided with N number of trap contact electrode 11, N is natural number, and trap contact electrode 11 is all positioned at well region, as shown in Figure 2, also comprise and lay respectively at source electrode 2, drain electrode 3, the source of grid 4, leakage, grid three pole electrode (21,31,41), and shallow channel isolation area (STI) 5; Check and adjust two probes and make it contact electrode with two traps all to contact well, concrete grammar is: inspection is pressed in the skin peace electric current between two probes on two traps contact electrodes respectively, and adjust the dynamics that presses and the position of two probes, contact good time obtain short-circuit current curve and skin peace electric current reach maximal value; Wherein, short-circuit current curve proves that two pins have all successfully been pressed on trap contact electrode, and skin peace electric current reaches maximal value and then illustrates that contact is good.
S5, will wherein remove from trap contact electrode by a probe, and point is pressed on the electrode to be measured of device under test, the bias voltage of the trap contact electrode then pressed by another root probe is set to zero volt, then tests the electrode to be measured of device under test.The electrode to be measured of device under test is conventionally tested, and is put on the source that is pressed in, leakage, gate electrode respectively by other three probes, completes corresponding test.After bias voltage trap being contacted electrode is set to zero volt (GND), serve the effect of skin peace level drain current path in original test, so identical with original testing process for the lower pin of source and drain.
Probe points is first pressed on the trap contact electrode that easily presses by present embodiment, and carries out zero potential to this trap contact electrode and be biased, thus after device under test and probe test carrier being isolated, can detect skin accurately and pacifies electric current and judge probes touch situation.
Wherein, the electrode to be measured of device under test comprises source, leakage, gate electrode.Device under test comprises integrated circuit (IC)-components, as CMOS, PN junction; Also comprise floating structural semiconductor device, as E-fuse, PolyGate.
The step of various method divides above, just in order to be described clearly, can merge into a step or splitting some step, being decomposed into multiple step, when realizing as long as comprise identical logical relation, all in the protection domain of this patent; To adding inessential amendment in algorithm or in flow process or introducing inessential design, but the core design not changing its algorithm and flow process is all in the protection domain of this patent.
Second embodiment of the present invention relates to a kind of method preventing electric leakage of probe test carrier, and present embodiment is roughly the same with the first embodiment, and its difference is, the device under test that present embodiment provides is SOI device.
Thus, in step s 2, adopted by device under test the mode of insulation isolation to be placed in probe test carrier, the substrate due to SOI device is dielectric substrate, therefore it is directly placed in probe test carrier, the bottom of device under test and probe test carrier just can be made to insulate and isolate.
For last two embodiments, such as, adopt the device under test of 55nm technology node, test the electric leakage data obtained as following table:
| IS | IG | ID | IW |
| 3.11E-10 | -1E-14 | 3.82E-10 | -6.9E-10 |
As can be seen here, the current summation of four electrodes is zero, proves that method of the present invention effectively can remove the electric leakage from the substrate of device under test to probe test carrier.Because the probe Main Function on trap contact electrode is that trap contact electrode arranges bias voltage, therefore the new probe (ClassA) not needing situation best, the probe of surface oxidized (contact resistance is large) or needle point comparatively thick (feature image is inaccurate) can be used, thus save testing cost.
It should be appreciated by those skilled in the art that those skilled in the art can realize change case in conjunction with prior art and above-described embodiment, such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. prevent a method for electric leakage of probe test carrier, be applied in atomic force nano probe test, it is characterized in that, adopt following steps:
S1, provides a device under test;
S2, adopts the mode of insulation isolation to be placed in probe test carrier by described device under test;
S3, carries out probe scanning to the region to be measured of described device under test, obtains a feature image;
S4, the region to be measured of wherein said device under test is provided with N number of trap contact electrode, N is natural number, to be put respectively by two probes be pressed on any two traps contact electrode of described device under test according to described feature image, checks and adjust two probes to make it contact electrode with two traps all to contact well;
S5, will wherein remove from trap contact electrode by a probe, and point is pressed on the electrode to be measured of described device under test, the bias voltage of the trap contact electrode then pressed by another root probe is set to zero volt, then tests the electrode to be measured of described device under test.
2. the method preventing electric leakage of probe test carrier according to claim 1, is characterized in that, in described step S1, the described device under test provided is ground to layer to be measured by the method that de-layer is secondary.
3. the method preventing electric leakage of probe test carrier according to claim 1, it is characterized in that, in described step S2, the mode of insulation isolation is adopted to be specially: by the bottom of described device under test by being placed in described probe test carrier after nonconductive adhesive material adhesion one chip fragment, the bottom of device under test and described probe test carrier to be insulated and isolates.
4. the method preventing electric leakage of probe test carrier according to claim 1, it is characterized in that, in described step S4, check and adjust two probes and make it contact electrode with two traps all to contact well, concrete grammar is: inspection is pressed in the skin peace electric current between two probes on two traps contact electrodes respectively, and adjust the dynamics that presses and the position of two probes, contact good time obtain short-circuit current curve and skin peace electric current reach maximal value.
5. the method preventing electric leakage of probe test carrier according to claim 1, is characterized in that, the electrode to be measured of described device under test comprises source, leakage, gate electrode.
6. the method preventing electric leakage of probe test carrier according to any one of claim 1-5, is characterized in that, described device under test comprises integrated circuit (IC)-components.
7. the method preventing electric leakage of probe test carrier according to claim 1, is characterized in that, described device under test comprises floating structural semiconductor device.
8. the method preventing electric leakage of probe test carrier according to claim 7, is characterized in that, described floating structural semiconductor device comprises SOI device, electrically programmable fuse and polysilicon gate.
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| CN106877945B (en) * | 2015-12-13 | 2021-06-22 | 航天信息股份有限公司 | Method for improving simulation test passing rate based on NFC Forum specification |
| CN107884693A (en) * | 2017-11-06 | 2018-04-06 | 武汉华星光电半导体显示技术有限公司 | Electrical characteristics test method |
| CN107833844B (en) * | 2017-11-21 | 2019-03-12 | 长江存储科技有限责任公司 | A method of it distinguishes and leaks electricity between PMOS grid and source-drain electrode or N trap |
| CN110261753A (en) * | 2019-05-06 | 2019-09-20 | 长江存储科技有限责任公司 | Semiconductor device failure analysis method |
| US20220381804A1 (en) * | 2021-05-26 | 2022-12-01 | Changxin Memory Technologies, Inc. | Sample fixation mechanism for test with nano-probe, apparatus for test and sample test method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1533804A1 (en) * | 2003-11-21 | 2005-05-25 | Pioneer Corporation | Recording / reproducing head, recording / reproducing head array, method of producing the same, and recording apparatus and reproducing apparatus |
| CN101551294A (en) * | 2009-04-30 | 2009-10-07 | 中国科学院上海技术物理研究所 | Method for detecting surface leakage channel of semiconductor detection device under illumination |
| CN103336150A (en) * | 2013-06-03 | 2013-10-02 | 上海华力微电子有限公司 | A method for improving the conductivity of an atomic force nanometer probe |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7735147B2 (en) * | 2005-10-13 | 2010-06-08 | The Regents Of The University Of California | Probe system comprising an electric-field-aligned probe tip and method for fabricating the same |
-
2013
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1533804A1 (en) * | 2003-11-21 | 2005-05-25 | Pioneer Corporation | Recording / reproducing head, recording / reproducing head array, method of producing the same, and recording apparatus and reproducing apparatus |
| CN101551294A (en) * | 2009-04-30 | 2009-10-07 | 中国科学院上海技术物理研究所 | Method for detecting surface leakage channel of semiconductor detection device under illumination |
| CN103336150A (en) * | 2013-06-03 | 2013-10-02 | 上海华力微电子有限公司 | A method for improving the conductivity of an atomic force nanometer probe |
Non-Patent Citations (1)
| Title |
|---|
| 纳米探针在超大规模集成电路可靠性和失效分析中的应用;章鸣;《中国优秀硕士学位论文全文数据库·信息科技辑》;20091215(第12期);I135-121 * |
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