CN103943609A - Structure for testing integrity of grid boundary oxide layer - Google Patents
Structure for testing integrity of grid boundary oxide layer Download PDFInfo
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- CN103943609A CN103943609A CN201410111307.9A CN201410111307A CN103943609A CN 103943609 A CN103943609 A CN 103943609A CN 201410111307 A CN201410111307 A CN 201410111307A CN 103943609 A CN103943609 A CN 103943609A
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- oxidation layer
- grid boundary
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- integrity test
- boundary oxidation
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Abstract
The invention provides a structure for testing integrity of a grid boundary oxide layer. The structure comprises a plurality of conductive strip-shaped parts arranged in parallel, and one ends of the conductive strip-shaped parts are electrically connected together. The structure for testing the integrity of the grid boundary oxide layer comprises contact holes formed in the conductive strip-shaped parts and communicated with source areas and drain areas on the two sides of a polycrystalline silicon grid electrode, and the contact holes are filled with conductive materials so that the conductive strip-shaped parts can be electrically connected with the source areas and the drain areas on the two sides of the polycrystalline silicon grid electrode respectively.
Description
Technical field
The present invention relates to semiconductor manufacturing tests field, more particularly, the present invention relates to a kind of novel grid boundary oxidation layer integrity test structure.
Background technology
While assessing gate oxide integrity (GOI) in semiconductor technology reliability at present, can the different test structures of design as Isolation Edge Block (Area), the defect that Isolation Edge Finger (STI edge) and Gate Edge Finger cause to detect different process process.（JP001.01）
Wherein grid border (Gate Edge Finger) GOI test structure object is the defect as polysilicon etching parameter, grid oxygen injury being formed in order to detect grid technique.Conventional grid border GOI test structure schematic diagram as depicted in figs. 1 and 2, wherein Fig. 2 is the sectional view of seeing along the arrow of Fig. 1.As depicted in figs. 1 and 2, generally design pectination polysilicon 1(poly finger) connect and drawn as high-pressure side by upper strata metal 2, draw as low-pressure end active area below grid oxygen in substrate 3, when test, adds accumulation mode (accumulation) voltage until grid oxygen punctures at high-pressure side.
Along with technique progress gate oxide thickness is more and more thinner, the test of the transoid of using instead (inversion) pattern causes under accumulation mode the electric leakage of grid oxygen increasing, is difficult to the instantaneous breakdown point of detecting grid oxygen, if can be introduced transoid parasitic capacitance, as shown in Figure 3, affect test result accuracy.Meanwhile, conventional structure is also difficult to detect as erosion
yield and integrity problem that the residual polycrystalline silicon that carving technology causes is introduced.
Summary of the invention
Technical problem to be solved by this invention is for there being above-mentioned defect in prior art, provide one can effectively measure super thin oxide layer moment breakdown characteristics, and can detect oxide layer defect that grid technique causes and the grid boundary oxidation layer integrity test structure of residual polycrystalline silicon problem simultaneously.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of grid boundary oxidation layer integrity test structure.Described grid boundary oxidation layer integrity test structure is electrically connected to the source and drain areas of polysilicon gate both sides; And make source and drain areas and substrate region all connect relative low voltage in the time of the integrity test of grid boundary oxidation layer, make polysilicon gate connect relatively high voltage.
Preferably, described grid boundary oxidation layer integrity test structure comprises: the multiple conduction stripes that are arranged in parallel, one end of wherein said multiple conduction stripes is electrically connected, and described grid boundary oxidation layer integrity test structure comprises the contact hole that the source and drain areas with polysilicon gate both sides that is formed in described multiple conduction stripes communicates, and in described contact hole, be filled with electric conducting material so that described multiple conduction strip portion is electrically connected with the source and drain areas of polysilicon gate both sides respectively.
Preferably, one end of described multiple conduction stripes is electrically connected by the conductive connection part being electrically connected with one end of described multiple conduction stripes.
Described grid boundary oxidation layer integrity test structure comprises pectination polysilicon gate, and described pectination polysilicon gate die opening is minimum design dimension.
The test structure of the present invention's design is arranged device source drain terminal is drawn by pectination contact hole; Meanwhile, can also ensure that finger gate finger spacing is minimum design dimension; Can detect the impact that grid etch process causes grid oxygen, detect the problem such as grid and source/leakage short circuit that grid technique residual polycrystalline silicon causes simultaneously.
Brief description of the drawings
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows according to the part schematic diagram of the conventional grid border GOI test structure of prior art.
Fig. 2 schematically shows according to the partial cross section figure of the conventional grid border GOI test structure of prior art.
Fig. 3 schematically shows according to the inversion mode stress schematic diagram of the conventional grid border GOI test structure of prior art.
Fig. 4 schematically shows grid boundary oxidation layer integrity test structure according to the preferred embodiment of the invention.
Fig. 5 schematically shows the sectional view of grid boundary oxidation layer integrity test structure according to the preferred embodiment of the invention.
Fig. 6 schematically shows the comparison of gate current curve under different stress conditions.
It should be noted that, accompanying drawing is used for illustrating the present invention, and unrestricted the present invention.Note, the accompanying drawing that represents structure may not be to draw in proportion.And in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Unlike the prior art, grid boundary oxidation layer integrity test structure of the present invention is electrically connected to the source and drain areas of polysilicon gate both sides, in the time of the integrity test of grid boundary oxidation layer, make source and drain areas and substrate region all connect relative low voltage (for example ground connection) like this, and make polysilicon gate connect relatively high voltage, thereby carry out the integrity test of grid boundary oxidation layer, super thin oxide layer moment breakdown characteristics can be effectively measured, and oxide layer defect that grid technique causes and residual polycrystalline silicon problem can be detected simultaneously.
Fig. 4 schematically shows grid boundary oxidation layer integrity test structure according to the preferred embodiment of the invention; Fig. 5 schematically shows the sectional view of grid boundary oxidation layer integrity test structure according to the preferred embodiment of the invention.Wherein, Fig. 5 is the sectional view of seeing along the arrow of Fig. 4.
Specifically, grid boundary oxidation layer integrity test structure comprises the multiple conduction stripes 10 that are arranged in parallel according to the preferred embodiment of the invention, one end of wherein said multiple conduction stripes 10 (is for example electrically connected, be electrically connected by the conductive connection part 12 being electrically connected with one end of described multiple conduction stripes 10), and described grid boundary oxidation layer integrity test structure comprises the contact hole 11 that the source and drain areas with polysilicon gate 1 both sides that is formed in described multiple conduction stripes 10 communicates, and in described contact hole 11, be filled with electric conducting material so that described multiple conduction stripes 10 is electrically connected with the source and drain areas of polysilicon gate 1 both sides respectively.
Preferably, described grid boundary oxidation layer integrity test structure comprises pectination polysilicon gate, and described pectination polysilicon gate die opening is minimum design dimension.Correspondingly, the distance between two conduction stripes depends on polysilicon gate die opening size.
The newly-designed grid boundary oxidation of the present invention layer integrity test structure, with pectination contact hole arrangement mode by source, grid two ends leak draw, ground connection in test process, when adding high pressure on grid (, higher than the voltage of earthed voltage), when substrate ground connection, the inversion regime parasitic capacitances that formed at grid oxygen interface by the many sons of substrate will be missed and disappear due to source, now just can test the real puncture voltage of gate oxide, the comparison of gate current curve under different stress conditions as shown in Figure 6, common inversion mode is difficult to detect normal breakdown characteristics, and after source leakage is drawn, can obviously detect instantaneous breakdown electrical voltage point.
Conventional structure does not have the size of specification finger gate finger spacing simultaneously, general spacing is not easy to occur residual polycrystalline silicon problem when larger, but the close quarters in side circuit application, this problem has very large possibility can affect yield and reliability, so new designing requirement finger gate finger spacing is minimum design dimension (minimum design rule), can effectively detect like this residual polycrystalline silicon problem.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the descriptions such as term " first " in specification, " second ", " the 3rd " are only for distinguishing each assembly, element, step of specification etc., instead of for representing logical relation or the ordinal relation etc. between each assembly, element, step.
Be understandable that, although the present invention discloses as above with preferred embodiment, but above-described embodiment is not in order to limit the present invention.For any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (4)
1. a grid boundary oxidation layer integrity test structure, is characterized in that described grid boundary oxidation layer integrity test structure is electrically connected to the source and drain areas of polysilicon gate both sides; And make source and drain areas connect relatively low voltage in the time of the integrity test of grid boundary oxidation layer, make polysilicon gate connect relatively high voltage.
2. grid boundary oxidation layer integrity test structure according to claim 1, it is characterized in that comprising: the multiple conduction stripes that are arranged in parallel, one end of wherein said multiple conduction stripes is electrically connected, and described grid boundary oxidation layer integrity test structure comprises the contact hole that the source and drain areas with polysilicon gate both sides that is formed in described multiple conduction stripes communicates, and in described contact hole, be filled with electric conducting material so that described multiple conduction strip portion is electrically connected with the source and drain areas of polysilicon gate both sides respectively.
3. grid boundary oxidation layer integrity test structure according to claim 2, is characterized in that, one end of described multiple conduction stripes is electrically connected by the conductive connection part being electrically connected with one end of described multiple conduction stripes.
4. grid boundary oxidation layer integrity test structure according to claim 1 and 2, is characterized in that, described grid boundary oxidation layer integrity test structure comprises pectination polysilicon gate, and described pectination polysilicon gate die opening is minimum design dimension.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410111307.9A CN103943609A (en) | 2014-03-24 | 2014-03-24 | Structure for testing integrity of grid boundary oxide layer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410111307.9A CN103943609A (en) | 2014-03-24 | 2014-03-24 | Structure for testing integrity of grid boundary oxide layer |
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| CN103943609A true CN103943609A (en) | 2014-07-23 |
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| CN201410111307.9A Pending CN103943609A (en) | 2014-03-24 | 2014-03-24 | Structure for testing integrity of grid boundary oxide layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107026099A (en) * | 2016-01-06 | 2017-08-08 | 格罗方德半导体公司 | Method for early detection TS to PC short circuit problems |
| CN110690195A (en) * | 2018-07-05 | 2020-01-14 | 中芯国际集成电路制造(上海)有限公司 | Test structure of semiconductor device and test method thereof |
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| US7088123B1 (en) * | 2005-08-31 | 2006-08-08 | Texas Instruments Incorporated | System and method for extraction of C-V characteristics of ultra-thin oxides |
| US20080309365A1 (en) * | 2007-06-14 | 2008-12-18 | Pei-Chun Liao | Method for Determining Time Dependent Dielectric Breakdown |
| CN102157496A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Contact hole test device and method for testing leakage current of grid by active area contact hole |
| CN103779326A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Goi test circuit structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7088123B1 (en) * | 2005-08-31 | 2006-08-08 | Texas Instruments Incorporated | System and method for extraction of C-V characteristics of ultra-thin oxides |
| US20080309365A1 (en) * | 2007-06-14 | 2008-12-18 | Pei-Chun Liao | Method for Determining Time Dependent Dielectric Breakdown |
| CN102157496A (en) * | 2010-02-12 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Contact hole test device and method for testing leakage current of grid by active area contact hole |
| CN103779326A (en) * | 2012-10-18 | 2014-05-07 | 中芯国际集成电路制造(上海)有限公司 | Goi test circuit structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107026099A (en) * | 2016-01-06 | 2017-08-08 | 格罗方德半导体公司 | Method for early detection TS to PC short circuit problems |
| US10451666B2 (en) | 2016-01-06 | 2019-10-22 | Globalfoundries Inc. | Methodology for early detection of TS to PC short issue |
| CN107026099B (en) * | 2016-01-06 | 2020-03-17 | 格罗方德半导体公司 | Method for early detection of TS-to-PC short circuit problem |
| CN110690195A (en) * | 2018-07-05 | 2020-01-14 | 中芯国际集成电路制造(上海)有限公司 | Test structure of semiconductor device and test method thereof |
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Application publication date: 20140723 |