CN107346752B - Semiconductor test structure, forming method thereof and test method - Google Patents
Semiconductor test structure, forming method thereof and test method Download PDFInfo
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- CN107346752B CN107346752B CN201610293060.6A CN201610293060A CN107346752B CN 107346752 B CN107346752 B CN 107346752B CN 201610293060 A CN201610293060 A CN 201610293060A CN 107346752 B CN107346752 B CN 107346752B
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Abstract
A semiconductor test structure, a method of forming the same and a method of testing the same, the semiconductor test structure comprising: a substrate having a well region therein; the grid structure array is positioned on the well region in the substrate, a source region is arranged in the well region on one side of each grid structure in the grid structure array, and a drain region is arranged in the well region on the other side of each grid structure in the grid structure array; the grid structure array comprises a plurality of layers of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure; and the dielectric layer is positioned between the antenna structures which are stacked in the plurality of layers and is used for electrically insulating the adjacent antenna structures. The semiconductor test structure provided by the invention can be applied to plasma damage test in a front-end process and can also be applied to dielectric layer damage test in a back-end process.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor test structure and a forming method and a test method thereof.
Background
In order to ensure the quality of semiconductor devices, various tests are required to be performed on the prepared wafers during the device fabrication process, including, for example, tests in the front-end process and tests in the back-end process.
PID (Plasma Induced damp) tests are typically required in front-end processes. In various fabrication processes in the front-end process, such as ion implantation, dry etching, chemical vapor deposition (cvd) process, and photoresist removal process, plasma (plasma) is generally used for the process. Plasma charges are introduced to the surface or the inside of a substrate or a semiconductor structure during plasma processing, and when the plasma charges are accumulated to a certain amount on the surface or the inside of the semiconductor structure, a discharge phenomenon is generated to generate plasma current, and the plasma current can break down a semiconductor device formed on the surface or the inside of the substrate, such as a gate oxide layer, an interlayer dielectric layer or a metal layer in an MOS transistor, so that the reliability of the semiconductor device is reduced, that is, plasma damage is caused, and the plasma damage is also called antenna effect (antenna effect). Therefore, determining which process the plasma damage originates from, and further avoiding the plasma damage becomes a key to solving the plasma damage problem.
In back-end processes, ild (inter Layer dielectric) testing is typically required. The ILD test includes electrical tests of metal lines of the same layer, electrical tests of metal lines of different layers, and electrical tests of Inter Metal Dielectrics (IMD).
In the prior art, a chip structure usually comprises a plurality of device layers, so that a plurality of test structures are required in the manufacturing process of a semiconductor device, and the dicing channels of a wafer are difficult to bear too many test structures.
To this end, it is desirable to provide a test structure that can be used for both front-end and back-end process testing.
Disclosure of Invention
The problem to be solved by the present invention is to provide a semiconductor test structure, a method for forming the same, and a method for testing the same, so that the semiconductor test structure can be applied to both front-end process testing and back-end process testing, and the semiconductor test structure satisfies different test requirements, thereby reducing the number of semiconductor test structures required on a wafer.
To solve the above problems, the present invention provides a semiconductor test structure, comprising: a substrate having a well region therein; the grid structure array is positioned on the well region in the substrate, a source region is arranged in the well region on one side of each grid structure in the grid structure array, and a drain region is arranged in the well region on the other side of each grid structure in the grid structure array; the grid structure array comprises a plurality of layers of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure; and the dielectric layer is positioned between the antenna structures which are stacked in the plurality of layers and is used for electrically insulating the adjacent antenna structures.
Optionally, the semiconductor test structure further includes: a first test pad electrically connected to the well region; a second test pad electrically connected to the source region; a third test pad electrically connected with the drain region.
Optionally, the semiconductor test structure further includes: the first top layer connecting layer is electrically connected with the well region and is electrically connected with the first test pad; a second top connection layer electrically connected to the source region, the second top connection layer being electrically connected to the second test pad; and the third top layer connecting layer is electrically connected with the drain region and is electrically connected with the third test pad.
Optionally, the semiconductor test structure further includes: the grid structure array comprises a grid structure array and an interconnection structure, wherein the interconnection structure is positioned above the grid structure array and comprises a plurality of conductive layers which are arranged in a stacked mode, and each grid structure in the grid structure array is electrically connected with one antenna structure through at least one conductive layer.
Optionally, the semiconductor test structure further includes: a fourth test pad electrically connected to the conductive layer, and different layers of the conductive layer are electrically connected to different fourth test pads.
Optionally, the conductive layer of the same layer includes a discrete sub-conductive layer, and the interconnect structure further includes: and the conductive plug is positioned between the sub-conductive layers of the adjacent layers and is used for realizing the electrical connection between the sub-conductive layers of the adjacent layers.
Optionally, the semiconductor test structure further includes: a number of interconnect lines, wherein the interconnect lines are for electrical connection between the conductive layer and the antenna structure.
Optionally, the antenna structure is rectangular in shape.
Optionally, the antenna structure is in the shape of a comb structure, and includes a comb handle portion and a discrete comb tooth portion connected to the comb handle portion.
Optionally, the antenna structure on the same layer includes a first comb structure and a second comb structure disposed opposite to the first comb structure, and the first comb structure and the second comb structure are insulated from each other, where the first comb structure includes a first comb handle portion and a discrete first comb tooth portion connected to the first comb handle portion, the second comb structure includes a second comb handle portion and a discrete second comb tooth portion connected to the second comb handle portion, the first comb tooth portion and the second comb tooth portion are embedded at intervals, and the first comb structure and the second comb structure on the same layer are electrically connected to different gate structures in the gate structure array, respectively.
Optionally, the antenna structures on different layers include a plurality of layers of antenna structures electrically connected through an antenna plug, and the electrically connected antenna structures are electrically connected to the same gate structure.
Optionally, the antenna structures on different layers include N layers of antenna structures electrically connected through an antenna plug, and the N layers of electrically connected antenna structures are electrically connected to the same gate structure, where N is greater than or equal to 2.
Optionally, when the antenna connection structure on the same layer includes a first comb structure and a second comb structure disposed opposite to the first comb structure, the antenna plug is electrically connected to the first comb portion of the antenna structure on different layers; or the antenna plug is electrically connected with the second comb tooth part of the antenna structure of different layers.
Optionally, the antenna structure is made of polysilicon or metal.
The invention also provides a method for forming the semiconductor test structure, which comprises the following steps: providing a substrate, wherein a well region is formed in the substrate; forming a grid structure array on the well region in the substrate; forming a source region in the well region on one side of each gate structure in the gate structure array, and forming a drain region in the well region on the other side of each gate structure in the gate structure array; forming a plurality of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure; a dielectric layer is formed between the antenna structures for electrical insulation between adjacent antenna structures.
The invention also provides a test method, which comprises the following steps: providing the semiconductor test structure; applying a first bias voltage to at least one grid structure in the grid structure array to enable the source region, the drain region and the well region to be grounded and obtain grid current of the grid structure; applying a second bias voltage to at least one grid structure in the grid structure array, and applying a third bias voltage to the drain region, so that the source region and the well region are grounded, and the threshold voltage of the grid structure is obtained; and applying a fourth bias voltage to any two antenna structures in the stacked antenna structures to obtain the breakdown voltage between the two antenna structures.
Optionally, the test method includes: and applying a fourth bias voltage to adjacent antenna structures in the stacked antenna structures to obtain the breakdown voltage between the adjacent antenna structures.
Optionally, the method for obtaining the breakdown voltage between the antenna structures of adjacent layers includes: applying a fourth bias voltage to two gate structures electrically connected to the adjacent layer antenna structure; and changing the magnitude of the fourth bias voltage until the antenna structure breaks down, wherein the fourth bias voltage when the antenna structure breaks down is breakdown voltage.
Optionally, the testing method further includes: the antenna structure of the same layer comprises a first comb-shaped structure and a second comb-shaped structure opposite to the first comb-shaped structure; applying a fourth bias voltage to the first comb-shaped structure and the second comb-shaped structure of the same layer; and acquiring the breakdown voltage between the first comb-shaped structure and the second comb-shaped structure in the same layer.
Optionally, the testing method further includes: the antenna structures on different layers comprise a plurality of layers of antenna structures which are electrically connected through antenna plugs, and the electrically connected antenna structures are electrically connected with the same grid structure; and applying a fourth bias voltage to the antenna structure electrically connected with the antenna plug and the adjacent antenna structure electrically insulated from the antenna plug, and acquiring the breakdown voltage between the two antenna structures.
Optionally, in the process of obtaining the gate current of the gate structure, the fourth test pad is connected to a first bias voltage, and the first test pad, the second test pad, and the third test pad are grounded; in the process of obtaining the threshold voltage of the gate structure, the fourth test pad is connected with the second bias voltage, the third test pad is connected with the third bias voltage, and the first test pad and the second test pad are grounded.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the technical scheme of the semiconductor test structure provided by the invention comprises a plurality of layers of antenna structures which are arranged in a stacked mode, and each grid structure in the grid structure array is electrically connected with at least one layer of antenna structure. In the front-end process, the antenna structure collects plasma charges in the process, so that the antenna structure can be applied to detecting process damage on a grid structure connected with the antenna structure; in the back-end process, by applying bias voltage to at least two antenna structures, the breakdown voltage between the two antenna structures can be obtained, and further the process damage degree of a dielectric layer between the two antenna structures is obtained. Therefore, the semiconductor test structure provided by the invention can be applied to front-end process detection and back-end process detection, and the number of test structures required in the semiconductor production process is reduced.
Furthermore, the semiconductor test structure also comprises a first test pad electrically connected with the well region, so that bias voltage can be applied to the well region by applying bias voltage to the first test pad; a second test pad electrically connected to the source region, the second test pad being biased to apply a bias voltage to the source region; and a third test pad electrically connected to the drain region, the third test pad being biased to apply a bias voltage to the drain region.
Furthermore, the antenna structure is rectangular, and the process damage degree of the deposition process for forming the antenna structure to the dielectric layer between the adjacent antenna structures can be obtained by applying bias to the adjacent antenna structures to obtain the breakdown voltage.
Furthermore, the antenna structure is in a comb-shaped structure, and the breakdown voltage is obtained by applying bias to the adjacent antenna structures, so that the process damage degree of the deposition process for forming the antenna structure and the process damage degree of the etching process to the dielectric layer between the adjacent antenna structures can be obtained.
Further, the antenna structure on the same layer includes a first comb-shaped structure and a second comb-shaped structure which are electrically insulated from each other, and the breakdown voltage is obtained by applying bias to the first comb-shaped structure and the second comb-shaped structure on the same layer, so that the process damage degree of the deposition process and the etching process for forming the antenna structure on the same layer to the dielectric layer between the antenna structures on the same layer can be obtained.
Furthermore, the antenna structures of different layers further comprise N layers of antenna structures electrically connected through antenna plugs, and the damage degree of the etching process for forming the antenna plugs on the dielectric layer can be obtained by applying bias voltage to the antenna structures electrically connected with the antenna plugs and the antenna structures electrically insulated from the antenna plugs to obtain breakdown voltage.
According to the technical scheme of the testing method, the damage degree of the grid structure caused by the plasma process can be obtained by obtaining the grid current and the threshold voltage of the grid structure; and applying a fourth bias voltage to any two antenna structures in the stacked antenna structures to obtain the breakdown voltage between the two antenna structures, so that the damage degree of the process to the dielectric layer between the two antenna structures can be obtained. Therefore, the testing method provided by the invention can test both the front-end process and the back-end process.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams of a semiconductor test structure according to an embodiment of the present invention;
FIG. 4 is a schematic top view of the area A in FIG. 1 according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view taken along AA1 in FIG. 4;
FIG. 6 is a schematic top view of the area A in FIG. 1 according to another embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view taken along the direction BB1 in FIG. 6;
FIG. 8 is a schematic top view of the area A in FIG. 1 according to another embodiment of the present invention;
fig. 9 is a schematic cross-sectional view taken along direction CC1 in fig. 8.
Detailed Description
As can be seen from the background art, in the prior art, a lot of test structures are required in the manufacturing process of semiconductor devices, and it is difficult to bear too many test structures on the scribe lines of the wafer.
In order to perform PID testing, PID test structures are usually required to be arranged on scribe lines of a wafer, ILD test structures are required to be arranged on scribe lines of the wafer in order to perform ILD testing, the number of the PID test structures arranged in the wafer is determined according to the number of device layers included in a chip structure in the wafer and the type of a field effect transistor included in each device layer, and the number of the ILD test structures arranged is determined according to the number of device layers included in the chip structure in the wafer. In order to complete the PID test and the ILD test, more test structures are needed in the manufacturing process of the semiconductor device, and excessive test structures are difficult to bear on the cutting lines of the wafer.
In order to solve the above problems, the present invention provides a semiconductor test structure, which includes a substrate having a well region therein; the grid structure array is positioned on the well region in the substrate, a source region is arranged in the well region on one side of each grid structure in the grid structure array, and a drain region is arranged in the well region on the other side of each grid structure in the grid structure array; the grid structure array comprises a plurality of layers of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure; and the dielectric layer is positioned between the antenna structures which are stacked in the plurality of layers and is used for electrically insulating the adjacent antenna structures.
In the front-end process, the antenna structure collects plasma charges in the process, so that the antenna structure can be applied to detecting process damage on a grid structure connected with the antenna structure; in the back-end process, by applying bias voltage to at least two antenna structures, the breakdown voltage between the two antenna structures can be obtained, and further the process damage degree of a dielectric layer between the two antenna structures is obtained. Therefore, the semiconductor test structure provided by the invention can be applied to front-end process detection and back-end process detection, and the number of test structures required in the semiconductor production process is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to fig. 3 are schematic structural diagrams of a semiconductor test structure according to an embodiment of the present invention.
Fig. 1 is a schematic top view of the semiconductor test structure provided in this embodiment, fig. 2 is a schematic cross-sectional structure along XX1 in fig. 1, and fig. 3 is a schematic cross-sectional structure along YY1 in fig. 1. It should be noted that, for convenience of illustration and description, not all features of the cross-section of fig. 1 are shown in fig. 2 and 3.
Referring to fig. 1 to 3, the semiconductor test structure includes:
a substrate 200, wherein the substrate 200 is provided with a well region 201;
a gate structure array located on the surface of the well region 201 in the substrate 200, wherein the well region 201 on one side of each gate structure 202 in the gate structure array has a source region (not labeled), and the well region 201 on the other side of each gate structure 202 in the gate structure array has a drain region (not labeled);
a plurality of layers of antenna structures 203 arranged in a stacked manner, wherein each gate structure 202 in the gate structure array is electrically connected with at least one layer of antenna structure 203;
and the dielectric layer 204 is positioned between the plurality of layers of stacked antenna structures 203, and the dielectric layer 204 is used for electrical insulation between the adjacent antenna structures 203.
The semiconductor test structure provided by the present embodiment will be described in detail below with reference to the accompanying drawings.
The substrate 200 is a wafer for forming a chip or a semiconductor device, and the substrate 200 includes a plurality of chip regions (die) and scribe line regions between adjacent chip regions. In this embodiment, the antenna structure 203 is located in the scribe line region of the substrate 200. The substrate 200 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. The substrate 200 may also be a silicon-on-insulator substrate.
The surface of the well region 201 is used for arranging a gate structure array, P-type ions or N-type ions are doped in the well region 201, and the type of the doped ions in the well region 201 is opposite to that of the doped ions in the source region or the drain region on two sides of the gate structure 202. In an embodiment, the doped ions of the well region 201 are P-type ions, and the doped ions of the source region and the drain region are N-type ions; in another embodiment, the doped ions of the well region 201 are N-type ions, and the doped ions of the source region and the drain region are P-type ions.
In this embodiment, the gate structures 202 in the gate structure array are arranged in parallel, and the pattern of the gate structures 202 projected on the surface of the substrate 200 is a stripe pattern. In this embodiment, the semiconductor test structure can be used to detect plasma damage in a plurality of gate structures 202, the number of gate structures 202 in the gate structure array is 1-19, and for convenience of illustration and description, 4 gate structures 202 are shown in fig. 1 as an example.
In order to more effectively utilize the space of the substrate 200, the source region or the drain region is shared between adjacent gate structures 202, and a transistor is formed between each gate structure 202 and the source region and the drain region on both sides of the gate structure. In this embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer on a top surface of the gate dielectric layer. In other embodiments, the gate structure may further include a sidewall spacer on a surface of a sidewall of the gate dielectric layer and a surface of a sidewall of the gate electrode layer.
In this embodiment, in order to apply a bias voltage to the gate structure 202, the well 201, the source region and the drain region, the semiconductor test structure further includes: a first test pad 211, the first test pad 211 being electrically connected to the well region 201; a second test pad 212, the second test pad 212 being electrically connected with the source region; a third test pad 213, the third test pad 213 being electrically connected to the drain region. During testing, a bias voltage is applied to the well region 201 by applying a bias voltage to the first test pad 211, a bias voltage is applied to the source region by applying a bias voltage to the second test pad 212, and a bias voltage is applied to the drain region by applying a bias voltage to the third test pad 213.
The semiconductor test structure further comprises: a first top connection layer 221 electrically connected to the well 201, the first top connection layer 221 being electrically connected to the first test pad 211; a second top connection layer 222 electrically connected to the source region, the second top connection layer 222 being electrically connected to the second test pad 212; a third top connection layer 223 electrically connected to the drain region, the third top connection layer 223 being electrically connected to the third test pad 213. The first top connection layer 221, the second top connection layer 222, and the third top connection layer 223 are in the same layer. Specifically, the well region 201 and the first top connection layer 221 are electrically connected through a first plug 231; the source region is electrically connected with the second top connection layer 222 through a second plug 232; the drain region is electrically connected to the third top connection layer 223 through the third plug 233.
In this embodiment, the source regions on both sides of each gate structure 202 are electrically connected to the second top connection layer 222, so that the source regions on both sides of each gate structure 202 are electrically connected to the same second test pad 212; the drain regions on both sides of each gate structure 202 are electrically connected to the third top connection layer 223, so that the drain regions on both sides of each gate structure 202 are electrically connected to the same third test pad 213.
The semiconductor test structure further comprises: and the interconnection structure is positioned above the grid structure array and comprises a plurality of conductive layers 301 which are arranged in a stacked mode, wherein each grid structure 202 in the grid structure array is electrically connected with one antenna structure through at least one conductive layer 301.
The number of layers of the conductive layer 301 in the interconnection structure is determined according to the number of the gate structures 202 in the gate structure array to be detected, and the number of layers of the conductive layer 301 is at least equal to the number of the gate structures 202 in the gate structure array. In this embodiment, the conductive layer 301 is in the shape of a strip. The conductive layer 301 on the same layer includes separate sub-conductive layers, wherein the arrangement direction of the separate sub-conductive layers is the same as the arrangement direction of the gate structure 202, and the sub-conductive layers are strip-shaped. The sub-conductive layers are separated from each other, and each gate structure 202 is connected to at least one sub-conductive layer of the conductive layer 301, so that no electrical connection occurs between the gate structures 202.
The semiconductor test structure further comprises a gate plug 302 located on the top surface of the gate structure 202, and electrically connected to the conductive layer 301 through the gate plug 302.
The interconnect structure further comprises: and the conductive plug 303 is positioned between the adjacent sub-conductive layers, and the conductive plug 303 is used for realizing the electrical connection between the sub-conductive layers of the adjacent layers. Thereby electrically connecting each gate structure 202 with a sub-conductive layer in a different layer of the conductive layer 301. The following description will be given by taking an example that the gate structure array includes a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, the interconnect structure includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer from bottom to top, where each conductive layer includes 4 discrete sub-conductive layers, which are the first sub-conductive layer, the second sub-conductive layer, the third sub-conductive layer, and the fourth sub-conductive layer, and the connection manner of the gate structure 202 and the conductive layer 301 is as follows:
the first grid structure is electrically connected with the first sub-conducting layer in the first conducting layer through the grid plug; the second gate structure is electrically connected with the second sub-conductive layer in the second conductive layer through the gate plug, and a connection path of the second gate structure and the second sub-conductive layer in the second conductive layer includes: the grid plug, the second sub-conducting layer in the first conducting layer, the conducting plug positioned on the surface of the second sub-conducting layer in the first conducting layer and the second sub-conducting layer in the second conducting layer are electrically connected; in turn, the fourth gate structure is electrically connected to the fourth sub-conductive layer in the fourth conductive layer through the gate plug, and a connection path between the fourth gate structure and the fourth sub-conductive layer in the fourth conductive layer includes: the gate plug, the fourth sub-conductive layer in the first conductive layer, the conductive plug located on the surface of the fourth sub-conductive layer in the first conductive layer, the fourth sub-conductive layer in the second conductive layer, the conductive plug located on the surface of the fourth sub-conductive layer in the second conductive layer, the fourth sub-conductive layer in the third conductive layer, and the conductive plug located on the surface of the fourth sub-conductive layer in the third conductive layer.
The interconnect structure further comprises: an insulating layer 312 between adjacent conductive layers 301, the insulating layer 312 for electrical insulation between adjacent conductive layers 301.
The semiconductor test structure further comprises: a fourth test pad 214, the fourth test pad 214 being electrically connected with the conductive layer 301, and the conductive layer 301 of a different layer being electrically connected with a different fourth test pad 214. Subsequently, during the testing of the semiconductor test structure, a bias voltage is applied to the corresponding gate structure 202 by applying a bias voltage to the fourth test pad 214.
The interconnect structure further comprises an insulating layer 312 between adjacent conductive layers 301, the insulating layer 312 being used for electrical insulation between adjacent conductive layers 301. The insulating layer 312 is made of silicon oxide, silicon nitride, or silicon oxynitride.
The semiconductor test structure further comprises: a number of interconnect lines 401, the interconnect lines 401 being used to enable electrical connection between the conductive layer 301 and the antenna structure 203.
In this embodiment, the interconnection lines 401 are arranged in parallel, each interconnection line 401 is electrically connected to at least one conductive layer 301, and each interconnection line 401 is further electrically connected to at least one antenna structure 203, so that each gate structure 201 is correspondingly electrically connected to one antenna structure 203.
The material of the antenna structure 203 is polysilicon or metal, such as copper, aluminum or tungsten. In the front-end process, the antenna structure 203 is configured to collect plasma charges in the process, and the plasma damage degree of the corresponding process can be obtained by testing the threshold voltage and the gate current of the transistor corresponding to the gate structure 202 electrically connected to the antenna structure 203 and comparing the measured threshold voltage or gate current with a standard value. In this embodiment, the antenna structure 203 includes a plurality of stacked antenna structures, each antenna structure 203 can absorb plasma charges in a certain process, so that each gate structure 202 and the antenna structure electrically connected to the gate structure 202 can form an independent plasma detection structure, and the plasma detection structure can be used for detecting plasma damage in a corresponding process.
In the back-end process, damage caused by the process to the dielectric layer 204 between different antenna structures 203 can also be obtained by detecting breakdown voltages between different antenna structures 203.
The antenna structure 203 provided in the present embodiment will be described in detail below with reference to the drawings, taking the number of layers of the antenna structure 203 as an example of 6.
Fig. 4 is a schematic top view of the area a in fig. 1 according to an embodiment, and fig. 5 is a schematic cross-sectional view along the AA1 direction in fig. 4.
Referring to fig. 4 and 5, the antenna structure 203 is rectangular in shape. Each of the antenna structures 203 is electrically connected to a corresponding one of the fourth test pads 214 (refer to fig. 1) through a conductive layer.
In one embodiment, the antenna structures 203 of adjacent layers are electrically isolated, and specifically, the antenna structures 203 of adjacent layers are electrically isolated by the dielectric layer 204. When the semiconductor test structure is tested, by applying bias to the antenna structures 203 of adjacent layers, the breakdown voltage between the antenna structures 203 of adjacent layers is obtained, so that the damage degree of the process to the dielectric layer 204 between the antenna structures 203 of adjacent layers is obtained. Alternatively, by applying a bias voltage to any two antenna structures 203, the breakdown voltage between the two antenna structures 203 is obtained, so as to obtain the damage degree of the process to the dielectric layer 204 between the two antenna structures 203. Specifically, the damage of the dielectric layer 204 caused by plasma in the process of depositing the antenna structure 203 is obtained.
In another embodiment, the antenna structures 203 of different layers include N layers of antenna structures 203 electrically connected through the antenna plugs 401, where N is greater than or equal to 2, and the electrically connected N layers of antenna structures 203 are electrically connected to the same gate structure 202 (refer to fig. 1 to 3), so as to avoid a problem of a detection structure deviation caused by the electrically connected N layers of antenna structures 203 being electrically connected to different gate structures 202. In an embodiment, taking N as 2, the two layers of antenna structures 203 are electrically connected through the antenna plug 401. When the semiconductor test structure is tested, by applying bias to the antenna structure 203 electrically connected with the antenna plug 401 and the antenna structure 203 electrically insulated from the antenna plug 401, the breakdown voltage between the two antenna structures 203 electrically connected with the antenna plug 401 and electrically insulated from the antenna plug 401 is obtained, so that the damage degree of the dielectric layer 204 caused by the process for forming the antenna plug 401 is obtained.
Fig. 6 is a schematic top view of the area a in fig. 1 according to another embodiment of the present invention, and fig. 7 is a schematic cross-sectional view along the BB1 direction in fig. 6.
Referring to fig. 6 and 7, the antenna structure 203 is in the shape of a comb structure, and includes a comb handle portion 10 and a discrete comb tooth portion 11 connected to the comb handle portion 10. Each of the antenna structures 203 is electrically connected to a corresponding one of the fourth test pads 214 (refer to fig. 1) through a conductive layer 301.
In one embodiment, the antenna structures 203 of adjacent layers are electrically isolated from each other. When the semiconductor test structure is tested, applying bias voltage to the antenna structures 203 of adjacent layers to obtain the breakdown voltage between the antenna structures 203 of adjacent layers; alternatively, the breakdown voltage between any two antenna structures 203 is obtained by applying a bias voltage to the two antenna structures 203. And then the damage degree of the dielectric layer 204 between the two antenna structures 203 caused by the process is obtained. Specifically, the damage to the dielectric layer 204 caused by the etching process used for forming the antenna structure 203 is obtained.
In another embodiment, the antenna structures 203 of different layers include N layers of antenna structures 203 electrically connected through antenna plugs 401, where the antenna plugs 401 connect the comb-shaped handle portions 10 of the antenna structures 203 of different layers, or the antenna plugs 401 connect the comb-shaped tooth portions 11 of the antenna structures 203 of different layers. Wherein N is greater than or equal to 2, and the electrically connected N-layer antenna structures 203 are electrically connected to the same gate structure 202 (refer to fig. 1 to 3). In an embodiment, taking N as 2, the two layers of antenna structures 203 are electrically connected through the antenna plug 401. When the semiconductor test structure is tested, bias voltage is applied to the antenna structure 203 electrically connected with the antenna plug 401 and the antenna structure 203 electrically insulated from the antenna plug 401, so that breakdown voltage between the two antenna structures 203 is obtained, and thus the damage degree of the process for forming the antenna plug 401 to the dielectric layer 204 is obtained. Specifically, the damage of the dielectric layer 204 caused by the plasma in the etching process for forming the antenna plug 401 is obtained.
Fig. 8 is a schematic top view of the region a in fig. 1 according to another embodiment of the present invention, and fig. 9 is a schematic cross-sectional view taken along a direction CC1 in fig. 8.
Referring to fig. 8 and 9, the antenna structure 203 on the same layer includes a first comb structure (not shown) and a second comb structure (not shown) disposed opposite to the first comb structure, the first comb structure and the second comb structure being insulated from each other, wherein the first comb structure includes a first comb handle portion 21 and a first discrete comb tooth portion 22 connected to the first comb handle portion 21, the second comb structure includes a second comb handle portion 23 and a second discrete comb tooth portion 24 connected to the second comb handle portion, and the first comb tooth portion 22 and the second comb tooth portion 24 are disposed in a spaced-embedded manner. And the first comb-like structure and the second comb-like structure of the same layer are respectively and electrically connected with different gate structures 202 in the gate structure array, specifically, the first comb-like structure and the second comb-like structure are respectively and electrically connected with the discrete sub-conductive layers in the conductive layer of the same layer through interconnection lines.
The first and second comb handle portions 21 and 23 are parallel to each other. The first and second comb structures of the same layer are electrically connected to different fourth test pads 214 through separate sub-conductive layers in the conductive layer of the same layer. When the number of the antenna structures 203 is 6, the stacked antenna structures 203 may be electrically connected to 12 gate structures 202.
When the semiconductor test structure is tested, a breakdown voltage between the first comb-shaped structure and the second comb-shaped structure at the same layer is obtained by applying bias to the first comb-shaped structure and the second comb-shaped structure at the same layer, so that the damage degree of the process for forming the first comb-shaped structure and the second comb-shaped structure to the dielectric layer 204 is obtained.
In another embodiment, when the antenna structure 203 of the same layer includes a first comb structure and the first comb structure, the antenna structure 203 of a different layer includes N layers of antenna structures 203 electrically connected through an antenna plug (not shown), and the electrically connected N layers of antenna structures 203 are electrically connected to the same gate structure 202, where N is greater than or equal to 2. The antenna plug is electrically connected with the first comb-tooth part 22 of the antenna structure 203 of different layers; alternatively, the antenna plug is electrically connected to the second comb-tooth portion 24 of the antenna structure 203 of the different layer.
The dielectric layer 204 plays a role of electrically insulating different antenna structures 203, and the material of the dielectric layer 204 is silicon oxide, silicon nitride or silicon oxynitride.
As can be seen from the foregoing analysis, in the semiconductor test structure provided in this embodiment, the damage degree of the gate structure caused by the plasma process can be tested, the damage degree of the dielectric layer between the antenna structures of different layers caused by the back-end process can be tested, the damage degree of the dielectric layer between the antenna structures of the same layer caused by the back-end process can be tested, and the number of semiconductor test structures required in the semiconductor manufacturing process is reduced.
Correspondingly, the invention also provides a method for forming the semiconductor test structure, which comprises the following steps: providing a substrate, wherein a well region is formed in the substrate; forming a grid structure array on the well region in the substrate, wherein the grid structure array comprises a plurality of grid structures which are arranged in parallel; forming a source region in the well region on one side of each gate structure in the gate structure array, and forming a drain region in the well region on the other side of each gate structure in the gate structure array; forming a plurality of layers of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure; a dielectric layer is formed between the antenna structures for electrical insulation between adjacent antenna structures.
The invention also provides a test method, which comprises the following steps:
referring to fig. 1 to 8, the semiconductor test structure is provided;
applying a first bias voltage to at least one gate structure 202 in the gate structure array to ground the source region, the drain region and the well region 201, thereby obtaining a gate current of the gate structure 202;
applying a second bias voltage to at least one gate structure 202 in the gate structure array, and applying a third bias voltage to the drain region, so that both the source region and the well region 201 are grounded, and a threshold voltage of the gate structure 202 is obtained;
applying a fourth bias voltage between any two antenna structures 203 of the stacked antenna structures 203 to obtain a breakdown voltage between the two antenna structures.
The test method provided in this embodiment will be described in detail below.
The antenna structure 203 is used for collecting plasma charges in a process, and the plasma damage degree of the corresponding process can be obtained by testing the threshold voltage and the gate current of the transistor and comparing the measured threshold voltage or the measured gate current with a standard value.
Specifically, a first bias voltage is applied to the fourth test pad 214, that is, the first bias voltage is applied to the gate structure 202 electrically connected to the fourth test pad 214, so that the first test pad 211, the second test pad 212, and the third test pad 213 are all grounded, that is, the well region 201, the source region, and the drain region are all grounded, and the gate current of the gate structure 202 is obtained. By adjusting the first bias voltage, a first bias voltage can be applied to the gate electrode layer corresponding to the gate structure 202, and the gate current of the gate structure 202 can be obtained by testing the current generated by the gate electrode layer after the first bias voltage is applied. With the change of the first bias voltage, the gate current changes correspondingly, and by judging the change trend of the gate current, the damage degree of the plasma charges collected by the antenna structure 203 connected with the gate structure 202 to the semiconductor device can be obtained.
A second bias voltage is applied to the fourth test pad 214, i.e. to the gate structure 202 electrically connected to the fourth test pad 214, and a third bias voltage is applied to the third test pad 213, i.e. to the drain region, so that the first test pad 211 and the second test pad 212 are both grounded, i.e. the well region 201 and the source region are both grounded. Changing the magnitude of the second bias voltage until the channel region at the bottom of the gate structure 202 is turned on, that is, a drain saturation current is generated between the well region 201 and the source region, the channel region between the source region and the drain region is reversely conducted, and the second bias voltage for turning on the channel region of the gate structure 202 is the threshold voltage of the gate structure 202. By interpreting the threshold voltage for opening the channel region of the gate structure 202, the damage degree of the plasma charges collected by the antenna structure 203 connected to the gate structure 202 to the semiconductor device can be obtained.
When the semiconductor test structure is applied to a back-end-of-line test, the fourth bias is applied to any two antenna structures 203 by applying the fourth bias to two gate structures 202 electrically connected to the antenna structures 203, that is, applying the fourth bias to two fourth test pads 214 electrically connected to the two gate structures 202. A test method for testing the different shapes of the stacked antenna structure 203 will be described below with reference to the drawings.
Referring to fig. 4 and 5, the antenna structure 203 is rectangular.
The testing method comprises the step of applying a fourth bias voltage to adjacent layer antenna structures 203 in the stacked antenna structures 203 to obtain the breakdown voltage between the adjacent layer antenna structures 203. Specifically, the tested antenna structure 203 is a block structure, and the damage degree of the deposition process for forming the antenna structure 203 to the dielectric layer 204 between the antenna structures 203 can be tested.
In a specific embodiment, the method for obtaining the breakdown voltage between the antenna structures 203 of adjacent layers includes: applying a fourth bias to two gate structures 202 electrically connected to the adjacent tier antenna structure 203; changing the magnitude of the fourth bias voltage until the antenna structure 203 breaks down, wherein the fourth bias voltage when the break down occurs is a breakdown voltage.
Referring to fig. 4 and 5, when the antenna structures 203 of different layers include N layers of antenna structures 204 electrically connected through the antenna plugs 401, the electrically connected antenna structures 203 of several layers are electrically connected to the same gate structure 202; applying a fourth bias to the antenna structure 203 electrically connected to the antenna plug 401 and the adjacent antenna structure 203 electrically insulated from the antenna plug 401, obtains a breakdown voltage between the two antenna structures 203. By obtaining the breakdown voltage between the two antenna structures 203, the damage degree of the dielectric layer 204 caused by the process of forming the antenna plug 401, for example, the damage degree of the dielectric layer 204 caused by the etching process and the deposition process in the process of forming the antenna plug 401, can be obtained.
Referring to fig. 6 and 7, when the antenna structures 203 are comb-shaped structures, and the antenna structures 203 include comb handle portions 10 and separate comb tooth portions 11 connected to the comb handle portions 10, the testing method includes applying a fourth bias voltage to adjacent antenna structures 203 in the stacked antenna structures 203, and obtaining a breakdown voltage between the adjacent antenna structures 203. Specifically, the tested antenna structure 203 is a block structure, and the damage degree of the deposition process and the etching process for forming the antenna structure 203 to the dielectric layer 204 between the antenna structures 203 can be tested.
Referring to fig. 6 and 7, the antenna structures 203 of different layers include N layers of antenna structures 203 electrically connected through antenna plugs 401, and the antenna plugs 401 are connected to the comb-shaped handle portions 10 of the antenna structures 203 of different layers, or when the antenna plugs 401 are connected to the comb-shaped tooth portions 11 of the antenna structures 203 of different layers, a fourth bias is applied to the antenna structure 203 electrically connected to the antenna plug 401 and the adjacent antenna structure 203 electrically insulated from the antenna plug 401, so as to obtain a breakdown voltage between the two antenna structures 203. By obtaining the breakdown voltage, a damage degree of the dielectric layer 204 caused by an etching process or a deposition process in the process of forming the antenna plug 401 is obtained.
Referring to fig. 8 and 9, the antenna structure 203 on the same layer includes a first comb structure (not shown) and a second comb structure (not shown) disposed opposite to the first comb structure, the first comb structure and the second comb structure being insulated from each other, wherein the first comb structure includes a first comb handle portion 21 and a first discrete comb tooth portion 22 connected to the first comb handle portion 21, the second comb structure includes a second comb handle portion 23 and a second discrete comb tooth portion 24 connected to the second comb handle portion, and the first comb tooth portion 22 and the second comb tooth portion 24 are disposed in a spaced-embedded manner.
The test method comprises the following steps: applying a fourth bias voltage to the first comb-shaped structure and the second comb-shaped structure of the same layer; and acquiring the breakdown voltage between the first comb-shaped structure and the second comb-shaped structure in the same layer. By obtaining the breakdown voltage, the damage degree of the dielectric layer 204 caused by a deposition process or an etching process in the process of forming the first comb-shaped structure and the second comb-shaped structure can be obtained.
In another embodiment, when the antenna structure 203 of the same layer includes a first comb structure and a second comb structure electrically insulated from the first comb structure, the antenna structure 203 of the different layer includes N layers of antenna structures 203 electrically connected through an antenna plug (not shown), and the electrically connected N layers of antenna structures 203 are electrically connected to the same gate structure 202, where N is greater than or equal to 2. The antenna plug is electrically connected with the first comb-tooth part 22 of the antenna structure 203 of different layers; alternatively, the antenna plug is electrically connected to the second comb-tooth portion 24 of the antenna structure 203 of the different layer. The test method comprises the following steps: applying a fourth bias to the antenna structure 203 electrically connected to the antenna plug and the adjacent antenna structure 203 electrically insulated from the antenna plug, a breakdown voltage between the two antenna structures 203 is obtained. By obtaining the breakdown voltage, the damage degree of the dielectric layer 204 caused by the etching process or the deposition process for forming the antenna plug is obtained.
In the testing method provided by the embodiment, the damage degree of the gate structure caused by the plasma process can be obtained by obtaining the gate current and the threshold voltage of the gate structure; and applying a fourth bias voltage to any two antenna structures in the stacked antenna structures to obtain the breakdown voltage between the two antenna structures, so that the damage degree of the process to the dielectric layer between the two antenna structures can be obtained. Therefore, the testing method provided by the embodiment can test both the front-end process and the back-end process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A semiconductor test structure, comprising:
a substrate having a well region therein;
the grid structure array is positioned on the well region in the substrate, a source region is arranged in the well region on one side of each grid structure in the grid structure array, and a drain region is arranged in the well region on the other side of each grid structure in the grid structure array;
the grid structure array comprises a plurality of layers of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure;
the dielectric layer is positioned between the plurality of layers of antenna structures which are arranged in a stacked mode and is used for electrically insulating the adjacent antenna structures;
the antenna structure on the same layer comprises a first comb-shaped structure and a second comb-shaped structure arranged opposite to the first comb-shaped structure, the first comb-shaped structure and the second comb-shaped structure are insulated from each other, the first comb-shaped structure comprises a first comb handle part and a discrete first comb tooth part connected with the first comb handle part, the second comb-shaped structure comprises a second comb handle part and a discrete second comb tooth part connected with the second comb handle part, the first comb tooth part and the second comb tooth part are distributed in an embedded mode at intervals, and the first comb-shaped structure and the second comb-shaped structure on the same layer are respectively electrically connected with different grid structures in a grid structure array.
2. The semiconductor test structure of claim 1, wherein the semiconductor test structure further comprises: a first test pad electrically connected to the well region; a second test pad electrically connected to the source region; a third test pad electrically connected with the drain region.
3. The semiconductor test structure of claim 2, wherein the semiconductor test structure further comprises: the first top layer connecting layer is electrically connected with the well region and is electrically connected with the first test pad; a second top connection layer electrically connected to the source region, the second top connection layer being electrically connected to the second test pad; and the third top layer connecting layer is electrically connected with the drain region and is electrically connected with the third test pad.
4. The semiconductor test structure of claim 1, wherein the semiconductor test structure further comprises: the grid structure array comprises a grid structure array and an interconnection structure, wherein the interconnection structure is positioned above the grid structure array and comprises a plurality of conductive layers which are arranged in a stacked mode, and each grid structure in the grid structure array is electrically connected with one antenna structure through at least one conductive layer.
5. The semiconductor test structure of claim 4, wherein the semiconductor test structure further comprises: a fourth test pad electrically connected to the conductive layer, and different layers of the conductive layer are electrically connected to different fourth test pads.
6. The semiconductor test structure of claim 4, wherein the conductive layer of a same layer comprises discrete sub-conductive layers, the interconnect structure further comprising: and the conductive plug is positioned between the sub-conductive layers of the adjacent layers and is used for realizing the electrical connection between the sub-conductive layers of the adjacent layers.
7. The semiconductor test structure of claim 4, wherein the semiconductor test structure further comprises: a number of interconnect lines, wherein the interconnect lines are for electrical connection between the conductive layer and the antenna structure.
8. The semiconductor test structure of claim 1, wherein the antenna structure is rectangular in shape.
9. The semiconductor test structure of claim 1, wherein the antenna structure is in the shape of a comb structure comprising a comb handle portion and discrete comb teeth portions connected to the comb handle portion.
10. The semiconductor test structure according to claim 8, 9 or 1, wherein the antenna structures of different layers include N layers of antenna structures electrically connected through an antenna plug, and the electrically connected N layers of antenna structures are electrically connected to the same gate structure, where N is greater than or equal to 2.
11. The semiconductor test structure of claim 10, wherein when the antenna connection structure of the same layer includes a first comb structure and a second comb structure disposed opposite to the first comb structure, the antenna plug is electrically connected to the first comb portion of the antenna structure of a different layer; or the antenna plug is electrically connected with the second comb tooth part of the antenna structure of different layers.
12. The semiconductor test structure of claim 1, wherein the material of the antenna structure is polysilicon or metal.
13. A method for forming a semiconductor test structure, comprising:
providing a substrate, wherein a well region is formed in the substrate;
forming a grid structure array on the well region in the substrate;
forming a source region in the well region on one side of each gate structure in the gate structure array, and forming a drain region in the well region on the other side of each gate structure in the gate structure array;
forming a plurality of antenna structures which are arranged in a stacked mode, wherein each grid structure in the grid structure array is at least electrically connected with one layer of antenna structure;
a dielectric layer is formed between the antenna structures for electrical insulation between adjacent antenna structures.
14. A method of testing, comprising:
providing a semiconductor test structure according to any of claims 1 to 12;
applying a first bias voltage to at least one grid structure in the grid structure array to enable the source region, the drain region and the well region to be grounded and obtain grid current of the grid structure;
applying a second bias voltage to at least one grid structure in the grid structure array, and applying a third bias voltage to the drain region, so that the source region and the well region are grounded, and the threshold voltage of the grid structure is obtained;
applying a fourth bias voltage to any two antenna structures in the stacked antenna structures to obtain a breakdown voltage between the two antenna structures;
the antenna structure of the same layer comprises a first comb-shaped structure and a second comb-shaped structure opposite to the first comb-shaped structure;
applying a fourth bias voltage to the first comb-shaped structure and the second comb-shaped structure of the same layer; and acquiring the breakdown voltage between the first comb-shaped structure and the second comb-shaped structure in the same layer.
15. The test method of claim 14, wherein the test method comprises: and applying a fourth bias voltage to adjacent antenna structures in the stacked antenna structures to obtain the breakdown voltage between the adjacent antenna structures.
16. The test method of claim 15, wherein obtaining a breakdown voltage between the antenna structures of adjacent layers comprises:
applying a fourth bias voltage to two gate structures electrically connected to the adjacent layer antenna structure;
and changing the magnitude of the fourth bias voltage until the antenna structure breaks down, wherein the fourth bias voltage when the antenna structure breaks down is breakdown voltage.
17. The testing method of claim 14, further comprising:
the antenna structures on different layers comprise a plurality of layers of antenna structures which are electrically connected through antenna plugs, and the electrically connected antenna structures are electrically connected with the same grid structure;
and applying a fourth bias voltage to the antenna structure electrically connected with the antenna plug and the adjacent antenna structure electrically insulated from the antenna plug, and acquiring the breakdown voltage between the two antenna structures.
18. The method of testing of claim 14, wherein the semiconductor test structure further comprises: a first test pad, a second test pad, a third test pad, a fourth test pad, and an interconnect structure located over the array of gate structures; the interconnection structure comprises a plurality of conductive layers which are arranged in a stacked mode, wherein each grid structure in the grid structure array is electrically connected with one antenna structure through at least one conductive layer; the first test pad is electrically connected with the well region; the second test pad is electrically connected with the source region; the third test pad is electrically connected with the drain region; the fourth test pad is electrically connected with the conductive layer, and the conductive layers of different layers are electrically connected with different fourth test pads; in the process of obtaining the grid current of the grid structure, the fourth test pad is connected with a first bias voltage, and the first test pad, the second test pad and the third test pad are grounded; in the process of obtaining the threshold voltage of the gate structure, the fourth test pad is connected with the second bias voltage, the third test pad is connected with the third bias voltage, and the first test pad and the second test pad are grounded.
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| CN113451276A (en) * | 2021-06-28 | 2021-09-28 | 长江存储科技有限责任公司 | Test structure, test system and test method |
| CN114664744A (en) * | 2022-03-03 | 2022-06-24 | 长鑫存储技术有限公司 | Semiconductor device forming method and semiconductor device |
| CN114899177B (en) * | 2022-07-13 | 2022-09-16 | 合肥晶合集成电路股份有限公司 | Dielectric layer reliability test structure and test method |
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