CN109192676B - Characterization method of interface defect - Google Patents
Characterization method of interface defect Download PDFInfo
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- CN109192676B CN109192676B CN201811056275.1A CN201811056275A CN109192676B CN 109192676 B CN109192676 B CN 109192676B CN 201811056275 A CN201811056275 A CN 201811056275A CN 109192676 B CN109192676 B CN 109192676B
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a characterization method of interface defects. The characterization method of the interface defect comprises the following steps: forming a characterization structure, wherein the characterization structure comprises a substrate, a gate dielectric layer and a gate layer, the gate layer and the gate layer are positioned on the surface of the substrate, the gate layer comprises a first gate layer positioned on the surface of the gate dielectric layer and a second gate layer positioned on two opposite sides of the gate dielectric layer along the width direction of a channel, and the doped ion types of the first gate layer and the second gate layer are opposite; and respectively applying electric signals to the substrate, the first gate layer and the second gate layer to represent the defect density of the contact interface of the gate dielectric layer and the first gate layer. The defect density of the contact interface of the gate dielectric layer and the gate layer can be effectively represented.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a characterization method of interface defects.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
In integrated circuits such as 3D NAND memories, a large number of circuit elements, such as transistors, are provided and operated on a limited chip area. In an integrated circuit manufactured using Metal Oxide Semiconductor (MOS) technology, a Field Effect Transistor (FET) is used. Generally, a field effect transistor includes an n-type MOS transistor (i.e., NMOS) and a p-type MOS transistor (i.e., PMOS). During the fabrication of integrated circuits, field effect transistors may be fabricated in a variety of forms and configurations, such as planar FET devices or three-dimensional FET devices.
The reliability evaluation of the performance of the field effect transistor is an important part in the process development of the integrated circuit. However, the reliability evaluation of the Gate dielectric layer (Gate Oxide) in the field effect transistor is an important item in the previous paragraph, and is mainly used to evaluate the performance of the dielectric material in the previous paragraph. Many processes in the integrated circuit fabrication process may affect the upper and lower interfaces of the gate Dielectric layer, and thus the TDDB (Time Dependent Dielectric Breakdown) of the gate Dielectric layer, showing a polarity dependence. Therefore, how to effectively represent the defect density of the upper and lower interfaces of the gate dielectric layer is very important. However, the prior art does not have a method for effectively characterizing the interface defects of the gate dielectric layer.
Therefore, how to effectively characterize the interface defect of the gate dielectric layer is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention provides a method for characterizing interface defects, which is used for solving the problem that the interface defects of a gate dielectric layer cannot be effectively characterized in the prior art.
In order to solve the above problems, the present invention provides a method for characterizing an interface defect, comprising the following steps:
forming a characterization structure, wherein the characterization structure comprises a substrate, a gate dielectric layer and a gate layer, the gate layer and the gate layer are positioned on the surface of the substrate, the gate layer comprises a first gate layer positioned on the surface of the gate dielectric layer and a second gate layer positioned on two opposite sides of the gate dielectric layer along the width direction of a channel, and the doped ion types of the first gate layer and the second gate layer are opposite;
and respectively applying electric signals to the substrate, the first gate layer and the second gate layer to represent the defect density of the contact interface of the gate dielectric layer and the first gate layer.
Preferably, the specific steps of forming a characterizing structure include:
providing a substrate, wherein the surface of the substrate is provided with a gate dielectric layer;
and forming a gate layer on the substrate, wherein the gate layer comprises a first gate layer positioned on the surface of the gate dielectric layer and a second gate layer positioned on two opposite sides of the gate dielectric layer along the width direction of the channel, and the doped ion types of the first gate layer and the second gate layer are opposite.
Preferably, the substrate is provided with shallow trench isolation regions which are positioned on two opposite sides of the gate dielectric layer along the channel width direction and are positioned in the substrate;
the second grid layer at least partially covers the shallow trench isolation region.
Preferably, the substrate is internally provided with a doped region which is arranged corresponding to the gate dielectric layer;
the doped region is doped with the same ion type as the second gate layer.
Preferably, the doped region and the second gate layer are both doped with p-type ions, and the first gate layer is doped with n-type ions.
Preferably, the doped region and the second gate layer are both doped with n-type ions, and the first gate layer is doped with p-type ions.
Preferably, the ion doping concentration of the doping region is greater than that of the second gate layer.
Preferably, the ion doping concentration of the first gate layer is the same as the ion doping concentration of the second gate layer.
Preferably, after forming the gate layer on the substrate, the method further includes:
depositing an insulating material on the first gate layer, the second gate layer and the surface of the substrate to form a dielectric layer;
etching the dielectric layer, and simultaneously forming a first through hole penetrating to the surface of the substrate, a second through hole penetrating to the surface of the first grid layer and a third through hole penetrating to the surface of the second grid layer;
and depositing a conductive material in the first through hole, the second through hole and the third through hole, and simultaneously forming a first conductive plug in contact with the substrate, a second conductive plug in contact with the first grid layer and a third conductive plug in contact with the second grid layer.
Preferably, applying the electrical signal to the substrate, the first gate layer, and the second gate layer, respectively, comprises:
a periodic pulsed electrical signal is applied to the substrate through the first conductive plug, a reverse bias voltage is applied to the second gate layer through the third conductive plug, and the first gate layer is grounded through the second conductive plug.
According to the method for characterizing the interface defect, the length of the gate layer is extended along the width direction of the transistor channel, so that the gate layer comprises the first gate layer positioned on the surface of the gate dielectric layer and the second gate layer positioned on the opposite sides of the gate dielectric layer, and the first gate layer and the second gate layer are subjected to opposite-type ion doping, so that an inverted MOS (metal oxide semiconductor) structure is formed, and voltage can be conveniently applied to the substrate, the first gate layer and the second gate layer, so that the defect density of the contact interface of the gate dielectric layer and the gate layer is characterized.
Drawings
FIG. 1 is a flow chart of a method for characterizing interfacial defects in an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of an interface defect characterization structure along the length of a transistor channel as characterized in the embodiments of the present invention;
FIG. 3 is a schematic cross-sectional view of an interface defect characterization structure along a transistor channel width direction as characterized in the detailed description of the invention;
FIG. 4 is a schematic diagram of an electrical circuit configuration of an interface defect characterization structure as characterized in the detailed description of the invention;
FIG. 5 is a flow chart of a method for forming an interfacial defect characterization structure as characterized in an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of the method for characterizing interfacial defects provided by the present invention with reference to the accompanying drawings.
In the field effect transistor structure, a gate dielectric layer and a gate electrode are sequentially stacked on the surface of a substrate. Therefore, the evaluation of the defect density of the lower interface of the gate dielectric layer contacting the substrate and the upper interface of the gate dielectric layer contacting the gate electrode is one of the main components of the reliability evaluation of the gate dielectric layer. Because the performance of the lower interface of the contact of the gate dielectric layer and the substrate is evaluated, mainly the defect density of the channel region of the field effect transistor is evaluated, the performance can be characterized by adopting a Charge Pumping (CP) test mode. However, there is no effective means for characterizing the defect density at the upper interface of the gate dielectric layer and the gate contact.
In order to effectively characterize the defect density of the upper interface where the gate dielectric layer contacts the gate electrode, the present embodiment provides a method for characterizing an interface defect, fig. 1 is a flowchart of the method for characterizing an interface defect in the present embodiment, fig. 2 is a schematic cross-sectional view of an interface defect characterizing structure characterized in the present embodiment along the length direction of a transistor channel, fig. 3 is a schematic cross-sectional view of an interface defect characterizing structure characterized in the present embodiment along the width direction of a transistor channel, and fig. 4 is a schematic circuit structure diagram of an interface defect characterizing structure characterized in the present embodiment. As shown in fig. 1 to 4, the method for characterizing an interface defect provided by the present embodiment includes the following steps:
step S11, forming a characterization structure, where the characterization structure includes a substrate 11, and a gate dielectric layer 13 and a gate layer located on a surface of the substrate 11, where the gate layer includes a first gate layer 141 located on the surface of the gate dielectric layer 13 and a second gate layer 142 located on two opposite sides of the gate dielectric layer 13 along a channel width direction, and the doped ion types of the first gate layer 141 and the second gate layer 142 are opposite;
step S12, applying electrical signals to the substrate 11, the first gate layer 141, and the second gate layer 142, respectively, to characterize the defect density of the contact interface between the gate dielectric layer 13 and the first gate layer 141.
Preferably, the specific steps of forming a characterizing structure include:
providing a substrate 11, wherein a gate dielectric layer 13 is arranged on the surface of the substrate 11;
and forming a gate layer on the substrate, wherein the gate layer comprises a first gate layer 141 positioned on the surface of the gate dielectric layer 13 and a second gate layer 142 positioned on two opposite sides of the gate dielectric layer 13 along the channel width direction, and the ion types of the first gate layer 141 and the second gate layer 142 are opposite.
Specifically, as shown in fig. 2, along the length direction of the channel of the field effect transistor, a source region 15 and a drain region 16 extend from the surface of the substrate 11 on which the gate dielectric layer 13 is formed to the inside of the substrate 11, and the source region 15 and the drain region 16 are distributed on two opposite sides of the gate dielectric layer 13. As shown in fig. 3, in order not to affect the normal function of the field effect transistor, the gate layer extends along the width direction of the channel of the field effect transistor, and a first gate layer 141 on the surface of the gate dielectric layer 13 and a second gate layer 142 extending out of the gate dielectric layer 13 are formed. Wherein the width direction is a direction perpendicular to the length direction. Meanwhile, by controlling the ion types of the first gate layer 141 and the second gate layer 142 to be opposite, a PN junction is formed between the first gate layer 141 and the second gate layer 142, so that after an electrical signal is applied to the substrate 11, the first gate layer 141, and the second gate layer 142, the substrate 11, the first gate layer 141, and the second gate layer 142 together form an inverted MOS transistor structure, as shown in fig. 4: the substrate 11 is equivalent to the gate 31 of the MOS transistor, the second gate layer 142 on one side of the gate dielectric layer 13 is equivalent to the source 32 of the MOS transistor, the second gate layer 142 on the other side of the gate dielectric layer 13 is equivalent to the drain 33 of the MOS transistor, and the first gate layer 141 is equivalent to the base 34 of the MOS transistor. By constructing the inverted MOS structure, the defect density of the contact interface between the gate dielectric layer 13 and the first gate 141 can be characterized by using the existing interface defect characterization method.
Preferably, the substrate 11 has shallow trench isolation regions 22 located on two opposite sides of the gate dielectric layer 13 in the channel width direction and located in the substrate 11; the second gate layer 142 at least partially covers the shallow trench isolation region 22.
Preferably, the substrate 11 has a doped region 12 corresponding to the gate dielectric layer 13; the doped region 12 is doped with the same ion type as the second gate layer 142. For example, the doped region 12 and the second gate layer 142 are both doped with p-type ions, and the first gate layer is doped with n-type ions, that is, the substrate 11, the second gate layer 142, and the first gate layer 141 together form an inverted NMOS transistor structure; alternatively, the doped region 12 and the second gate layer 142 are both doped with n-type ions, and the first gate layer 141 is doped with p-type ions, that is, the substrate 11, the second gate layer 142, and the first gate layer 141 together form an inverted PMOS transistor structure.
The ion doping concentration of the doped region 12 is greater than that of the second gate layer 142. Preferably, the ion doping concentration of the first gate layer 141 is the same as the ion doping concentration of the second gate layer 142. By adopting the structure, the resistance of the doped region 12 can be effectively reduced, so that the overall electrical response speed of the interface defect characterization structure is improved. More preferably, the ion doping concentration of the doped region 12 is 1 × 1015/cm3～5×1018/cm3The ion doping concentration of the first gate layer 141 is 1 × 1015/cm3～5×1015/cm3The ion doping concentration of the second gate layer 142 is 1 × 1015/cm3～5×1015/cm3。
Preferably, after forming the gate layer on the substrate 11, the method further includes:
depositing an insulating material on the surfaces of the first gate layer 141, the second gate layer 142 and the substrate 11 to form a dielectric layer;
etching the dielectric layer, and simultaneously forming a first through hole penetrating to the surface of the substrate 11, a second through hole penetrating to the surface of the first gate layer 141, and a third through hole penetrating to the surface of the second gate layer 142;
and depositing conductive materials in the first through hole, the second through hole and the third through hole, and simultaneously forming a first conductive plug 25 in contact with the substrate 11, a second conductive plug 23 in contact with the first gate layer 141 and a third conductive plug 24 in contact with the second gate layer 142.
Preferably, the applying the electrical signal to the substrate 11, the first gate layer 141, and the second gate layer 142 includes:
a periodic pulsed electrical signal is applied to the substrate 11 through the first conductive plugs 25, a reverse bias is applied to the second gate layer 142 through the third conductive plugs 24, and the first gate layer 141 is grounded through the second conductive plugs 23.
Furthermore, the present embodiment provides an interface defect characterization structure, and the interface defect characterization structure provided by the present embodiment is shown in fig. 2 to fig. 4.
As shown in fig. 2 to fig. 4, the interface defect characterization structure provided by this embodiment further includes: a substrate 11; a gate dielectric layer 13 positioned on the surface of the substrate 11; the gate layer comprises a first gate layer 141 positioned on the surface of the gate dielectric layer 13 and a second gate layer 142 positioned on two opposite sides of the gate dielectric layer 13 in the channel width direction, and the ion types of the first gate layer 141 and the second gate layer 142 are opposite.
Preferably, the substrate 11 has a doped region 12 therein; the doped region 12 is disposed corresponding to the gate dielectric layer 13 and has the same ion type as the doped ions of the second gate layer 142.
In order to facilitate the application of voltage to each component in the interface defect characterization structure, preferably, the interface defect characterization structure provided by this embodiment further includes:
a first conductive plug 25 having one end in contact with the substrate 11 and the other end for receiving a first detection electrical signal;
a second conductive plug 23 having one end in contact with the first gate layer 141 and the other end for receiving a second detection electric signal;
and a third conductive plug 24 having one end contacting the second gate layer 142 and the other end for receiving a third detection electrical signal.
Preferably, the doped region 12 and the second gate layer 142 are both doped with p-type ions, and the first gate layer 141 is doped with n-type ions; alternatively, the doped region 12 and the second gate layer 142 are both doped with n-type ions, and the first gate layer 141 is doped with p-type ions.
Preferably, the ion doping concentration of the doped region 12 is greater than that of the second gate layer 142. More preferably, the ion doping concentration of the first gate layer 141 is the same as the ion doping concentration of the second gate layer 142.
In order to further improve the accuracy of the interface characterization, preferably, the interface defect characterization structure further includes:
shallow trench isolation regions 22 located in the substrate 11, where the shallow trench isolation regions 22 are located on two opposite sides of the gate dielectric layer 13 along the channel width direction;
the second gate layer 142 at least partially covers the shallow trench isolation region 22.
Moreover, the present embodiment further provides an interface defect detection apparatus. The interface defect detection device is used for detecting the interface defect of any one of the interface defect characterization structures and comprises a detection part. The detection part is used for applying electric signals to the substrate 11, the first gate layer 141 and the second gate layer 142 respectively so as to detect the defect density of the contact interface of the gate dielectric layer 13 and the first gate layer 141. Preferably, the detection unit is a charge pump.
Specifically, the interface defect characterization structure is switched between an inversion state and an accumulation state by applying a pulse voltage to the substrate 11 periodically by the charge pump, wherein the substrate is the gate 31 of the MOS transistor, the first gate layer 141 is the base 34 and is grounded, and the second gate layer 142 is the source 32 and the drain 33. In the inversion state, minority carriers from the second gate layer 142 fill the contact interface of the gate dielectric layer 13 and the first gate layer 141; in the accumulation state, majority carriers from the first gate layer 141 are recombined with minority carriers filled at the contact interface between the gate dielectric layer 13 and the first gate layer 141, so as to form a charge pump current. By analyzing the charge pump current, the defect density of the contact interface between the gate dielectric layer 13 and the first gate layer 141 can be characterized.
Furthermore, the present embodiment further provides a method for forming an interface defect characterization structure, and fig. 5 is a flowchart of a method for forming an interface defect characterization structure characterized in the present embodiment, and the interface defect characterization structure formed in the present embodiment is shown in fig. 2 to fig. 4. As shown in fig. 2 to fig. 5, the method for forming an interface defect characterization structure according to this embodiment includes the following steps:
step S51, providing a substrate 11, where the surface of the substrate 11 has a gate dielectric layer 13. The substrate 11 is preferably a silicon substrate.
Step S52, forming a gate layer on the substrate 11, where the gate layer includes a first gate layer 141 located on the surface of the gate dielectric layer 13 and a second gate layer 142 located on two opposite sides of the gate dielectric layer 13 along the channel width direction, and the doped ion types of the first gate layer 141 and the second gate layer 142 are opposite.
Preferably, the substrate 11 has a doped region 12 which is disposed corresponding to the gate dielectric layer 13 and is doped with a first type of ions; forming a gate layer on the substrate 11 includes:
forming a gate material layer on the gate dielectric layer 13 and the surface of the substrate 11;
performing second-type ion doping on the first region in the gate material layer to form the first gate layer 141;
and performing first type ion doping on a second region in the gate material layer to form the second gate layer 142.
In this embodiment, the first type ions are p-type ions and the second type ions are n-type ions, so as to form a PN junction between the first gate layer 141 and the second gate layer 142. In other embodiments, the first type of ion may also be an n-type ion and, correspondingly, the second type of ion is a p-type ion.
Specifically, the specific steps of forming the gate material layer on the gate dielectric layer 13 and the surface of the substrate 11 include: and depositing a polysilicon material on the gate dielectric layer 13 and the surface of the substrate 11 to form the gate material layer. A polysilicon material may be deposited on the gate dielectric layer 13 and the surface of the substrate 11 by using a chemical vapor deposition, physical vapor deposition, or plasma deposition process. An IMP (Ionized Metal Plasma sputtering) process may be used in the process of doping the first polysilicon material layer with n-type ions and doping the second polysilicon material layer with p-type ions. The ion doping concentrations of the first gate layer 141 and the second gate layer 142 may be the same as the ion doping concentrations of the source region 15 and the drain region 16 in the transistor including the characterized gate dielectric layer. Preferably, the ion doping concentration of the doped region 12 is greater than that of the second gate layer 142. Preferably, the ion doping concentration of the first gate layer 141 is the same as the ion doping concentration of the second gate layer 142.
Preferably, the substrate 11 further includes shallow trench isolation regions 22 located in the substrate 11 and distributed on two opposite sides of the gate dielectric layer 13 along the channel width direction;
the second gate layer at least partially covers the shallow trench isolation region 22.
Preferably, after forming the gate layer on the substrate 11, the method further includes:
depositing an insulating material on the surfaces of the first gate layer 141, the second gate layer 142 and the substrate 11 to form a dielectric layer;
etching the dielectric layer, and simultaneously forming a first through hole penetrating to the surface of the substrate 11, a second through hole penetrating to the surface of the first gate layer 141, and a third through hole penetrating to the surface of the second gate layer 142;
and depositing conductive materials in the first through hole, the second through hole and the third through hole, and simultaneously forming a first conductive plug 25 in contact with the substrate, a second conductive plug 23 in contact with the first gate layer 141 and a third conductive plug 24 in contact with the second gate layer 142. Wherein the conductive material is preferably tungsten.
In the method for characterizing an interface defect provided by this embodiment, the length of the gate layer is extended along the width direction of the transistor channel, so that the gate layer includes a first gate layer located on the surface of the gate dielectric layer and a second gate layer located on opposite sides of the gate dielectric layer, and the first gate layer and the second gate layer are doped with ions of opposite types, thereby forming an inverted MOS structure, which facilitates applying a voltage to the substrate gate layer, the first gate layer, and the second gate layer, so as to characterize the defect density of the contact interface between the gate dielectric layer and the gate layer.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A characterization method of an interface defect is characterized by comprising the following steps:
forming a characterization structure, wherein the characterization structure comprises a substrate, a gate dielectric layer and a gate layer, the gate dielectric layer and the gate layer are positioned on the surface of the substrate, the gate layer comprises a first gate layer positioned on the surface of the gate dielectric layer and a second gate layer positioned on two opposite sides of the gate dielectric layer along the width direction of a channel, and the doped ion types of the first gate layer and the second gate layer are opposite to each other, so that an inverted MOS (metal oxide semiconductor) tube structure is formed;
and respectively applying electric signals to the substrate, the first gate layer and the second gate layer to represent the defect density of the contact interface of the gate dielectric layer and the first gate layer.
2. The method for characterizing interface defects according to claim 1, wherein the substrate has shallow trench isolation regions located on two opposite sides of the gate dielectric layer in the channel width direction and located in the substrate;
the second grid layer at least partially covers the shallow trench isolation region.
3. The method for characterizing interfacial defects according to claim 1, wherein the substrate has a doped region therein corresponding to the gate dielectric layer;
the doped region is doped with the same ion type as the second gate layer.
4. The method of claim 3, wherein the doped region and the second gate layer are both doped with p-type ions, and the first gate layer is doped with n-type ions.
5. The method of claim 3, wherein the doped region and the second gate layer are both doped with n-type ions, and the first gate layer is doped with p-type ions.
6. The method of characterizing interfacial defects according to claim 4 or 5, wherein the doped region has an ion doping concentration greater than that of the second gate layer.
7. The method of characterizing interfacial defects according to claim 4 or 5, wherein the ion doping concentration of the first gate layer is the same as the ion doping concentration of the second gate layer.
8. The method of characterizing interfacial defects according to claim 1, further comprising the steps of:
depositing an insulating material on the first gate layer, the second gate layer and the surface of the substrate to form a dielectric layer;
etching the dielectric layer, and simultaneously forming a first through hole penetrating to the surface of the substrate, a second through hole penetrating to the surface of the first grid layer and a third through hole penetrating to the surface of the second grid layer;
and depositing a conductive material in the first through hole, the second through hole and the third through hole, and simultaneously forming a first conductive plug in contact with the substrate, a second conductive plug in contact with the first grid layer and a third conductive plug in contact with the second grid layer.
9. The method of characterizing interfacial defects according to claim 8, wherein applying electrical signals to the substrate, the first gate layer, and the second gate layer, respectively, comprises:
a periodic pulsed electrical signal is applied to the substrate through the first conductive plug, a reverse bias voltage is applied to the second gate layer through the third conductive plug, and the first gate layer is grounded through the second conductive plug.
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