TWI594401B - Simple and cost-free mtp structure - Google Patents

Description

Simple and free multiple programmable structure

The present invention relates to a non-volatile memory unit and a method of forming the same.

In recent years, multi-time programmable (MTP) memory has been introduced for beneficial use in applications that require customization for digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security IDs, and more. However, the inclusion of MTP memory typically also incurs the cost of some additional process steps. Some existing methods of fabricating MTP memory tend to have slow access times, small coupling ratios, and/or large cell sizes. Some existing methods use a band-to-band tunneling hot hole (BBHH) for the erase operation, but this requires a high junction band voltage and more process steps. Other existing methods require additional coupling erase gates and coupling capacitors, requiring more area.

Therefore, there is a need for a simple and free multiple programmable structure to fabricate non-volatile memory cells with standard complementary metal oxide semiconductor (CMOS) platforms.

Embodiments are generally directed to a simple and free multiple programmable structure. In one embodiment, the non-volatile MTP memory cell includes a substrate provided with an isolation well, a high voltage (HV) well region disposed within the isolation well, and a first region within the HV well region disposed in the substrate With the second well. A first transistor having a select gate and a second transistor having a floating gate are adjacent to each other and disposed above the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. A control gate is disposed over the first well and coupled to the floating gate. The control gate and the floating gate include the same gate layer extending across the first and second wells. The control gate includes a capacitor.

In other embodiments, a non-volatile MTP memory unit is disclosed. The memory unit includes a substrate provided with first and second isolation wells. The second isolation well is disposed in the first isolation well. First and second wells are disposed within the first isolation well. A first transistor having a select gate and a second transistor having a floating gate are adjacent to each other and disposed above the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. A control gate is disposed over the first well and coupled to the floating gate. The control gate and the floating gate include the same gate layer extending across the first and second wells.

In yet another embodiment, a method for forming a non-volatile MTP memory cell is disclosed. A substrate is provided and first and second isolation wells are formed in the substrate. First and second wells are formed in the second isolation well. First transistor with selective gate and floating gate The second transistor locations are adjacent to one another and are formed over the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. The first and second transistors are coupled in series and share a common second diffusion region. A control gate is formed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.

These and other advantages and features of the embodiments disclosed herein will be apparent from the description and appended claims. Further, it is to be understood that the advantages of the various embodiments described herein are not mutually exclusive and may be present in various embodiments and permutations.

100‧‧‧ memory unit

110‧‧‧First transistor

112‧‧‧First access diffusion area

114‧‧‧Second access diffusion area

116‧‧‧ access gate

130‧‧‧Second transistor

132‧‧‧First storage diffusion area

134‧‧‧Second storage diffusion area

136‧‧‧Storage gate

150‧‧‧Control Capacitor

152‧‧‧Capacitive contact plug

156‧‧‧Control gate

200‧‧‧ memory unit

205‧‧‧Substrate

207‧‧‧Second well

208‧‧‧Isolation well

209‧‧‧First Well

210‧‧‧HV well area

212‧‧‧First access diffusion area

214‧‧‧Second access diffusion area

216‧‧‧ access gate

220‧‧‧Active Capacitor Area

222‧‧‧Active transistor area

232‧‧‧First storage diffusion area

234‧‧‧Second storage diffusion area

236‧‧‧Storage gate

252‧‧‧Capacitive contact plug

256‧‧‧Control gate

257‧‧‧gate dielectric

258‧‧ ‧ gate electrode

261‧‧‧ Telluride block

280‧‧‧Unit isolation area

284‧‧‧Unit area

290‧‧‧primary layer

300‧‧‧Array of memory cells

400a‧‧‧FN tunneling mode

400b‧‧‧FN tunneling erase mode

400c‧‧‧Read operation

500‧‧‧Array of memory cells

600‧‧‧Process

602 to 618‧‧‧ Process steps

In the drawings, the same symbols generally indicate the same parts in the various different aspects. Moreover, the drawings are not necessarily to scale unless otherwise In the following description, various embodiments of the invention are described with reference to the following drawings in which: FIG. 1 shows a schematic diagram of a memory unit; FIG. 2a shows a top view of an embodiment of a memory unit, and FIGS. 2b and 2c Various cross-sectional views showing an embodiment of the memory cell; Figures 3a and 3b show schematic views of an embodiment of an array of memory cells; Figures 4a through 4c show various operations of the memory cell; and Figure 5 shows memory cells Array of embodiments Plan view; and Figure 6 shows a process for forming an embodiment of a memory cell.

Embodiments are generally directed to semiconductor devices. In particular, some embodiments are directed to memory devices, such as non-volatile memory (NVM) devices. For example, such memory devices can be incorporated into a stand-alone memory device, such as a USB or other type of portable storage unit, or an IC, such as a microcontroller or system on chips (SoCs). For example, the device or IC can be incorporated or used with consumer electronics or other types of devices in question.

FIG. 1 shows a schematic diagram of an embodiment of a memory unit 100. In one embodiment, the memory unit is a non-volatile (NV) multiple programmable (MTP) memory unit 100. As shown in FIG. 1, the memory unit 100 includes a first transistor 110, a second transistor 130, and a control capacitor 150. In an embodiment, the second transistor acts as a storage element and the control capacitor acts as a voltage coupling element. For example, the first and second transistors are metal oxide semiconductor (MOS) transistors. The transistor includes a gate between the first and second diffusion regions. The diffusion region of the transistor is a heavily doped region having a dopant of the first polarity type. This type of polarity determines the type of transistor. For example, the first polarity can be n-type for an n-type transistor or p-type for a p-type transistor.

In an embodiment, the transistor diffusion region may include a diffusion extension region (not shown). For example, the transistor diffusion region can include A lightly doped diffusion region that extends beyond the diffusion region and overlaps a portion of the transistor gate. The diffusion extension region may include a lightly doped drain (LDD) extension region and a halo region. For example, the LDD extension region is oppositely doped with the annular region. For example, for a first type of transistor, the annular region includes a second polarity type dopant, and the LDD extension region includes a first polarity type dopant for the first type of transistor. Other configurations can be used for the diffusion extension area. For example, a diffusion extension region having only an LDD extension region and no annular region can be used.

The gate includes a gate electrode and a gate dielectric. The first transistor 110 serves as an access transistor and the second transistor 130 serves as a storage transistor. For example, the access transistor 110 includes a first access diffusion region 112, a second access diffusion region 114, and an access gate 116. The storage transistor 130 includes a first storage diffusion region 132 and a second storage diffusion. Region 134 and storage gate 136. Access gate 116 can be referred to as a select gate, and storage gate 136 can be referred to as a floating gate.

In an embodiment, the control capacitor 150 is a MOS capacitor. For example, the control capacitor 150 includes a control gate 156 having a control gate electrode and a control gate dielectric. Control gate 156 forms control capacitor 150. The control capacitor includes first and second capacitor plates separated by a dielectric layer. For example, the control gate electrode acts as the first (or gate capacitance) plate and the control well 209 (described later) acts as the second (or well) capacitor plate. For example, a dielectric layer disposed over the second capacitor plate separates the first and second capacitor plates. A capacitive contact plug 152 (or a well tap described later) is disposed on the substrate and coupled The active capacitor (or well pickup region) is coupled to provide a bias to the control well. In an embodiment, the capacitive contact plug is disposed adjacent to the control capacitor. For example, the capacitive contact plug is disposed adjacent to a side of the control gate. The capacitive contact plug provides an electrically conductive connection to the active capacitive region. In an embodiment, the control gate is coupled to the storage gate. For example, the gate is formed by a common gate conductor. The control capacitor isolates the storage gate 136 to become a floating gate.

The access and storage transistors 110 and 130 are coupled in series. For example, the second access diffusion region and the second storage diffusion regions 114 and 134 form a common diffusion region of the transistor. As for the control gate 156 and the storage gate 136, they are co-coupled. For example, a common gate electrode and a gate dielectric are provided to form the storage gate and the control gate. Other configurations of the storage and control gates may also be useful. By collectively coupling the control and storage gates 156 and 136, a floating storage gate is created.

The first access diffusion region 112 of the first or access transistor 110 is coupled to a source line (SL) of the memory device. The first storage diffusion region 132 of the second or storage transistor 130 is coupled to a bit line (BL) of the memory device. The select gate of the memory cell 100, or the access gate 116 of the first transistor 110, is coupled to a select gate line (SGL) of the memory device. The capacitive contact plug 152 of the control capacitor is coupled to the control gate line (CGL) of the memory device. In an embodiment, the SGL is disposed along a first direction (eg, a word line direction) and the BL is disposed along a second direction (eg, a bit line direction). For example, the first and second directions are Orthogonal to each other. As for the CGL, it is disposed along the direction of the word line and the SL is disposed along the direction of the bit line. Other configurations of BL, CGL, SGL, and SL can also be used. For example, the memory cells of the array can also be coupled to a common SL (CSL) disposed along the direction of the word line.

Fig. 2a shows a top view of various embodiments of the memory cell, and Fig. 2b shows a cross-sectional view of the memory cell of an embodiment, and Fig. 2c shows a cross-sectional view of another embodiment of the memory cell. For example, these cross-sectional views are along the A-A', B-B', and C-C' segments of the memory cell. The memory device includes a memory unit 200. This memory unit is similar to that described in Figure 1. Common components may not be described or described in detail. The displayed memory unit 200 is an NVM unit. For example, the memory unit is a non-volatile MTP memory unit.

The device can include doped regions having different dopant concentrations. For example, the device can include heavily doped (x ⁺ ), moderately doped (x), and lightly doped (x ⁻ ) regions, where x can be a polar type of p-type or n-type dopant. The lightly doped region may have a dopant concentration of about 1E11-1E12 cm ^-2 , the medium doped region may have a dopant concentration of about 1E12-1E13 cm ^-2 , and the heavily doped region may have about 1E13 - 1E14 cm ^-2 dopant concentration. Other dopant concentrations can also be provided for different types of doped regions. For example, the dopant concentration range can vary depending on the technology node. The P-type dopant may include boron (B), fluorine (F), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), bismuth. (Sb) or a combination thereof.

The device is disposed on the substrate 205. The substrate is a semiconductor substrate such as a germanium substrate. Other types of semiconductor substrates may also be useful. In an embodiment, the substrate 205 is a lightly doped substrate. In an embodiment, the substrate is lightly doped with a dopant of a second polarity type. For example, the substrate is lightly doped p-type (p ^-) of the substrate. Substrates or other undoped substrates doped with other types of dopants may also be provided.

A cell region 284 is provided in the substrate. For example, the unit area is a unit area in which the memory unit is disposed. Although shown as a unit area, the apparatus can include a plurality of unit areas having memory cells interconnected to form a memory array. Further, depending on the type of device or IC, the substrate can include other types of device regions. For example, the device can include a device area for high voltage (HV), medium or medium voltage (MV) and/or low voltage (LV) devices.

The unit area includes first and second wells 209 and 207. The first well system acts as a control well for the control gate and the second well system acts as a transistor well. For example, the transistor well is used as a well for accessing (or selecting) and storing transistors 110 and 130. In an embodiment, the control gate includes a control capacitor 150. The control capacitor can be a MOS capacitor. Other types of control gates can also be used.

As shown, the wells are placed adjacent to each other. The first well 209 houses the control capacitor and the second well 207 houses the access and storage transistors. The first (or control) well includes a capacitance type dopant and the second (or transistor) well includes a transistor well type dopant. In an embodiment, the control well is a lightly doped well. For example, the control well may have a dopant concentration of about 1E11-1E12 cm ^-2 . Regarding the transistor well, it can be a light to moderate doped well. For example, the transistor well can have a dopant concentration of about 1E12-1E13 cm ^-2 . Other control and/or dopant concentrations of the transistor wells can also be used. The first and second wells can be used as device wells for HV and MV devices, respectively. For example, the first well is sufficiently doped to form an HV device well while the second well is sufficiently doped to form an MV device well.

From the surface of the substrate, the first well 209 includes a depth D _W1 and the second well 207 includes a depth D _W2 . Although the figures illustrate that the first and second wells have approximately the same depth dimension from the surface of the substrate, it should be understood that the first and second wells may also include different depth dimensions. For example, D _{W1 of} the first well may be different from D _{W2 of} the second well.

The type of polarity of the control well dopant may depend on the type of polarity of the control gate. In an embodiment, the polarity of the control well depends on the polarity type of the control capacitor. In the example of controlling the capacitance, the control well is of the same polarity as the capacitance type. For example, the control well dopant is p-type for a p-type MOS capacitor or n-type for an n-type MOS capacitor. Regarding the transistor well dopant, it is of the opposite polarity type to the transistor. In an embodiment, for a first type of transistor having a first polarity type dopant, the transistor well dopant is a dopant of a second polarity type. For example, for an n-type transistor, the transistor well dopant is p-type. In an embodiment, the polarity type of the transistor well is opposite to the polarity type of the control well. For example, a transistor of the second polarity type is provided to a control well of the first polarity type. The first polarity type can be an n-type and the second polarity type can be a p-type. Other configurations of the transistor and control well can also be used. For example Said that the first polarity type can be p-type and the second polarity type can be n-type.

Isolation well 208 can be provided in the substrate as shown in Figures 2b and 2c. The isolation well may be a deep isolation well disposed below the first and second wells. In one embodiment, the isolation well is a common isolation well for a memory wafer. For example, the isolation well surrounds a plurality of memory arrays of a memory chip. The isolation well includes an isolation well dopant. In an embodiment, the isolation well is lightly doped with an isolation well dopant. For example, the isolation well dopant has a polarity type that is opposite to the substrate type polarity type. In an embodiment, for the second polarity type substrate, the isolation well dopant is a first polarity type dopant. For example, an n-type isolation well is provided to the p-type substrate. Isolation wells and other configurations of the substrate can also be used. The isolation well 208 is used to isolate the first and second wells from the substrate to improve the noise immunity of the memory device. The isolation well 208 has a depth D _N from the surface of the substrate. The isolation well 208 can be referred to as a first isolation well.

In some embodiments, the HV well region 210 can be provided within the isolation well 208 in the substrate. In an embodiment, the HV well region surrounds the first and second wells. For example, the HV well region separates the first and second wells 209 and 207 from the isolation well 208. In one embodiment, the HV well region is a common HV well region of the memory array. For example, the HV well region surrounds a plurality of memory cells of the memory array. The HV well region includes HV well dopants. In an embodiment, the HV well region 210 is lightly doped with HV well dopants. For example, the polarity type of the HV well dopant is opposite to the polarity type of the isolation well dopant. In an embodiment, the HV well dopant is of a second polarity type for the isolation well dopant of the first polarity type. For example, a p-type HV well region is provided for an n-type isolation well. The HV well area as well as other configurations of the isolation well can also be used. In an embodiment, the HV well region and the control well are doped with dopants of opposite polarity types. For example, a p-type HV well region is provided for the n-type isolation and control wells 208 and 209. The HV well area is used to improve isolation of the control well during operation of the apparatus or program. The provision of the HV well region enables selective programming and reduces cell size layout. The HV well region has a depth D _P from the surface of the substrate. The HV well area can be referred to as a second isolation well.

In an embodiment, D _P is shallower than D _N and deeper than D _W . In general, D _{W is} less than D _P and D _{P is} less than D _N (D _W <D _P <D _N ). For example, D _N can be about 1.8 μm and D _P can be about 0.8-1.2 μm. Other suitable depth dimensions for D _W , D _{N ,} and D _P can also be used.

The unit isolation region 280, as shown, separates the first and second wells from other device regions. In an embodiment, the cell isolation region 280 is sufficiently overlapped with the first and second wells 209 and 207 to isolate the different wells. For example, the unit isolation region overlaps a portion of the first and second wells. In an embodiment, the bottoms of the first and second wells extend below the unit isolation region. For example, the first and second wells extend to and protrude below the unit isolation region. Other configurations of the first and second wells can also be used. A lifting type of isolation type may also be provided between the first and second wells. The unit isolation region defines an active region in the first and second wells. For example, the unit isolation region is defined in the second well 207 Active transistor region 222, and active capacitive region 220 in first well 209. For example, the cell isolation region is a shallow trench isolation (STI) region. Other types of isolated areas can also be used.

The cell isolation region has a depth D _I . For example, the cell isolation region has a depth D _I from the surface of the substrate. In an embodiment, the unit isolation region has a shallower depth than the first and second wells. For example, D _I is less deep than the first and second wells and the HV well region (D _I <D _W <D _P ). For example, D _I can be about 0.5 μm . Other suitable depth dimensions for D _I can also be used.

In other embodiments, a native layer 290 protrudes below the cell isolation region separating the first and second wells 209 and 207, as shown in Figure 2c. A native layer 290 is disposed between the bottoms of the first and second wells. For example, the native layer separates the first and second wells. In an embodiment, the fabrication process is designed to include maintaining a low doping concentration of the substrate region of the substrate 205 to form the native layer 290. For example, the native layer is an essentially doped layer and acts as a barrier to maintain the original lightly doped portion of the substrate, which may become heavily doped regions during the logic (or main) process. Other types of native layers can also be used. The native layer extends from the bottom of the cell isolation region to a depth of approximately _DW . For example, the first and second wells do not protrude below the cell isolation region. The threshold voltage (Vt) is typically very low, for example, about 0.2 V and the native layer is a lightly doped layer having properties very similar or close to the initial substrate. Thus, the presence of the native layer improves isolation between the first and second wells and increases the breakdown voltage.

An access and storage cell system is disposed on the active transistor region in the second or transistor well. The transistor includes a gate disposed between the first and second diffusion regions. For example, the diffusion region includes a dopant of the same polarity type as the transistor type dopant. For example, a p-type transistor has a diffusion region with a p-type dopant. For example, the diffusion region is a heavily doped region. The gate is disposed on the substrate and the diffusion region is disposed in an active region of the substrate. The gate includes a gate electrode 258 and a gate dielectric 257. For example, gate electrode 258 can be a polysilicon gate electrode and gate dielectric 257 can be a yttria gate dielectric. Gate electrodes as well as other types of dielectric materials can also be used.

A dielectric spacer (not shown) may be provided on the gate sidewall of the transistor. The spacer can be used to facilitate the formation of a transistor diffusion region. For example, a spacer is formed after the diffusion extension region is formed. For example, a spacer can be formed by forming a spacer layer on the substrate and anisotropically etching it to remove the horizontal portion, leaving a spacer on the sidewall of the gate. After the spacer is formed, implantation is performed to form the transistor diffusion region.

As discussed, access transistor 110 includes first and second access diffusion regions 212 and 214 heavily doped with transistor type dopants in active transistor region 222 and access gates on the substrate Pole 216. In an embodiment, the transistor diffusion region can include a diffusion extension region (not shown) that extends beyond the diffusion region to protrude below a portion of the transistor gate. The access gate includes an access gate electrode 258 overlying the access gate dielectric 257. The access gate can be referred to as a selection gate. Storage The storage transistor 130 includes first and second storage diffusion regions 232 and 234 heavily doped with a transistor type dopant in the substrate and a storage gate 236 on the substrate. The storage gate includes a storage gate electrode 258 overlying the storage gate dielectric 257. The storage gate can be referred to as a floating gate. Access and storage transistors 110 and 130 are coupled in series. In an embodiment, the second access diffusion region 214 and the second storage diffusion region 234 form a common diffusion region of the transistor. Other configurations for the series connection of the access and storage gates may also be useful.

A control capacitor 150 is disposed on the first well. The control capacitor includes a control gate 256 disposed on the substrate over the active capacitive region. The control gate includes a control gate electrode 258 over the control gate dielectric 257. For example, control gate electrode 258 can be a polysilicon control gate electrode, and control gate dielectric 257 can be a yttria control gate dielectric. Other types of gate electrodes or dielectric materials can also be used. In an embodiment, the control gate electrode is doped with a control or capacitance type dopant. For example, the control gate electrode is heavily doped with the same polarity type dopant as the control well. A capacitive contact plug 252 is disposed above the control well and adjacent to a side of the control gate. For example, the capacitive contact tether is removed from the side of the control gate. In an embodiment, the capacitive contact plug is coupled to an active capacitive region (or well pick-up region) between the unit isolation region and a side of the control gate. For example, the capacitive contact plug can be a conductive contact plug, such as a tungsten contact plug. Other types of conductive contact plugs can also be used. Capacitive contact plug 252 acts as a well tap for the well pick-up area of the capacitor. Although shown as a capacitive contact plug, it should be understood that this may be more A capacitive contact plug is coupled to the active capacitive region or the exposed top surface of the control well. Control well 209 acts as the second or well capacitance plate and the gate electrode 258 acts as the first or gate capacitance plate. In an embodiment, the capacitive gate electrode is doped prior to forming the capacitive contact plug. For example, a gate electrode layer disposed on the substrate is pre-doped with a control dopant and patterned to form the capacitive gate electrode.

In an embodiment, the control gate and the storage gate electrode 258 are co-coupled. In one embodiment, control gate 256 and storage gate 236 are formed with the same gate layer. For example, patterning the gate layer produces the control and storage gate. In such an example, control gate 256 and storage gate 236 are formed of the same material. For example, the control gate electrode and the dielectric layer are formed of the same material as the storage gate electrode and the dielectric layer. For example, the gate electrode is doped with a capacitance type dopant. Other dopant types for the gate electrode can also be provided. In one embodiment, the access, storage, and control gates are formed from the same gate layer. Other configurations of the gate can also be used. For example, the gate can be formed by different gate layers.

A metal halide contact (not shown) can be provided on the contact area of the memory cell. For example, the metal telluride contact can be a nickel or nickel based metal halide contact. Other suitable types of metal halide contact may also be used, including cobalt or cobalt based metal halide contacts. In an embodiment, a metal halide contact can be provided over the transistor diffusion region, the active capacitor region, and the access gate. A germanide block 261 is disposed over the storage and control gates. For example, the germanium block is a dielectric material. For example, yttrium oxide or tantalum nitride. Other types of bismuth block can also be used. Providing a germanide block on the storage and control gate prevents the germanide contact from forming over the gate. This improves data retention.

The first access diffusion region 212 is coupled to the SL of the memory device. The first storage diffusion region 232 is coupled to the BL of the memory device. Access gate 216 is coupled to the SGL of the memory device. Capacitive contact plug 252 is coupled to the CGL of the memory device. In some embodiments, control gate 256 is implemented as control capacitor 150. In some embodiments, the SGL is disposed along a first direction (eg, a word line (WL) direction) and the bit line is along a second direction (eg, a bit line that is perpendicular to the WL direction (BL) )))) setting. The CGL can be disposed along the direction of the word line, and the SL can be disposed along the direction of the bit line. Other configurations of BL, CGL, SGL, and SL can also be used. For example, the memory cells of the array can be coupled to a common SL (CSL) disposed along the direction of the word line.

The various wires of the memory unit can be placed in the metal hierarchy of the device. Wires placed in the same direction can be provided in the same metal level. For example, a wire disposed along the BL direction may be disposed at M _X , and a wire disposed along the WL direction may be disposed at M _{X+1 of} the device. Wires and other configurations of the metal hierarchy can also be used.

The described memory cells have improved or more efficient programs because of the increased capacitance coupling ratio. For example, the layout of the control gate (CG) and floating gate (FG) can be designed to have an area ratio to produce the desired capacitive coupling ratio. In some embodiments, the area ratio of CG:FG can be about 0.8:0.2. For example, the width of the floating gate (W) The length (L) may be about 0.4 x 0.28, and the W x L of the control gate may be about 1.6 x 0.84. Other CG:FG area ratios can also be provided. By providing a large area to the control gate, a medium bias can be generated on the capacitor well. For the high efficiency program of the memory cell, this bias voltage is transmitted to the floating gate. Reducing the high voltage required for this capacitive well also allows for the formation of smaller charge pumps. This further reduces the size of the device.

In some embodiments, the effect of reducing the voltage drop of the resistance and thereby improving process robustness can be achieved by providing a plurality of contacts (eg, capacitive contact plugs) coupled to the well capacitor plates of the capacitor. For example, one or more contact pins can be disposed adjacent to the control gate to electrically couple the well capacitance plate to the CGL. The number of contact plugs may depend on the perimeter of the control gate, the size of the active capacitive region, and the size and spacing of the contacts. A larger number of contacts will reduce more resistance.

Figures 3a and 3b show schematic diagrams of an embodiment of an array 300 of memory cells. For example, portions of the array are shown as having four memory cells 100, such as those depicted in Figures 1 and 2a through 2c. Common components may not be described or described in detail. An array of memory cells can be formed on a substrate having first and second wells 209 and 207 disposed within HV well region 210. In some embodiments, the HV well region is surrounded by an isolation well 208 that is common to the memory array of the memory chip. In an embodiment, the first and second wells extend across a plurality of rows of interconnected memory cells of the array. For example, the first and second wells form a common first and second well of the memory array. Other configurations of the first and second wells can also be used.

As shown in Figure 3a, the memory cells are interconnected to form two rows connected by BL (BL0 and BL1) and SL (SL0 and SL1), and by SGL (SGL0 and SGL1) and CGL (CGL0 and CGL1). ) Two columns of connected memory cells. In an embodiment, the SLs (SL0 and SL1) of each row of memory cells are coupled to separate source terminals. For example, SL0 and SL1 are coupled to the first and second source terminals and BL0 and BL1 are coupled to the first and second terminals. The separate rows of coupled memory cells to separate (or dedicated) source terminations form an AND type array configuration. For example, the illustrated AND type array configuration has access and storage transistors coupled to each of the separate SL and BL terminals, respectively. Having an AND type array configuration within the array provides more reliable memory unit operation.

In other embodiments, the SL of each row of memory cells is coupled to a common source terminal. As shown in FIG. 3b, the SL of each row of the memory cells can be coupled to a common source terminal (CSL) disposed in the WL direction. The separation of the coupled storage cells to the common source termination forms a NOR type array configuration. The illustrated NOR type array configuration has an access transistor coupled to the CSL in a separate row, while the storage cell system in the separate row is coupled to a separate BL (or drain) terminal. Having a NOR type array configuration provides random access to the memory unit and reduces the footprint of the array. Other configurations of the array can also be used.

Although shown as a 2x2 portion of the array, it should be understood that the array can include numerous columns and rows. For example, the memory array can form a memory block.

In one embodiment, the figures of Figure 1 and Figures 2a to 2c The memory cell unit is for including a first type of transistor and a first type of capacitor. For example, the access and storage transistor is of the same polarity type as the control capacitor. In an embodiment, the first type is an n-type. For example, the memory cell is configured to have an n-type transistor and an n-type capacitor. In such an example, the transistor (or second) well 207 and the capacitor (or first) well 209 comprise dopants of the opposite polarity type. The transistor well includes a second polarity type or p-type dopant, and the control well includes a first polarity type or an n-type dopant. The transistor diffusion region is n-type. Further, the gate electrode is doped with a capacitance type dopant. For example, the gate electrode is doped with a first polarity type or an n-type dopant. Other gate configurations are also available.

For memory cells having a first type of transistor and capacitor, various modes of operation are described in Figures 4a through 4c. For example, the first type is an n-type. Table 1 below shows the various bias voltages used for program, erase, and read modes of operation for various terminals of the memory unit:

The values in Table 1 are tunneled to the program and erase operations using Fowler-Nordheim (FN). For example, the value is for an operating voltage _Vdd equal to about 5V. Other suitable voltage values can also be used.

The memory unit is operable in a Fowler-Nordhein (FN) tunneling program mode 400a as shown in Figure 4a. In order to implement the FN tunneling program operation, various selection (sel) signals for such program operations are provided for the various terminals of the selected memory unit. In this programming mode, an electronic carrier 465 is tunneled from the transistor well to the floating gate (FG). Other suitable types of program mode can also be used, such as channel hot electron (CHE) injection mode. For example, in the CHE program mode, an electronic carrier is injected from the transistor channel to the FG on the drain side.

The memory unit is operable in the FN tunneling erase mode 400b as shown in Figure 4b. In order to implement the FN tunneling erase mode, various sel signals for such erase operations are provided for various terminals of the selected memory unit. In the erase mode, the electronic carrier 465 is moved from the FG to the transistor well from the drain side of the gate. This erase mode enables erase operations of memory blocks or lines.

Regarding the read operation 400c, it is illustrated in Figure 4c. Various selections (sel) signals for read operations are provided at various terminals of the selected memory unit to affect the read operation.

Figure 5 shows a plan view of an embodiment of an array 500 of memory cells of a memory device. This memory unit is similar to that described in Figures 1 and 2a through 2c. Common components may not be described or described in detail. The memory unit 200 is shown as a non-volatile memory unit. For example, the memory unit is a non-volatile MTP memory unit. Such as As shown, the memory cell includes access and storage transistors 110 and 130 coupled in series, and control gate 256 is commonly coupled to storage gate 236 to generate a floating gate. The electro-optic system is disposed on the active transistor region and the control gate is disposed on the active capacitor region. An array of memory cells can be formed on the substrate having the isolation well, the HV well region, and the first and second wells.

In an embodiment, array 500 includes a plurality of memory cells arranged in opposite directions from one another. For example, the memory cells are mirror images of one another on the first and second sides and the memory cells are mirror images of each other on the top and bottom sides. In other embodiments, the memory unit can be placed along the Y or word line direction (eg, without mirroring). In one embodiment, the native layer 290 is disposed between the active transistor and the capacitive region in the substrate. For example, the native layer increases the breakdown voltage and improves the insulation between the transistor and the control well.

A plurality of memory cells can be interconnected by various lines to form an array. For example, memory cells can be interconnected by SGL and CGL to form columns of memory cells and interconnects by BL and SL to form rows of memory cells. Access to the memory unit can be achieved by applying appropriate signals to various lines or terminals of the memory unit. A bit sequence of the memory cell is achieved by FN tunneling to tunnel electrons from the transistor well into the floating gate. By tunneling FN electrons from the FG to the transistor well, block or row erase can be achieved from the drain side of the gate.

Figure 6 shows a process 600 for forming an embodiment of the memory cell described herein. In detail, process 600 illustrates an example The semiconductor fabrication process flows to form the memory cells described in Figures 1 and 2a through 2c. Common components may not be described or described in detail.

At step 602, the process of forming the device includes providing a substrate provided with one or more cells or device regions. For example, the substrate is lightly doped with a second polarity type dopant (eg, a p-type dopant). Substrates doped with other types of dopants or undoped substrates may also be provided. A device area can be isolated from other device areas by device isolation regions, such as shallow trench isolation (STI) regions. In an embodiment, the device isolation region defines an active region, such as the active transistor and the capacitive region. For example, the device isolation region isolates the transistor as well as the capacitive region and other device regions, such as HV, MV, and/or LV devices. In an embodiment, forming the device isolation region includes forming a recess in the substrate and forming an insulating layer filling the recess.

In an embodiment, the process flow may continue along arrow A to form a native layer prior to forming the isolation well in the substrate. In an alternate embodiment, the process flow can continue along arrow B to form the isolation well in the substrate without forming a native layer.

At step 604, a native layer is formed between the transistor and the capacitive region. The native layer can be disposed in the substrate below the isolation region of the device, as shown in Figure 2c. The native layer is an intrinsic doped layer introduced during the manufacturing process. In one embodiment, the fabrication process is designed to form a native layer as a barrier layer to maintain the original lightly doped portion of the substrate, which may form a heavily doped region during the logic (or main) process. For example, the fabrication process is designed to include maintaining the low doping concentration of the substrate region of the substrate 205 to form the native layer 290. Other suitable techniques for forming the native layer can also be used. The native layer includes a depth deeper than the isolated region of the device. For example, the device isolation region is disposed above the native layer. In one embodiment, the native layer is a lightly doped layer that protrudes below the device isolation region separating the first and second wells. For example, the native layer can be about 0.39 μιη wide. Other suitable sizes of the primary layer may also be useful. The native layer separates the bottom of the well that extends below the isolation zone of the device. The depth of the native layer can be about the depth of the first and/or second well. In the case where the native layer is present, the native layer increases the breakdown voltage and improves the insulation between the first and second wells.

At step 606, an isolation well is formed in the substrate. In one embodiment, the isolation well is a common isolation well surrounding the memory array of the memory chip. For example, the isolation well is a deep isolation well implanted to a depth below the isolation region of the device. Other methods of forming the isolation well can also be used. In one embodiment, for a second polarity type substrate, a first polarity type isolation well is formed. For example, for a p-type substrate, the isolation well is lightly doped with an n-type dopant. Other dopant concentrations as well as dopant types can also be used.

At step 608, an HV well region is formed in the isolation well in the substrate. For example, the isolation well is surrounding the HV well region. In an embodiment, the HV well region is a common HV well region surrounding an array of interconnected memory cells. For example, the HV well region is implanted to a depth that is shallower than the isolation well but deeper than the isolation region of the device. Other techniques for forming the HV well can also be used. In an embodiment, for In the case of an isolation well of the first polarity type, an HV well region of the second polarity type is formed. For example, for an n-type isolation well, the HV well region is lightly doped with a p-type dopant. Other dopant concentrations can also be used. The HV well area as well as other configurations of the isolation well can also be used.

At step 610, first and second well systems are formed within the HV well region. For example, the HV well region surrounds the first and second wells. The first well is formed in the active capacitor region and the second well is formed in the active transistor region. In one embodiment, the first and second wells are implanted to a depth that is shallower than the HV well but deeper than the isolation region of the device. For example, the first and second wells have approximately the same depth. It is also possible to provide first and second wells having different depths. Other techniques for forming the well can also be used. The first well is lightly doped with a control or capacitance type dopant, and the second well is doped with a transistor type dopant. Other dopant concentrations can also be used.

At step 612, a device gate is formed on the substrate. A gate dielectric layer is disposed on the substrate and across the device region to form a gate dielectric of various devices. For example, a hafnium oxide layer is formed on the substrate to form a gate dielectric layer. The gate dielectric can be defined in different thicknesses for different device regions. In an embodiment, a gate electrode layer (eg, a polysilicon layer) is disposed over the gate dielectric layer and patterned to form gate electrodes of the various devices. In an embodiment, the gate electrode layer is a doped polysilicon layer. For example, the gate electrode of the control gate is pre-doped with a control or capacitance type dopant to form the control gate. The gate electrode and the gate dielectric are patterned to form a device (eg, HV, MV, and/or LV) The gate of the device). The process can continue to form a memory unit, such as an MTP memory unit. In one embodiment, the memory unit is made of HV and/or MV devices. For example, the access and storage transistor is an MV device and the control capacitor is an HV device.

At step 614, a diffusion extension region is formed. In an embodiment, the LDD and the annular region are formed adjacent to a side of the gate of the transistor and extending below the gate. For example, a common implant mask is employed to form the LDD and the annular region. For example, the implant mask is used to form an annular region in a first implantation step, and a second step is performed to form an LDD region into the annular region to form an annular and LDD region of the transistor. Other suitable techniques may also be used to form the ring and LDD regions. It is also possible to provide the LDD region without having an annular region.

At step 616, a gate sidewall spacer is formed. A dielectric spacer layer can be disposed on the substrate and cover the device area. The dielectric spacer layer can be patterned to form a gate sidewall spacer. For example, the sidewall spacers overlap the LDD and the annular region. In an embodiment, the exposed substrate region adjacent to the sidewall spacer is heavily doped with a first or second polarity type dopant to form a transistor diffusion region. For example, the transistor diffusion region is implanted deeper into the LDD and the annular region and is approximately aligned to the gate sidewall spacer.

At step 618, a conductive contact plug is formed. In an embodiment, a capacitive contact plug is formed over the control well. For example, the capacitive contact plug can be formed using a single damascene process in a pre-metallized dielectric (PMD) layer (not shown) disposed on the substrate. Capacitor contact pin coupling The active capacitive region is between the device isolation region and the capacitor. For example, the capacitive contact plug is disposed adjacent to a side of the control gate. Other configurations of capacitive contact plugs may also be useful. In an embodiment, the capacitive contact plug is a conductive contact plug. For example, the capacitive contact plug can be a tungsten contact plug. Other types of conductive contact plugs may also be useful. The capacitive contact tether acts as a well tap for the well pick-up area of the capacitor.

The process continues to complete the formation of the device. The process can include forming an interlayer dielectric (ILD) layer, metal telluride contacts to the termination of the memory cell, conductive contacts, and one or more interconnect levels, final passivation, dicing, assembly, and Package. Other processes to complete the formation of the device may also be included. Other suitable processes can also be used to form the apparatus as shown in Figures 2a through 2c.

The inventive concept of the invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the foregoing embodiments are to be considered in all aspects illustrative illustrative The scope of the invention is to be construed as being limited by the scope of the claims

100‧‧‧ memory unit

110‧‧‧First transistor

112‧‧‧First access diffusion area

114‧‧‧Second access diffusion area

116‧‧‧ access gate

130‧‧‧Second transistor

132‧‧‧First storage diffusion area

134‧‧‧Second storage diffusion area

136‧‧‧Storage gate

150‧‧‧Control Capacitor

152‧‧‧Capacitive contact plug

156‧‧‧Control gate

Claims (18)

A non-volatile multi-programmable memory unit comprising: a substrate provided with an isolation well; a high voltage well region disposed in the isolation well, wherein the high voltage well region is a common well region of the memory array; a first well and a second well in the high voltage well region; a first transistor having a selected gate adjacent to each other and disposed above the second well; and a second transistor having a floating gate, the electricity The crystal includes first and second diffusion regions disposed adjacent to sides of the gate; and a control gate disposed over the first well, wherein the control gate is coupled to the floating gate, and the control gate The pole and floating gates comprise the same gate layer extending across the first well and the second well, and the control gate includes a capacitor. The memory unit of claim 1, wherein the first well is of a first polarity type and the second well is of a second polarity type different from the first polarity type. The memory unit of claim 2, wherein the first well is an n-type well and the second well is a p-type well, wherein each of the floating gate and the selection gate comprises An n-type metal oxide semiconductor, and wherein the control gate comprises an n-type capacitor. The memory unit of claim 3, wherein the memory unit is compliant by a Fowler-Nordheim (FN) tunneling effect Program. The memory unit of claim 3, wherein the memory unit is erasable by a Fowler-Nordheim (FN) tunneling effect. The memory unit of claim 3, wherein the memory unit comprises a capacitive contact plug coupled to the first well. The memory unit of claim 6, wherein the high voltage well region comprises a depth deeper than the first well and the second well. The memory unit of claim 7, wherein the isolation well comprises a depth deeper than the high voltage well region. The memory unit of claim 8, wherein the high voltage well region is of a second polarity type and the isolation well is of a first polarity type different from the second polarity type. The memory unit of claim 1, wherein the first well is of a first polarity type and the high voltage well region is of a second polarity type different from the first polarity type. The memory unit of claim 1, wherein the memory unit comprises a native layer disposed in the substrate between the first well and the second well. A non-volatile multiple-programmable memory unit includes: a substrate provided with a first isolation well and a second isolation well, wherein the second isolation well is disposed within the first isolation well, and wherein the second The isolation well is a common second isolation well surrounding the memory unit of the memory array; a first well and a second well disposed in the second isolation well; a first transistor having a selection gate adjacent to each other and disposed above the second well; and a second transistor having a floating gate, The transistor includes first and second diffusion regions disposed adjacent to sides of the gate; and a control gate disposed over the first well, wherein the control gate is coupled to the floating gate, and the control gate The pole and floating gates comprise the same gate layer extending across the first well and the second well. The memory unit of claim 12, wherein the first well comprises a first polarity type and the second well is a second polarity type different from the first polarity type. The memory unit of claim 12, wherein the memory array comprises an AND type array arrangement. The memory unit of claim 12, wherein the memory array comprises a NOR type array arrangement. The memory unit of claim 12, wherein the memory unit comprises a native layer between the first well and the second well. The memory unit of claim 12, wherein: the first isolation well comprises a first polarity type; and the second isolation well comprises a second polarity type. A method for forming a non-volatile multi-programmable memory unit, comprising: providing a substrate; forming a first isolation well and a second isolation well in the substrate; Forming a first well and a second well in the second isolation well, wherein the second isolation well is a common second isolation well surrounding the memory unit of the memory array; forming a first transistor having a selected gate and a second transistor having a floating gate adjacent to and above the second well, the transistor including first and second diffusion regions formed adjacent sides of the gate, wherein the first transistor And the second transistor is coupled in series, and the first transistor and the second transistor share a common second diffusion region; and a control gate is formed over the first well, wherein the control gate is coupled to the floating gate And the control gate and the floating gate comprise the same gate layer extending across the first well and the second well, and the control gate comprises a capacitor.