TWI594401B - Simple and cost-free mtp structure - Google Patents

Simple and cost-free mtp structure Download PDF

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TWI594401B
TWI594401B TW104112181A TW104112181A TWI594401B TW I594401 B TWI594401 B TW I594401B TW 104112181 A TW104112181 A TW 104112181A TW 104112181 A TW104112181 A TW 104112181A TW I594401 B TWI594401 B TW I594401B
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well
gate
memory unit
transistor
isolation
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TW201605025A (en
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達尼 帕克奇摩 史摩
仰偉 傅
賓德爾 史葛
孫遠
馬恩 葛尤 安葛 馬恩
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格羅方德半導體私人有限公司
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Description

簡單及免費的多次可程式結構 Simple and free multiple programmable structure

本發明關於一種非揮發性記憶體單元及其形成方法。 The present invention relates to a non-volatile memory unit and a method of forming the same.

近年來,多次可程式(multi-time programmable,MTP)記憶體被引入以在一些對於數位及類比設計上需客製化的應用方面有實益用途。這些應用包括數據加密、基準修調(reference trimming)、製造標識(ID)、安全ID、以及其他種種應用。然而,MTP記憶體的納入通常也產生一些額外製程步驟的費用。製造MTP記憶體的一些現有方法往往有緩慢存取時間、較小耦合比及/或大單元尺寸的問題。一些現有方法對於抹除運算係採用了能帶對能帶隧穿熱電洞(band-to-band tunneling hot hole,BBHH),但是這需要高接合能帶電壓以及更多製程步驟。其他現有方法需要額外的耦合抹除閘極以及耦合電容,因而需要更多面積。 In recent years, multi-time programmable (MTP) memory has been introduced for beneficial use in applications that require customization for digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security IDs, and more. However, the inclusion of MTP memory typically also incurs the cost of some additional process steps. Some existing methods of fabricating MTP memory tend to have slow access times, small coupling ratios, and/or large cell sizes. Some existing methods use a band-to-band tunneling hot hole (BBHH) for the erase operation, but this requires a high junction band voltage and more process steps. Other existing methods require additional coupling erase gates and coupling capacitors, requiring more area.

因此,需要一種簡單且免費的多次可程式結構以製造具有標準互補金屬氧化半導體(CMOS)平臺的非揮發性記憶體單元。 Therefore, there is a need for a simple and free multiple programmable structure to fabricate non-volatile memory cells with standard complementary metal oxide semiconductor (CMOS) platforms.

實施例一般關於一種簡單且免費的多次可程式結構。在一實施例中,非揮發性MTP記憶體單元包括備有隔離井的基板、設置於該隔離井內的高電壓(HV)井區域以及設置在該基板中的該HV井區域內的第一與第二井。具有選擇閘極的第一電晶體以及具有浮動閘極的第二電晶體位置彼此相鄰並且係設置在該第二井之上。所述電晶體包括設置於鄰近所述閘極的側邊的第一及第二擴散區域。控制閘極設置於該第一井之上並耦合至該浮動閘極。該控制閘極以及浮動閘極包括延伸跨過該第一及第二井的相同閘極層。該控制閘極包括電容。 Embodiments are generally directed to a simple and free multiple programmable structure. In one embodiment, the non-volatile MTP memory cell includes a substrate provided with an isolation well, a high voltage (HV) well region disposed within the isolation well, and a first region within the HV well region disposed in the substrate With the second well. A first transistor having a select gate and a second transistor having a floating gate are adjacent to each other and disposed above the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. A control gate is disposed over the first well and coupled to the floating gate. The control gate and the floating gate include the same gate layer extending across the first and second wells. The control gate includes a capacitor.

在另外的實施例中,係公開一種非揮發性MTP記憶體單元。該記憶體單元包括備有第一及第二隔離井的基板。該第二隔離井設置於該第一隔離井內。第一及第二井設置在該第一隔離井內。具有選擇閘極的第一電晶體以及具有浮動閘極的第二電晶體位置彼此相鄰並且係設置於該第二井之上。所述電晶體包括設置於鄰近所述閘極的側邊的第一及第二擴散區域。控制閘極設置於該第一井之上並耦合至該浮動閘極。該控制閘極以及浮動閘極包括延伸跨過該第一及第二井的相同閘極層。 In other embodiments, a non-volatile MTP memory unit is disclosed. The memory unit includes a substrate provided with first and second isolation wells. The second isolation well is disposed in the first isolation well. First and second wells are disposed within the first isolation well. A first transistor having a select gate and a second transistor having a floating gate are adjacent to each other and disposed above the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. A control gate is disposed over the first well and coupled to the floating gate. The control gate and the floating gate include the same gate layer extending across the first and second wells.

在又一另外的實施例中,公開一種用於形成非揮發性MTP記憶體單元的方法。提供基板並且在該基板中形成第一及第二隔離井。在該第二隔離井內形成第一及第二井。具有選擇閘極的第一電晶體以及具有浮動閘極 的第二電晶體位置彼此相鄰並且係形成在該第二井之上。所述電晶體包括設置於鄰近所述閘極的側邊的第一及第二擴散區域。該第一及第二電晶體以串聯耦合並且分享共同第二擴散區域。控制閘極係形成在該第一井之上並且耦合至該浮動閘極。該控制及浮動閘極包括延伸跨過該第一及第二井的相同閘極層。該控制閘極包括電容。 In yet another embodiment, a method for forming a non-volatile MTP memory cell is disclosed. A substrate is provided and first and second isolation wells are formed in the substrate. First and second wells are formed in the second isolation well. First transistor with selective gate and floating gate The second transistor locations are adjacent to one another and are formed over the second well. The transistor includes first and second diffusion regions disposed adjacent sides of the gate. The first and second transistors are coupled in series and share a common second diffusion region. A control gate is formed over the first well and coupled to the floating gate. The control and floating gates include the same gate layer extending across the first and second wells. The control gate includes a capacitor.

本文所公開的實施例的這些及其他優點和特徵,透過參考以下描述以及所附圖式將變得顯而易見。更進一步來說,應理解到本文描述的各種實施例的優點並不相互排斥,並且可存在於各種實施例以及置換中。 These and other advantages and features of the embodiments disclosed herein will be apparent from the description and appended claims. Further, it is to be understood that the advantages of the various embodiments described herein are not mutually exclusive and may be present in various embodiments and permutations.

100‧‧‧記憶體單元 100‧‧‧ memory unit

110‧‧‧第一電晶體 110‧‧‧First transistor

112‧‧‧第一存取擴散區域 112‧‧‧First access diffusion area

114‧‧‧第二存取擴散區域 114‧‧‧Second access diffusion area

116‧‧‧存取閘極 116‧‧‧ access gate

130‧‧‧第二電晶體 130‧‧‧Second transistor

132‧‧‧第一儲存擴散區域 132‧‧‧First storage diffusion area

134‧‧‧第二儲存擴散區域 134‧‧‧Second storage diffusion area

136‧‧‧儲存閘極 136‧‧‧Storage gate

150‧‧‧控制電容 150‧‧‧Control Capacitor

152‧‧‧電容接觸栓 152‧‧‧Capacitive contact plug

156‧‧‧控制閘極 156‧‧‧Control gate

200‧‧‧記憶體單元 200‧‧‧ memory unit

205‧‧‧基板 205‧‧‧Substrate

207‧‧‧第二井 207‧‧‧Second well

208‧‧‧隔離井 208‧‧‧Isolation well

209‧‧‧第一井 209‧‧‧First Well

210‧‧‧HV井區域 210‧‧‧HV well area

212‧‧‧第一存取擴散區域 212‧‧‧First access diffusion area

214‧‧‧第二存取擴散區域 214‧‧‧Second access diffusion area

216‧‧‧存取閘極 216‧‧‧ access gate

220‧‧‧主動電容區域 220‧‧‧Active Capacitor Area

222‧‧‧主動電晶體區域 222‧‧‧Active transistor area

232‧‧‧第一儲存擴散區域 232‧‧‧First storage diffusion area

234‧‧‧第二儲存擴散區域 234‧‧‧Second storage diffusion area

236‧‧‧儲存閘極 236‧‧‧Storage gate

252‧‧‧電容接觸栓 252‧‧‧Capacitive contact plug

256‧‧‧控制閘極 256‧‧‧Control gate

257‧‧‧閘極介電質 257‧‧‧gate dielectric

258‧‧‧閘電極 258‧‧ ‧ gate electrode

261‧‧‧矽化物阻塊 261‧‧‧ Telluride block

280‧‧‧單元隔離區域 280‧‧‧Unit isolation area

284‧‧‧單元區域 284‧‧‧Unit area

290‧‧‧原生層 290‧‧‧primary layer

300‧‧‧記憶體單元的陣列 300‧‧‧Array of memory cells

400a‧‧‧FN隧穿程式模式 400a‧‧‧FN tunneling mode

400b‧‧‧FN隧穿抹除模式 400b‧‧‧FN tunneling erase mode

400c‧‧‧讀取操作 400c‧‧‧Read operation

500‧‧‧記憶體單元的陣列 500‧‧‧Array of memory cells

600‧‧‧製程 600‧‧‧Process

602至618‧‧‧製程步驟 602 to 618‧‧‧ Process steps

在圖式中,相同的符號一般表示於各個不同觀點中相同的部分。並且,圖式並不需要按比例,相反地在圖示說明各種實施例的原理時一般會放入重點。在以下描述中,係參考以下圖示描述了本發明的各種實施例,其中:第1圖顯示記憶體單元的示意圖;第2a圖顯示記憶體單元之實施例的俯視圖,以及第2b及2c圖顯示該記憶體單元之實施例的各種剖面圖;第3a及3b圖顯示記憶體單元的陣列之實施例的示意圖;第4a至4c圖顯示記憶體單元的各種操作;第5圖顯示記憶體單元的實施例之陣列的 平面圖;以及第6圖顯示用於形成記憶體單元之實施例的製程。 In the drawings, the same symbols generally indicate the same parts in the various different aspects. Moreover, the drawings are not necessarily to scale unless otherwise In the following description, various embodiments of the invention are described with reference to the following drawings in which: FIG. 1 shows a schematic diagram of a memory unit; FIG. 2a shows a top view of an embodiment of a memory unit, and FIGS. 2b and 2c Various cross-sectional views showing an embodiment of the memory cell; Figures 3a and 3b show schematic views of an embodiment of an array of memory cells; Figures 4a through 4c show various operations of the memory cell; and Figure 5 shows memory cells Array of embodiments Plan view; and Figure 6 shows a process for forming an embodiment of a memory cell.

實施例一般關於半導體裝置。具體而言,一些實施例關於記憶體裝置,例如非揮發性記憶體(NVM)裝置。舉例來說,這類的記憶體裝置可併入至獨立記憶體裝置,例如USB或其他類型的可攜式儲存單元,或IC,例如微控制器或晶片系統(system on chips,SoCs)。舉例來說,該裝置或IC可被併入或與消費類電子產品或相關的其他類型裝置一起使用。 Embodiments are generally directed to semiconductor devices. In particular, some embodiments are directed to memory devices, such as non-volatile memory (NVM) devices. For example, such memory devices can be incorporated into a stand-alone memory device, such as a USB or other type of portable storage unit, or an IC, such as a microcontroller or system on chips (SoCs). For example, the device or IC can be incorporated or used with consumer electronics or other types of devices in question.

第1圖顯示記憶體單元100的實施例的示意圖。在一實施例中,該記憶體單元為非揮發性(NV)多次可程式(MTP)記憶體單元100。如第1圖所示,記憶體單元100包括第一電晶體110、第二電晶體130以及控制電容150。在一實施例中,該第二電晶體作為儲存元件且該控制電容作為電壓耦合元件。舉例來說,該第一及第二電晶體為金屬氧化半導體(MOS)電晶體。電晶體包括介於第一及第二擴散區域之間的閘極。電晶體的擴散區域為具有第一極性類型摻雜物的重摻雜區域。該極性類型決定電晶體的類型。舉例來說,該第一極性對於n型電晶體來說可為n型,或對於p型電晶體來說可為p型。 FIG. 1 shows a schematic diagram of an embodiment of a memory unit 100. In one embodiment, the memory unit is a non-volatile (NV) multiple programmable (MTP) memory unit 100. As shown in FIG. 1, the memory unit 100 includes a first transistor 110, a second transistor 130, and a control capacitor 150. In an embodiment, the second transistor acts as a storage element and the control capacitor acts as a voltage coupling element. For example, the first and second transistors are metal oxide semiconductor (MOS) transistors. The transistor includes a gate between the first and second diffusion regions. The diffusion region of the transistor is a heavily doped region having a dopant of the first polarity type. This type of polarity determines the type of transistor. For example, the first polarity can be n-type for an n-type transistor or p-type for a p-type transistor.

在一實施例中,電晶體擴散區域可包括擴散延伸區域(未圖示)。舉例來說,電晶體擴散區域可包括 延伸超過該擴散區域而與該電晶體閘極的一部分重疊之輕摻雜擴散區域。擴散延伸區域可包括輕摻雜汲極(LDD)延伸區域以及環狀(halo)區域。舉例來說,該LDD延伸區域與該環狀區域為相反摻雜。舉例來說,對於第一類型電晶體而言該環狀區域包括第二極性類型摻雜物,而該LDD延伸區域對於第一類型電晶體而言則包括第一極性類型摻雜物。擴散延伸區域也可使用其他配置。舉例來說,可使用僅具有LDD延伸區域而無環狀區域的擴散延伸區域。 In an embodiment, the transistor diffusion region may include a diffusion extension region (not shown). For example, the transistor diffusion region can include A lightly doped diffusion region that extends beyond the diffusion region and overlaps a portion of the transistor gate. The diffusion extension region may include a lightly doped drain (LDD) extension region and a halo region. For example, the LDD extension region is oppositely doped with the annular region. For example, for a first type of transistor, the annular region includes a second polarity type dopant, and the LDD extension region includes a first polarity type dopant for the first type of transistor. Other configurations can be used for the diffusion extension area. For example, a diffusion extension region having only an LDD extension region and no annular region can be used.

閘極包括閘電極以及閘極介電質。第一電晶體110作為存取電晶體而第二電晶體130作為儲存電晶體。舉例來說,該存取電晶體110包括第一存取擴散區域112、第二存取擴散區域114以及存取閘極116;而儲存電晶體130包括第一儲存擴散區域132、第二儲存擴散區域134以及儲存閘極136。存取閘極116可稱作為選擇閘極,以及儲存閘極136可稱作為浮動閘極。 The gate includes a gate electrode and a gate dielectric. The first transistor 110 serves as an access transistor and the second transistor 130 serves as a storage transistor. For example, the access transistor 110 includes a first access diffusion region 112, a second access diffusion region 114, and an access gate 116. The storage transistor 130 includes a first storage diffusion region 132 and a second storage diffusion. Region 134 and storage gate 136. Access gate 116 can be referred to as a select gate, and storage gate 136 can be referred to as a floating gate.

在一實施例中,該控制電容150為MOS電容。舉例來說,該控制電容150包括具有控制閘電極以及控制閘極介電質的控制閘極156。控制閘極156形成控制電容150。該控制電容包括由介電質層所分開的第一及第二電容極板。舉例來說,該控制閘電極作為該第一(或閘電容)極板,而控制井209(將在之後描述)作為該第二(或井)電容極板。舉例來說,設置在該第二電容極板之上的介電質層將該第一及第二電容極板分離。電容接觸栓152(或將在之後描述之井分接頭(well tap))設置在該基板之上並耦 合至主動電容(或井拾取(well pickup)區域)以提供偏壓給該控制井。在一實施例中,該電容接觸栓設置於鄰近該控制電容。舉例來說,該電容接觸栓設置於鄰近該控制閘極的側邊。該電容接觸栓提供導電連接至該主動電容區域。在一實施例中,該控制閘極係耦合至該儲存閘極。具例來說,該閘極係由共閘極導體所形成。該控制電容隔離儲存閘極136,使其成為浮動閘極。 In an embodiment, the control capacitor 150 is a MOS capacitor. For example, the control capacitor 150 includes a control gate 156 having a control gate electrode and a control gate dielectric. Control gate 156 forms control capacitor 150. The control capacitor includes first and second capacitor plates separated by a dielectric layer. For example, the control gate electrode acts as the first (or gate capacitance) plate and the control well 209 (described later) acts as the second (or well) capacitor plate. For example, a dielectric layer disposed over the second capacitor plate separates the first and second capacitor plates. A capacitive contact plug 152 (or a well tap described later) is disposed on the substrate and coupled The active capacitor (or well pickup region) is coupled to provide a bias to the control well. In an embodiment, the capacitive contact plug is disposed adjacent to the control capacitor. For example, the capacitive contact plug is disposed adjacent to a side of the control gate. The capacitive contact plug provides an electrically conductive connection to the active capacitive region. In an embodiment, the control gate is coupled to the storage gate. For example, the gate is formed by a common gate conductor. The control capacitor isolates the storage gate 136 to become a floating gate.

該存取及儲存電晶體110和130以串聯耦合。舉例來說,該第二存取擴散區域以及第二儲存擴散區域114和134係形成該電晶體的共同擴散區域。至於該控制閘極156及儲存閘極136,它們為共同耦合。舉例來說,係提供共閘電極以及閘極介電質以形成該儲存閘極及控制閘極。該儲存及控制閘極的其他配置也可能是有用的。藉由共同耦合該控制及儲存閘極156和136,係產生浮動儲存閘極。 The access and storage transistors 110 and 130 are coupled in series. For example, the second access diffusion region and the second storage diffusion regions 114 and 134 form a common diffusion region of the transistor. As for the control gate 156 and the storage gate 136, they are co-coupled. For example, a common gate electrode and a gate dielectric are provided to form the storage gate and the control gate. Other configurations of the storage and control gates may also be useful. By collectively coupling the control and storage gates 156 and 136, a floating storage gate is created.

該第一或存取電晶體110的第一存取擴散區域112耦合至該記憶體裝置的源極線(SL)。該第二或儲存電晶體130的第一儲存擴散區域132耦合至該記憶體裝置的位元線(BL)。記憶體單元100的選擇閘極、或是第一電晶體110的存取閘極116係耦合至該記憶體裝置的選擇閘極線(SGL)。該控制電容的電容接觸栓152耦合該記憶體裝置的控制閘極線(CGL)。在一實施例中,該SGL係沿著第一方向(例如字元線方向)設置,而該BL係沿著第二方向(例如位元線方向)設置。舉例來說,該第一及第二方向為 互相正交。至於CGL,其係沿著該字元線方向設置且SL係沿著該位元線方向設置。也可使用BL、CGL、SGL以及SL的其他配置。舉例來說,陣列的該記憶體單元也可耦合至沿著字元線方向設置的共同SL(CSL)。 The first access diffusion region 112 of the first or access transistor 110 is coupled to a source line (SL) of the memory device. The first storage diffusion region 132 of the second or storage transistor 130 is coupled to a bit line (BL) of the memory device. The select gate of the memory cell 100, or the access gate 116 of the first transistor 110, is coupled to a select gate line (SGL) of the memory device. The capacitive contact plug 152 of the control capacitor is coupled to the control gate line (CGL) of the memory device. In an embodiment, the SGL is disposed along a first direction (eg, a word line direction) and the BL is disposed along a second direction (eg, a bit line direction). For example, the first and second directions are Orthogonal to each other. As for the CGL, it is disposed along the direction of the word line and the SL is disposed along the direction of the bit line. Other configurations of BL, CGL, SGL, and SL can also be used. For example, the memory cells of the array can also be coupled to a common SL (CSL) disposed along the direction of the word line.

第2a圖顯示記憶體單元的各種實施例的俯視圖,以及第2b圖顯示一實施例的記憶體單元的剖面圖,而第2c圖顯示記憶體單元的另一實施例的剖面圖。舉例來說,這些剖面圖係沿著該記憶體單元的A-A’、B-B’以及C-C’線段。該記憶體裝置包括記憶體單元200。該記憶體單元係與在第1圖中所描述的類似。常見的元件可能不被描述或詳細描述。所顯示的記憶體單元200為NVM單元。舉例來說,該記憶體單元為非揮發性MTP記憶體單元。 Fig. 2a shows a top view of various embodiments of the memory cell, and Fig. 2b shows a cross-sectional view of the memory cell of an embodiment, and Fig. 2c shows a cross-sectional view of another embodiment of the memory cell. For example, these cross-sectional views are along the A-A', B-B', and C-C' segments of the memory cell. The memory device includes a memory unit 200. This memory unit is similar to that described in Figure 1. Common components may not be described or described in detail. The displayed memory unit 200 is an NVM unit. For example, the memory unit is a non-volatile MTP memory unit.

該裝置可包括具有不同摻雜物濃度的摻雜區域。舉例來說,該裝置可包括重摻雜(x+)、中等摻雜(x)以及輕摻雜(x-)區域,其中x可為p型或n型摻雜物的極性類型。輕摻雜區域可具有大約1E11-1E12 cm-2的摻雜物濃度,中等摻雜區域可具有大約1E12-1E13 cm-2的摻雜物濃度,以及重摻雜區域可具有大約1E13-1E14 cm-2的摻雜物濃度。也可對不同類型的摻雜區域提供其他的摻雜物濃度。舉例來說,該摻雜物濃度範圍根據技術節點可以有所變化。P型摻雜物可包括硼(B)、氟(F)、鋁(Al)、銦(In)或它們的組合,而n型摻雜物可包括磷(P)、砷(As)、銻(Sb)或它們的組合。 The device can include doped regions having different dopant concentrations. For example, the device can include heavily doped (x + ), moderately doped (x), and lightly doped (x ) regions, where x can be a polar type of p-type or n-type dopant. The lightly doped region may have a dopant concentration of about 1E11-1E12 cm -2 , the medium doped region may have a dopant concentration of about 1E12-1E13 cm -2 , and the heavily doped region may have about 1E13 - 1E14 cm -2 dopant concentration. Other dopant concentrations can also be provided for different types of doped regions. For example, the dopant concentration range can vary depending on the technology node. The P-type dopant may include boron (B), fluorine (F), aluminum (Al), indium (In), or a combination thereof, and the n-type dopant may include phosphorus (P), arsenic (As), bismuth. (Sb) or a combination thereof.

該裝置設置於基板205上。該基板為半導體 基板,例如矽基板。其他類型的半導體基板也可能是有用的。在一實施例中,基板205為輕摻雜基板。在一實施例中,該基板係以第二極性類型的摻雜物輕摻雜。舉例來說,該基板為輕摻雜p型(p-)基板。也可以提供摻雜其他類型的摻雜物的基板或未摻雜的基板。 The device is disposed on the substrate 205. The substrate is a semiconductor substrate such as a germanium substrate. Other types of semiconductor substrates may also be useful. In an embodiment, the substrate 205 is a lightly doped substrate. In an embodiment, the substrate is lightly doped with a dopant of a second polarity type. For example, the substrate is lightly doped p-type (p -) of the substrate. Substrates or other undoped substrates doped with other types of dopants may also be provided.

單元區域284係提供於該基板中。舉例來說,該單元區域為設置該記憶體單元的單元區域。儘管顯示為一個單元區域,該裝置可包括多個具有互連以形成記憶體陣列的記憶體單元之單元區域。此外,根據裝置或IC的類型,該基板可包括其他類型的裝置區域。舉例來說,該裝置可包括用於高電壓(HV)、中等或中電壓(MV)及/或低電壓(LV)裝置的裝置區域。 A cell region 284 is provided in the substrate. For example, the unit area is a unit area in which the memory unit is disposed. Although shown as a unit area, the apparatus can include a plurality of unit areas having memory cells interconnected to form a memory array. Further, depending on the type of device or IC, the substrate can include other types of device regions. For example, the device can include a device area for high voltage (HV), medium or medium voltage (MV) and/or low voltage (LV) devices.

該單元區域包括第一及第二井209及207。該第一井係作為對於控制閘極的控制井而該第二井係作為電晶體井。舉例來說,該電晶體井係作為用於存取(或選擇)及儲存電晶體110及130的井。在一實施例中,該控制閘極包括控制電容150。該控制電容可為MOS電容。也可使用其他類型的控制閘極。 The unit area includes first and second wells 209 and 207. The first well system acts as a control well for the control gate and the second well system acts as a transistor well. For example, the transistor well is used as a well for accessing (or selecting) and storing transistors 110 and 130. In an embodiment, the control gate includes a control capacitor 150. The control capacitor can be a MOS capacitor. Other types of control gates can also be used.

如圖所示,該井係設置為相鄰彼此。第一井209容納該控制電容及第二井207容納該存取及儲存電晶體。該第一(或控制)井包括電容類型摻雜物及該第二(或電晶體)井包括電晶體井類型摻雜物。在一實施例中,該控制井為輕摻雜井。舉例來說,該控制井的摻雜物濃度可為大約1E11-1E12 cm-2。關於該電晶體井,其可為輕到中度 摻雜井。舉例來說,該電晶體井的摻雜物濃度可為大約1E12-1E13 cm-2。也可使用其他控制及/或電晶體井的摻雜物濃度。該第一及第二井可作為分別用於HV及MV裝置的裝置井。舉例來說,該第一井為充分摻雜以形成HV裝置井,而該第二井為充分摻雜以形成MV裝置井。 As shown, the wells are placed adjacent to each other. The first well 209 houses the control capacitor and the second well 207 houses the access and storage transistors. The first (or control) well includes a capacitance type dopant and the second (or transistor) well includes a transistor well type dopant. In an embodiment, the control well is a lightly doped well. For example, the control well may have a dopant concentration of about 1E11-1E12 cm -2 . Regarding the transistor well, it can be a light to moderate doped well. For example, the transistor well can have a dopant concentration of about 1E12-1E13 cm -2 . Other control and/or dopant concentrations of the transistor wells can also be used. The first and second wells can be used as device wells for HV and MV devices, respectively. For example, the first well is sufficiently doped to form an HV device well while the second well is sufficiently doped to form an MV device well.

從該基板的表面算起,第一井209包括深度DW1以及第二井207包括深度DW2。儘管圖式說明從該基板的表面算起該第一及第二井具有大約相同的的深度尺寸,應理解到該第一及第二井也可包括不同的深度尺寸。舉例來說,該第一井的DW1可不同於該第二井的DW2From the surface of the substrate, the first well 209 includes a depth D W1 and the second well 207 includes a depth D W2 . Although the figures illustrate that the first and second wells have approximately the same depth dimension from the surface of the substrate, it should be understood that the first and second wells may also include different depth dimensions. For example, D W1 of the first well may be different from D W2 of the second well.

該控制井摻雜物的極性類型可取決於該控制閘極的極性類型。在一實施例中,該控制井的極性類型取決於該控制電容的極性類型。在控制電容的例子中,該控制井為與該電容類型相同的極性。舉例來說,對於p型MOS電容而言該控制井摻雜物為p型,或對於n型MOS電容而言該控制井摻雜物為n型。關於該電晶體井摻雜物,其為與該電晶體相反的極性類型。在一實施例中,對於具有第一極性類型摻雜物的第一類型電晶體而言,該電晶體井摻雜物為第二極性類型的摻雜物。舉例來說,對於n型電晶體而言,該電晶體井摻雜物為p型。在一實施例中,該電晶體井的極性類型與該控制井的極性類型相反。舉例來說,提供第二極性類型的電晶體井給第一極性類型的控制井。該第一極性類型可為n型以及該第二極性類型可為p型。也可使用電晶體及控制井的其他配置。舉例來 說,該第一極性類型可為p型以及該第二極性類型可為n型。 The type of polarity of the control well dopant may depend on the type of polarity of the control gate. In an embodiment, the polarity of the control well depends on the polarity type of the control capacitor. In the example of controlling the capacitance, the control well is of the same polarity as the capacitance type. For example, the control well dopant is p-type for a p-type MOS capacitor or n-type for an n-type MOS capacitor. Regarding the transistor well dopant, it is of the opposite polarity type to the transistor. In an embodiment, for a first type of transistor having a first polarity type dopant, the transistor well dopant is a dopant of a second polarity type. For example, for an n-type transistor, the transistor well dopant is p-type. In an embodiment, the polarity type of the transistor well is opposite to the polarity type of the control well. For example, a transistor of the second polarity type is provided to a control well of the first polarity type. The first polarity type can be an n-type and the second polarity type can be a p-type. Other configurations of the transistor and control well can also be used. For example Said that the first polarity type can be p-type and the second polarity type can be n-type.

隔離井208可提供於該基板中,如第2b及2c圖所示。該隔離井可為設置於該第一及第二井之下的深隔離井。在一實施例中,該隔離井為記憶體晶片的共同隔離井。舉例來說,該隔離井環繞記憶體晶片的多個記憶體陣列。該隔離井包括隔離井摻雜物。在一實施例中,該隔離井為以隔離井摻雜物輕摻雜。舉例來說,該隔離井摻雜物的極性類型與該基板類型極性類型相反。在一實施例中,對於第二極性類型基板而言,該隔離井摻雜物為第一極性類型摻雜物以。舉例來說,提供n型隔離井給p型基板。也可使用隔離井以及基板的其他配置。隔離井208用以將該第一及第二井與該基板隔離以改善該記憶體裝置的噪聲抗擾性(immunity)。隔離井208從該基板的表面算起係具有深度DN。隔離井208可稱為第一隔離井。 Isolation well 208 can be provided in the substrate as shown in Figures 2b and 2c. The isolation well may be a deep isolation well disposed below the first and second wells. In one embodiment, the isolation well is a common isolation well for a memory wafer. For example, the isolation well surrounds a plurality of memory arrays of a memory chip. The isolation well includes an isolation well dopant. In an embodiment, the isolation well is lightly doped with an isolation well dopant. For example, the isolation well dopant has a polarity type that is opposite to the substrate type polarity type. In an embodiment, for the second polarity type substrate, the isolation well dopant is a first polarity type dopant. For example, an n-type isolation well is provided to the p-type substrate. Isolation wells and other configurations of the substrate can also be used. The isolation well 208 is used to isolate the first and second wells from the substrate to improve the noise immunity of the memory device. The isolation well 208 has a depth D N from the surface of the substrate. The isolation well 208 can be referred to as a first isolation well.

在一些實施例中,HV井區域210可提供於該基板中的隔離井208內。在一實施例中,該HV井區域環繞該第一及第二井。舉例來說,該HV井區域將該第一及第二井209和207與隔離井208分離。在一實施例中,該HV井區域為記憶體陣列的共同HV井區域。舉例來說,該HV井區域環繞記憶體陣列的多個記憶體單元。該HV井區域包括HV井摻雜物。在一實施例中,HV井區域210是以HV井摻雜物輕摻雜。舉例來說,該HV井摻雜物的極性類型與該隔離井摻雜物的極性類型相反。在一實施例 中,對於第一極性類型的隔離井摻雜物而言,該HV井摻雜物為第二極性類型。舉例來說,提供p型HV井區域給n型隔離井。也可使用HV井區域以及隔離井的其他配置。在一實施例中,該HV井區域以及控制井是以相反極性類型的摻雜物摻雜。舉例來說,提供p型HV井區域給n型隔離及控制井208和209。在裝置或程式操作期間,該HV井區域用以改善該控制井的隔離。HV井區域的提供致使能選擇性程式並且能減低單元尺寸佈局。該HV井區域具有從該基板的表面算起的深度DP。該HV井區域可稱作為第二隔離井。 In some embodiments, the HV well region 210 can be provided within the isolation well 208 in the substrate. In an embodiment, the HV well region surrounds the first and second wells. For example, the HV well region separates the first and second wells 209 and 207 from the isolation well 208. In one embodiment, the HV well region is a common HV well region of the memory array. For example, the HV well region surrounds a plurality of memory cells of the memory array. The HV well region includes HV well dopants. In an embodiment, the HV well region 210 is lightly doped with HV well dopants. For example, the polarity type of the HV well dopant is opposite to the polarity type of the isolation well dopant. In an embodiment, the HV well dopant is of a second polarity type for the isolation well dopant of the first polarity type. For example, a p-type HV well region is provided for an n-type isolation well. The HV well area as well as other configurations of the isolation well can also be used. In an embodiment, the HV well region and the control well are doped with dopants of opposite polarity types. For example, a p-type HV well region is provided for the n-type isolation and control wells 208 and 209. The HV well area is used to improve isolation of the control well during operation of the apparatus or program. The provision of the HV well region enables selective programming and reduces cell size layout. The HV well region has a depth D P from the surface of the substrate. The HV well area can be referred to as a second isolation well.

在一實施例中,DP比DN淺且比DW深。一般而言,DW少於DP,DP少於DN(DW<DP<DN)。舉例來說,DN可為大約1.8μm而DP可為大約0.8-1.2μm。也可使用對於DW、DN以及DP而言的其他合適深度尺寸。 In an embodiment, D P is shallower than D N and deeper than D W . In general, D W is less than D P and D P is less than D N (D W <D P <D N ). For example, D N can be about 1.8 μm and D P can be about 0.8-1.2 μm. Other suitable depth dimensions for D W , D N , and D P can also be used.

單元隔離區域280,如圖所示,係分離該第一及第二井以及其他裝置區域。在一實施例中,單元隔離區域280充分重疊於第一及第二井209及207以隔離該不同的井。舉例來說,該單元隔離區域重疊於該第一及第二井的一部分。在一實施例中,該第一及第二井的底部延伸至該單元隔離區域之下。舉例來說,該第一及第二井延伸至且突出於該單元隔離區域之下。也可使用第一及第二井的其他配置。也可在該第一和第二井之間設置提他類型的隔離區域。該單元隔離區域界定在該第一及第二井中的主動區域。舉例來說,該單元隔離區域界定在第二井207中 的主動電晶體區域222,以及在第一井209中的主動電容區域220。舉例來說,該單元隔離區域為淺槽隔離(STI)區域。也可使用隔離區域的其他類型。 The unit isolation region 280, as shown, separates the first and second wells from other device regions. In an embodiment, the cell isolation region 280 is sufficiently overlapped with the first and second wells 209 and 207 to isolate the different wells. For example, the unit isolation region overlaps a portion of the first and second wells. In an embodiment, the bottoms of the first and second wells extend below the unit isolation region. For example, the first and second wells extend to and protrude below the unit isolation region. Other configurations of the first and second wells can also be used. A lifting type of isolation type may also be provided between the first and second wells. The unit isolation region defines an active region in the first and second wells. For example, the unit isolation region is defined in the second well 207 Active transistor region 222, and active capacitive region 220 in first well 209. For example, the cell isolation region is a shallow trench isolation (STI) region. Other types of isolated areas can also be used.

單元隔離區域具有深度DI。舉例來說,該單元隔離區域具有從該基板表面算起的深度DI。在一實施例中,該單元隔離區域具有比該第一及第二井較淺的深度。舉例來說,DI比該第一及第二井以及該HV井區域的深度較少(DI<DW<DP)。舉例來說,DI可為大約0.5μm。也可使用對於DI之其他合適的深度尺寸。 The cell isolation region has a depth D I . For example, the cell isolation region has a depth D I from the surface of the substrate. In an embodiment, the unit isolation region has a shallower depth than the first and second wells. For example, D I is less deep than the first and second wells and the HV well region (D I <D W <D P ). For example, D I can be about 0.5 μm . Other suitable depth dimensions for D I can also be used.

在其他實施例中,原生層(native layer)290突出於分離該第一及第二井209及207的該單元隔離區域之下,如第2c圖所示。原生層290係設置介於該第一及第二井的底部之間。舉例來說,該原生層係分離該第一及第二井。在一實施例中,製造製程設計為包括維持基板205的低摻雜濃度的基板區域以形成原生層290。舉例來說,該原生層為本質上摻雜層並且作為阻擋層以維持該基板的原始輕摻雜部分,其可能在邏輯(或主)製程階段變為重摻雜區域。也可使用原生層的其他類型。該原生層係從該單元隔離區域的底部延伸至大約DW的深度。舉例來說,該第一及第二井並不於該單元隔離區域之下突出。該臨界電壓(Vt)典型上很低,舉例來說,大約0.2V並且該原生層為具有非常類似或接近該初始基板的特性的輕摻雜層。因此,該原生層的存在改善了在該第一及第二井之間的隔離並且增加崩潰電壓。 In other embodiments, a native layer 290 protrudes below the cell isolation region separating the first and second wells 209 and 207, as shown in Figure 2c. A native layer 290 is disposed between the bottoms of the first and second wells. For example, the native layer separates the first and second wells. In an embodiment, the fabrication process is designed to include maintaining a low doping concentration of the substrate region of the substrate 205 to form the native layer 290. For example, the native layer is an essentially doped layer and acts as a barrier to maintain the original lightly doped portion of the substrate, which may become heavily doped regions during the logic (or main) process. Other types of native layers can also be used. The native layer extends from the bottom of the cell isolation region to a depth of approximately DW . For example, the first and second wells do not protrude below the cell isolation region. The threshold voltage (Vt) is typically very low, for example, about 0.2 V and the native layer is a lightly doped layer having properties very similar or close to the initial substrate. Thus, the presence of the native layer improves isolation between the first and second wells and increases the breakdown voltage.

存取以及儲存電晶體係設置在該第二或電晶體井中的該主動電晶體區域上。電晶體包括設置在介於第一及第二擴散區域之間的閘極。舉例來說,該擴散區域包括與該電晶體類型摻雜物相同極性類型的摻雜物。舉例來說,p型電晶體具有有p型摻雜物的擴散區域。舉例來說,該擴散區域為重摻雜區域。該閘極係設置在該基板上而該擴散區域係設置在該基板的主動區域中。閘極包括閘電極258以及閘極介電質257。舉例來說,閘電極258可為多晶矽閘電極以及閘極介電質257可為氧化矽閘極介電質。也可使用閘電極以及介電質材料的其他類型。 An access and storage cell system is disposed on the active transistor region in the second or transistor well. The transistor includes a gate disposed between the first and second diffusion regions. For example, the diffusion region includes a dopant of the same polarity type as the transistor type dopant. For example, a p-type transistor has a diffusion region with a p-type dopant. For example, the diffusion region is a heavily doped region. The gate is disposed on the substrate and the diffusion region is disposed in an active region of the substrate. The gate includes a gate electrode 258 and a gate dielectric 257. For example, gate electrode 258 can be a polysilicon gate electrode and gate dielectric 257 can be a yttria gate dielectric. Gate electrodes as well as other types of dielectric materials can also be used.

介電質間隔件(未圖示)可提供在該電晶體的閘極側壁上。該間隔件可用以促進形成電晶體擴散區域。舉例來說,在擴散延伸區域形成之後形成間隔件。舉例來說,可藉由在該基板上形成間隔件層並且將其各向異性蝕刻以移除水平部分,留下在該閘極的側壁上的間隔件之方式形成間隔件。在形成該間隔件之後,執行植入以形成該電晶體擴散區域。 A dielectric spacer (not shown) may be provided on the gate sidewall of the transistor. The spacer can be used to facilitate the formation of a transistor diffusion region. For example, a spacer is formed after the diffusion extension region is formed. For example, a spacer can be formed by forming a spacer layer on the substrate and anisotropically etching it to remove the horizontal portion, leaving a spacer on the sidewall of the gate. After the spacer is formed, implantation is performed to form the transistor diffusion region.

如所討論的,存取電晶體110包括在主動電晶體區域222中以電晶體類型摻雜物重摻雜的第一及第二存取擴散區域212及214以及在該基板上的存取閘極216。在一實施例中,電晶體擴散區域可包括延伸超過該擴散區域下以於該電晶體閘極的一部分之下突出的擴散延伸區域(未圖示)。該存取閘極包括覆蓋在存取閘極介電質257之上的存取閘電極258。該存取閘極可稱作為選擇閘極。儲 存電晶體130包括在該基板中之電晶體類型摻雜物重摻雜的第一及第二儲存擴散區域232及234以及在該基板上的儲存閘極236。該儲存閘極包括覆蓋在儲存閘極介電質257上的儲存閘電極258。該儲存閘極可稱作為浮動閘極。存取以及儲存電晶體110及130是串聯耦合。在一實施例中,第二存取擴散區域214以及第二儲存擴散區域234形成該電晶體的共同擴散區域。對於該存取及儲存閘極的串聯連接的其他配置也可能是有用的。 As discussed, access transistor 110 includes first and second access diffusion regions 212 and 214 heavily doped with transistor type dopants in active transistor region 222 and access gates on the substrate Pole 216. In an embodiment, the transistor diffusion region can include a diffusion extension region (not shown) that extends beyond the diffusion region to protrude below a portion of the transistor gate. The access gate includes an access gate electrode 258 overlying the access gate dielectric 257. The access gate can be referred to as a selection gate. Storage The storage transistor 130 includes first and second storage diffusion regions 232 and 234 heavily doped with a transistor type dopant in the substrate and a storage gate 236 on the substrate. The storage gate includes a storage gate electrode 258 overlying the storage gate dielectric 257. The storage gate can be referred to as a floating gate. Access and storage transistors 110 and 130 are coupled in series. In an embodiment, the second access diffusion region 214 and the second storage diffusion region 234 form a common diffusion region of the transistor. Other configurations for the series connection of the access and storage gates may also be useful.

控制電容150設置在該第一井上。該控制電容包括設置在該基板上在該主動電容區域之上的控制閘極256。該控制閘極包括在控制閘極介電質257之上的控制閘電極258。舉例來說,控制閘電極258可為多晶矽控制閘電極,並且控制閘極介電質257可為氧化矽控制閘極介電質。也可使用閘電極或介電質材料的其他類型。在一實施例中,該控制閘電極以控制或電容類型摻雜物摻雜。舉例來說,該控制閘電極是以與該控制井相同的極性類型摻雜物的重摻雜。電容接觸栓252係設置在該控制井之上並且鄰近於該控制閘極的側邊。舉例來說,該電容接觸栓係從該控制閘極的側邊移開。在一實施例中,該電容接觸栓耦合至介於該單位隔離區域以及該控制閘極的側邊之間的主動電容區域(或井拾取區域)。舉例來說,該電容接觸栓可為導電接觸栓,例如鎢接觸栓。也可使用導電接觸栓的其他類型。電容接觸栓252作為該電容的井拾取區域之井分接頭。儘管顯示為一個電容接觸栓,應理解到這可能有多 於一個之電容接觸栓耦合至該主動電容區域或該控制井的露出頂端表面。控制井209係作為該第二或井電容極板,而該閘電極258係作為該第一或閘電容極板。在一實施例中,該電容閘電極係在形成該電容接觸栓之前摻雜。舉例來說,設置在該基板上的閘電極層是預摻雜有控制摻雜物並且經圖案化以成形該電容閘電極。 A control capacitor 150 is disposed on the first well. The control capacitor includes a control gate 256 disposed on the substrate over the active capacitive region. The control gate includes a control gate electrode 258 over the control gate dielectric 257. For example, control gate electrode 258 can be a polysilicon control gate electrode, and control gate dielectric 257 can be a yttria control gate dielectric. Other types of gate electrodes or dielectric materials can also be used. In an embodiment, the control gate electrode is doped with a control or capacitance type dopant. For example, the control gate electrode is heavily doped with the same polarity type dopant as the control well. A capacitive contact plug 252 is disposed above the control well and adjacent to a side of the control gate. For example, the capacitive contact tether is removed from the side of the control gate. In an embodiment, the capacitive contact plug is coupled to an active capacitive region (or well pick-up region) between the unit isolation region and a side of the control gate. For example, the capacitive contact plug can be a conductive contact plug, such as a tungsten contact plug. Other types of conductive contact plugs can also be used. Capacitive contact plug 252 acts as a well tap for the well pick-up area of the capacitor. Although shown as a capacitive contact plug, it should be understood that this may be more A capacitive contact plug is coupled to the active capacitive region or the exposed top surface of the control well. Control well 209 acts as the second or well capacitance plate and the gate electrode 258 acts as the first or gate capacitance plate. In an embodiment, the capacitive gate electrode is doped prior to forming the capacitive contact plug. For example, a gate electrode layer disposed on the substrate is pre-doped with a control dopant and patterned to form the capacitive gate electrode.

在一實施例中,該控制閘極以及儲存閘電極258為共耦合。在一實施例中,控制閘極256以及儲存閘極236以相同的閘極層形成。舉例來說,圖案化該閘極層係產生該控制以及儲存閘極。在這樣的例子中,控制閘極256以及儲存閘極236係以相同的材料形成。舉例來說,該控制閘電極以及介電質層係以與該儲存閘電極以及介電質層相同的材料形成。舉例來說,該閘電極係以電容類型摻雜物摻雜。也可以提供閘電極其他摻雜物類型。在一實施例中,該存取、儲存以及控制閘極係由相同的閘極層形成。也可使用該閘極的其他配置。舉例來說,該閘極可由不同的閘極層形成。 In an embodiment, the control gate and the storage gate electrode 258 are co-coupled. In one embodiment, control gate 256 and storage gate 236 are formed with the same gate layer. For example, patterning the gate layer produces the control and storage gate. In such an example, control gate 256 and storage gate 236 are formed of the same material. For example, the control gate electrode and the dielectric layer are formed of the same material as the storage gate electrode and the dielectric layer. For example, the gate electrode is doped with a capacitance type dopant. Other dopant types for the gate electrode can also be provided. In one embodiment, the access, storage, and control gates are formed from the same gate layer. Other configurations of the gate can also be used. For example, the gate can be formed by different gate layers.

金屬矽化物接觸(未圖示)可提供在該記憶體單元的接觸區域上。舉例來說,該金屬矽化物接觸可為鎳或鎳基金屬矽化物接觸。也可使用金屬矽化物接觸的其他適合類型,包括鈷或鈷基金屬矽化物接觸。在一實施例中,金屬矽化物接觸可提供在該電晶體擴散區域、主動電容區域以及該存取閘極上。矽化物阻塊261係設置在該儲存及控制閘極之上。舉例來說,該矽化阻塊為介電質材料, 例如氧化矽或氮化矽。也可使用矽化物阻塊的其他類型。提供矽化物阻塊在該儲存及控制閘極之上可防止矽化物接觸形成在該閘極之上。這改善了數據保持。 A metal halide contact (not shown) can be provided on the contact area of the memory cell. For example, the metal telluride contact can be a nickel or nickel based metal halide contact. Other suitable types of metal halide contact may also be used, including cobalt or cobalt based metal halide contacts. In an embodiment, a metal halide contact can be provided over the transistor diffusion region, the active capacitor region, and the access gate. A germanide block 261 is disposed over the storage and control gates. For example, the germanium block is a dielectric material. For example, yttrium oxide or tantalum nitride. Other types of bismuth block can also be used. Providing a germanide block on the storage and control gate prevents the germanide contact from forming over the gate. This improves data retention.

第一存取擴散區域212耦合至該記憶體裝置的SL。第一儲存擴散區域232耦合至該記憶體裝置的BL。存取閘極216耦合至該記憶體裝置的SGL。電容接觸栓252耦合至該記憶體裝置的CGL。在一些實施例中,控制閘極256實施為控制電容150。在一些實施例中,該SGL係沿著第一方向(例如字元線(WL)方向)設置,而該位元線係沿著第二方向(例如垂直於該WL方向的位元線(BL)方向)設置。該CGL可沿著該字元線方向設置,以及該SL可沿著該位元線方向設置。也可使用BL、CGL、SGL以及SL的其他配置。舉例來說,陣列的記憶體單元可耦合至沿著字元線方向設置的共同SL(CSL)。 The first access diffusion region 212 is coupled to the SL of the memory device. The first storage diffusion region 232 is coupled to the BL of the memory device. Access gate 216 is coupled to the SGL of the memory device. Capacitive contact plug 252 is coupled to the CGL of the memory device. In some embodiments, control gate 256 is implemented as control capacitor 150. In some embodiments, the SGL is disposed along a first direction (eg, a word line (WL) direction) and the bit line is along a second direction (eg, a bit line that is perpendicular to the WL direction (BL) )))) setting. The CGL can be disposed along the direction of the word line, and the SL can be disposed along the direction of the bit line. Other configurations of BL, CGL, SGL, and SL can also be used. For example, the memory cells of the array can be coupled to a common SL (CSL) disposed along the direction of the word line.

該記憶體單元的各種導線可設置於該裝置的金屬階層中。設置於相同方向的導線可提供在相同的金屬階層中。舉例來說,沿著該BL方向設置的導線可設置在MX,而沿著該WL方向設置的導線可設在該裝置的MX+1。也可使用導線以及金屬階層的其他配置。 The various wires of the memory unit can be placed in the metal hierarchy of the device. Wires placed in the same direction can be provided in the same metal level. For example, a wire disposed along the BL direction may be disposed at M X , and a wire disposed along the WL direction may be disposed at M X+1 of the device. Wires and other configurations of the metal hierarchy can also be used.

所描述的記憶體單元因為增加了電容耦合比而具有改善的或更有效率的程式。舉例來說,該控制閘極(CG)以及浮動閘極(FG)的佈局可設計為具有一面積比以產生該所需的電容耦合比。在一些實施例中,CG:FG的面積比可為大約0.8:0.2。舉例來說,該浮動閘極的寬(W) ×長(L)可為大約0.4×0.28,而該控制閘極的W×L可為大約1.6×0.84。也可以提供其他CG:FG的面積比。藉由提供大面積給該控制閘極,可產生中等偏壓在該電容井上。為了該記憶體單元的高效率程式,此偏壓被傳輸至該浮動閘極。降低該電容井所需的高電壓也允許形成較小的電荷泵。這進一步縮減了該裝置的尺寸。 The described memory cells have improved or more efficient programs because of the increased capacitance coupling ratio. For example, the layout of the control gate (CG) and floating gate (FG) can be designed to have an area ratio to produce the desired capacitive coupling ratio. In some embodiments, the area ratio of CG:FG can be about 0.8:0.2. For example, the width of the floating gate (W) The length (L) may be about 0.4 x 0.28, and the W x L of the control gate may be about 1.6 x 0.84. Other CG:FG area ratios can also be provided. By providing a large area to the control gate, a medium bias can be generated on the capacitor well. For the high efficiency program of the memory cell, this bias voltage is transmitted to the floating gate. Reducing the high voltage required for this capacitive well also allows for the formation of smaller charge pumps. This further reduces the size of the device.

在一些實施例中,藉由提供耦合至該電容的井電容極板的多個接觸(例如電容接觸栓)可達成降低電阻的壓降的效果並且從而改善製程穩固性。舉例來說,一個或更多個接觸栓可設置於鄰近該控制閘極以電性耦合該井電容極板至CGL。該接觸栓的數目可取決於該控制閘極的周長、該主動電容區域的尺寸以及該接觸的尺寸及間距。越大數目的接觸將降低更多的電阻。 In some embodiments, the effect of reducing the voltage drop of the resistance and thereby improving process robustness can be achieved by providing a plurality of contacts (eg, capacitive contact plugs) coupled to the well capacitor plates of the capacitor. For example, one or more contact pins can be disposed adjacent to the control gate to electrically couple the well capacitance plate to the CGL. The number of contact plugs may depend on the perimeter of the control gate, the size of the active capacitive region, and the size and spacing of the contacts. A larger number of contacts will reduce more resistance.

第3a及3b圖顯示記憶體單元的陣列300的實施例的示意圖。舉例來說,陣列的部分顯示為具有四個記憶體單元100,例如那些描述在第1圖及第2a至2c圖中者。常見的元件可能不被描述或詳細描述。記憶體單元的陣列可形成在具有設置於HV井區域210內的第一及第二井209及207的基板上。在一些實施例中,該HV井區域是由記憶體晶片的記憶體陣列共同的隔離井208所圍繞。在一實施例中,該第一及第二井延伸跨過陣列的互連記憶體單元的多個行。舉例來說,該第一及第二井係形成記憶體陣列的共同第一及第二井。也可使用第一及第二井的其他配置。 Figures 3a and 3b show schematic diagrams of an embodiment of an array 300 of memory cells. For example, portions of the array are shown as having four memory cells 100, such as those depicted in Figures 1 and 2a through 2c. Common components may not be described or described in detail. An array of memory cells can be formed on a substrate having first and second wells 209 and 207 disposed within HV well region 210. In some embodiments, the HV well region is surrounded by an isolation well 208 that is common to the memory array of the memory chip. In an embodiment, the first and second wells extend across a plurality of rows of interconnected memory cells of the array. For example, the first and second wells form a common first and second well of the memory array. Other configurations of the first and second wells can also be used.

如第3a圖所示,該記憶體單元係互連以形成由BL(BL0及BL1)及SL(SL0及SL1)所連接的兩行,以及由SGL(SGL0及SGL1)及CGL(CGL0及CGL1)所連接的記憶體單元的兩列。在一實施例中,記憶體單元的每一行的SL(SL0及SL1)係耦合至分離的源終端。舉例來說,SL0及SL1係耦合至第一及第二源終端並且BL0及BL1係耦合至第一及第二終端。耦合記憶體單元的分離行至分離的(或專用的)源終端係形成一AND類型陣列配置。舉例來說,圖示的AND類型陣列配置具有分別耦合至分離的SL及BL終端的每一行的存取及儲存電晶體。具有AND類型陣列配置於陣列內提供了更可靠的記憶體單元操作。 As shown in Figure 3a, the memory cells are interconnected to form two rows connected by BL (BL0 and BL1) and SL (SL0 and SL1), and by SGL (SGL0 and SGL1) and CGL (CGL0 and CGL1). ) Two columns of connected memory cells. In an embodiment, the SLs (SL0 and SL1) of each row of memory cells are coupled to separate source terminals. For example, SL0 and SL1 are coupled to the first and second source terminals and BL0 and BL1 are coupled to the first and second terminals. The separate rows of coupled memory cells to separate (or dedicated) source terminations form an AND type array configuration. For example, the illustrated AND type array configuration has access and storage transistors coupled to each of the separate SL and BL terminals, respectively. Having an AND type array configuration within the array provides more reliable memory unit operation.

在其他的實施例中,記憶體單元的每一行的SL耦合至共同的源終端。如第3b圖所示,記憶體單元的每一行的SL可耦合至設置於WL方向的共同源終端(CSL)。耦合儲存單元的分離行至共同源終端係形成NOR類型陣列配置。所圖示的NOR類型陣列配置具有於分離行中耦合至CSL的存取電晶體,而於分離行中的儲存電晶體係耦合至分離BL(或汲極)終端。具有NOR類型陣列配置提供了隨機存取至該記憶體單元並且減少陣列的佔用空間。也可使用陣列的其他配置。 In other embodiments, the SL of each row of memory cells is coupled to a common source terminal. As shown in FIG. 3b, the SL of each row of the memory cells can be coupled to a common source terminal (CSL) disposed in the WL direction. The separation of the coupled storage cells to the common source termination forms a NOR type array configuration. The illustrated NOR type array configuration has an access transistor coupled to the CSL in a separate row, while the storage cell system in the separate row is coupled to a separate BL (or drain) terminal. Having a NOR type array configuration provides random access to the memory unit and reduces the footprint of the array. Other configurations of the array can also be used.

儘管所顯示的為陣列的2×2部分,應理解到該陣列可包括眾多的列及行。舉例來說,該記憶體陣列可形成記憶體塊。 Although shown as a 2x2 portion of the array, it should be understood that the array can include numerous columns and rows. For example, the memory array can form a memory block.

於一實施例中,第1圖及第2a至2c圖的記 憶體單元是用以包括第一類型電晶體以及第一類型電容。舉例來說,該存取及儲存電晶體為與該控制電容相同的極性類型。於一實施例中,該第一類型為n型。舉例來說,該記憶體單元係配置為具有n型電晶體以及n型電容。在這樣的例子中,該電晶體(或第二)井207以及電容(或第一)井209包括相反極性類型的摻雜物。該電晶體井包括第二極性類型或p型摻雜物,而該控制井包括第一極性類型或n型摻雜物。該電晶體擴散區域為n型。更進一步來說,該閘電極以電容類型摻雜物摻雜。舉例來說,該閘電極係以第一極性類型或n型摻雜物摻雜。也可使用其他的閘極配置。 In one embodiment, the figures of Figure 1 and Figures 2a to 2c The memory cell unit is for including a first type of transistor and a first type of capacitor. For example, the access and storage transistor is of the same polarity type as the control capacitor. In an embodiment, the first type is an n-type. For example, the memory cell is configured to have an n-type transistor and an n-type capacitor. In such an example, the transistor (or second) well 207 and the capacitor (or first) well 209 comprise dopants of the opposite polarity type. The transistor well includes a second polarity type or p-type dopant, and the control well includes a first polarity type or an n-type dopant. The transistor diffusion region is n-type. Further, the gate electrode is doped with a capacitance type dopant. For example, the gate electrode is doped with a first polarity type or an n-type dopant. Other gate configurations are also available.

對於具有第一類型電晶體及電容的記憶體單元,各種操作模式係被描述在第4a至4c圖中。舉例來說,該第一類型為n型。以下表1顯示用於程式、抹除以及讀取操作模式之於記憶體單元的各種終端的各種偏壓: For memory cells having a first type of transistor and capacitor, various modes of operation are described in Figures 4a through 4c. For example, the first type is an n-type. Table 1 below shows the various bias voltages used for program, erase, and read modes of operation for various terminals of the memory unit:

在表1中的數值使用Fowler-Nordheim(FN)隧穿於程式 及抹除運算。舉例來說,該數值係針對操作電壓Vdd等於大約5V者。也可使用其他合適的電壓數值。 The values in Table 1 are tunneled to the program and erase operations using Fowler-Nordheim (FN). For example, the value is for an operating voltage Vdd equal to about 5V. Other suitable voltage values can also be used.

該記憶體單元可操作在Fowler-Nordhein(FN)隧穿程式模式400a,如第4a圖所示。為了實現FN隧穿程式操作,提供用於這樣的程式操作的各種選擇(sel)訊號於所選擇的記憶體單元的各種終端。在該程式模式中,電子載體465從該電晶體井隧穿通過至該浮動閘極(FG)。也可使用程式模式的其他合適類型,例如通道熱電子(CHE)注入程式模式。舉例來說,在該CHE程式模式中,電子載體被從該電晶體通道注入至在該汲極側上的該FG。 The memory unit is operable in a Fowler-Nordhein (FN) tunneling program mode 400a as shown in Figure 4a. In order to implement the FN tunneling program operation, various selection (sel) signals for such program operations are provided for the various terminals of the selected memory unit. In this programming mode, an electronic carrier 465 is tunneled from the transistor well to the floating gate (FG). Other suitable types of program mode can also be used, such as channel hot electron (CHE) injection mode. For example, in the CHE program mode, an electronic carrier is injected from the transistor channel to the FG on the drain side.

該記憶體單元可操作在FN隧穿抹除模式400b,如第4b圖所示。為了實現FN隧穿抹除模式,提供用於這樣的抹除操作的各種sel訊號於所選擇的記憶體單元的各種終端。在該抹除模式中,電子載體465從該FG移動至該電晶體井,從該閘極的該汲極側。該抹除模式可實現記憶體塊或行的抹除操作。 The memory unit is operable in the FN tunneling erase mode 400b as shown in Figure 4b. In order to implement the FN tunneling erase mode, various sel signals for such erase operations are provided for various terminals of the selected memory unit. In the erase mode, the electronic carrier 465 is moved from the FG to the transistor well from the drain side of the gate. This erase mode enables erase operations of memory blocks or lines.

關於讀取操作400c,其圖示在第4c圖。提供用於讀取操作的各種選擇(sel)訊號於所選擇的記憶體單元的各種終端,以影響該讀取操作。 Regarding the read operation 400c, it is illustrated in Figure 4c. Various selections (sel) signals for read operations are provided at various terminals of the selected memory unit to affect the read operation.

第5圖顯示記憶體裝置的記憶體單元的陣列500的實施例的平面圖。該記憶體單元類似於在第1圖及第2a至2c圖中所描述者。常見的元件可能不被描述或詳細描述。所示記憶體單元200為非揮發性記憶體單元。舉例來說,該記憶體單元為非揮發性MTP記憶體單元。如 圖所示,該記憶體單元包括存取以及儲存電晶體110及130以串聯耦合,而控制閘極256係共同耦合至儲存閘極236以產生浮動閘極。該電晶體係設置在主動電晶體區域上並且該控制閘極係設置在主動電容區域上。記憶體單元的陣列可形成在具有隔離井、HV井區域以及第一及第二井的基板上。 Figure 5 shows a plan view of an embodiment of an array 500 of memory cells of a memory device. This memory unit is similar to that described in Figures 1 and 2a through 2c. Common components may not be described or described in detail. The memory unit 200 is shown as a non-volatile memory unit. For example, the memory unit is a non-volatile MTP memory unit. Such as As shown, the memory cell includes access and storage transistors 110 and 130 coupled in series, and control gate 256 is commonly coupled to storage gate 236 to generate a floating gate. The electro-optic system is disposed on the active transistor region and the control gate is disposed on the active capacitor region. An array of memory cells can be formed on the substrate having the isolation well, the HV well region, and the first and second wells.

在一實施例中,陣列500包括多個在彼此相反的方向配置的記憶體單元。舉例來說,該記憶體單元在第一及第二側邊上為彼此的鏡像並且該記憶體單元在頂側及底側上為彼此的鏡像。在其他的實施例中,該記憶體單元可沿著Y或是字元線方向如是安置(例如不具有鏡像)。在一實施例中,原生層290設置在該基板中介於該主動電晶體及電容區域之間。舉例來說,該原生層增加了崩潰電壓並且改善了介於該電晶體以及控制井之間的絕緣。 In an embodiment, array 500 includes a plurality of memory cells arranged in opposite directions from one another. For example, the memory cells are mirror images of one another on the first and second sides and the memory cells are mirror images of each other on the top and bottom sides. In other embodiments, the memory unit can be placed along the Y or word line direction (eg, without mirroring). In one embodiment, the native layer 290 is disposed between the active transistor and the capacitive region in the substrate. For example, the native layer increases the breakdown voltage and improves the insulation between the transistor and the control well.

多個記憶體單元可藉由各種線互連以形成陣列。舉例來說,記憶體單元可藉由SGL及CGL而互連以形成記憶體單元的列及藉由BL及SL而互連以形成記憶體單元的行。藉由施加合適的訊號至記憶體單元的各種線或終端,可達成存取該記憶體單元。藉由FN隧穿以從該電晶體井隧穿電子進入該浮動閘極,係達成該記憶體單元的位元程式。藉由從該FG隧穿FN電子至該電晶體井,從該閘極的該汲極側,可達成塊或是行抹除。 A plurality of memory cells can be interconnected by various lines to form an array. For example, memory cells can be interconnected by SGL and CGL to form columns of memory cells and interconnects by BL and SL to form rows of memory cells. Access to the memory unit can be achieved by applying appropriate signals to various lines or terminals of the memory unit. A bit sequence of the memory cell is achieved by FN tunneling to tunnel electrons from the transistor well into the floating gate. By tunneling FN electrons from the FG to the transistor well, block or row erase can be achieved from the drain side of the gate.

第6圖顯示用於形成本文所述的記憶體單元的實施例的製程600。詳而言之,製程600說明範例的 半導體製造程序流程以形成描述在第1圖以及第2a至2c圖中的記憶體單元。常見的元件可能不被描述或詳細描述。 Figure 6 shows a process 600 for forming an embodiment of the memory cell described herein. In detail, process 600 illustrates an example The semiconductor fabrication process flows to form the memory cells described in Figures 1 and 2a through 2c. Common components may not be described or described in detail.

在步驟602,形成該裝置的製程包括提供備有一個或更多個單元或裝置區域的基板。舉例來說,該基板為以第二極性類型摻雜物(例如p型摻雜物)輕摻雜。也可以提供以其他類型的摻雜物摻雜的基板或未摻雜的基板。藉由裝置隔離區域(例如淺槽隔離(STI)區域),可將一裝置區域與其他裝置區域隔離。在一實施例中,該裝置隔離區域係界定主動區域,例如該主動電晶體以及電容區域。舉例來說,裝置隔離區域隔離該電晶體以及電容區域和其他裝置區域,例如HV、MV及/或LV裝置。在一實施例中,形成該裝置隔離區域包括在該基板中形成凹槽以及形成填充該凹槽的絕緣層。 At step 602, the process of forming the device includes providing a substrate provided with one or more cells or device regions. For example, the substrate is lightly doped with a second polarity type dopant (eg, a p-type dopant). Substrates doped with other types of dopants or undoped substrates may also be provided. A device area can be isolated from other device areas by device isolation regions, such as shallow trench isolation (STI) regions. In an embodiment, the device isolation region defines an active region, such as the active transistor and the capacitive region. For example, the device isolation region isolates the transistor as well as the capacitive region and other device regions, such as HV, MV, and/or LV devices. In an embodiment, forming the device isolation region includes forming a recess in the substrate and forming an insulating layer filling the recess.

在一實施例中,在形成隔離井於該基板中之前,該製程流程可沿著箭頭A繼續以形成原生層。在替換的實施例中,該製程流程可沿著箭頭B繼續以形成該隔離井於該基板中而不形成原生層。 In an embodiment, the process flow may continue along arrow A to form a native layer prior to forming the isolation well in the substrate. In an alternate embodiment, the process flow can continue along arrow B to form the isolation well in the substrate without forming a native layer.

在步驟604,原生層係形成在介於該電晶體以及電容區域之間。該原生層可設置在該基板中、於該裝置隔離區域之下,如第2c圖所示。該原生層為在該製造程序期間引入的本質摻雜層。在一實施例中,該製造程序係設計成形成作為阻擋層的原生層以維持該基板的原始輕摻雜部分,其可能在邏輯(或主)製程階段形成變為重摻雜區域。舉例來說,該製造程序係設計成包括維持基板205的 該低摻雜濃度的基板區域以形成該原生層290。也可使用其他用以形成該原生層的合適技術。該原生層包括深於該裝置隔離區域的深度。舉例來說,裝置隔離區域設置在該原生層之上。於一實施例中,該原生層為於分離該第一及第二井的裝置隔離區域之下突出的輕摻雜層。舉例來說,該原生層可為大約0.39μm寬。原生層的其他合適尺寸也可能是有用的。該原生層係分離延伸在該裝置隔離區域之下的井的底部。該原生層的深度可為大約該第一及/或第二井的深度。在原生層存在的例子中,該原生層增加了崩潰電壓以及改善了該第一及第二井之間的絕緣。 At step 604, a native layer is formed between the transistor and the capacitive region. The native layer can be disposed in the substrate below the isolation region of the device, as shown in Figure 2c. The native layer is an intrinsic doped layer introduced during the manufacturing process. In one embodiment, the fabrication process is designed to form a native layer as a barrier layer to maintain the original lightly doped portion of the substrate, which may form a heavily doped region during the logic (or main) process. For example, the fabrication process is designed to include maintaining the low doping concentration of the substrate region of the substrate 205 to form the native layer 290. Other suitable techniques for forming the native layer can also be used. The native layer includes a depth deeper than the isolated region of the device. For example, the device isolation region is disposed above the native layer. In one embodiment, the native layer is a lightly doped layer that protrudes below the device isolation region separating the first and second wells. For example, the native layer can be about 0.39 μιη wide. Other suitable sizes of the primary layer may also be useful. The native layer separates the bottom of the well that extends below the isolation zone of the device. The depth of the native layer can be about the depth of the first and/or second well. In the case where the native layer is present, the native layer increases the breakdown voltage and improves the insulation between the first and second wells.

在步驟606,隔離井形成在該基板中。在一實施例中,該隔離井為環繞記憶體晶片的記憶體陣列的共同隔離井。舉例來說,該隔離井為植入至該裝置隔離區域之下一深度的深隔離井。也可使用形成該隔離井的其他方法。在一實施例中,對於第二極性類型基板而言,係形成第一極性類型隔離井以。舉例來說,對於p型基板而言,該隔離井係以n型摻雜物輕摻雜。也可使用其他的摻雜物濃度以及摻雜物類型。 At step 606, an isolation well is formed in the substrate. In one embodiment, the isolation well is a common isolation well surrounding the memory array of the memory chip. For example, the isolation well is a deep isolation well implanted to a depth below the isolation region of the device. Other methods of forming the isolation well can also be used. In one embodiment, for a second polarity type substrate, a first polarity type isolation well is formed. For example, for a p-type substrate, the isolation well is lightly doped with an n-type dopant. Other dopant concentrations as well as dopant types can also be used.

在步驟608,HV井區域係形成在該隔離井內、於該基板中。舉例來說,該隔離井係環繞該HV井區域。在一實施例中,該HV井區域為環繞互連的記憶體單元的陣列的共同HV井區域。舉例來說,該HV井區域為植入至較淺於該隔離井但較深於該裝置隔離區域的深度。也可使用形成該HV井的其他技術。在一實施例中,對於 第一極性類型的隔離井而言,係形成第二極性類型的HV井區域。舉例來說,對於n型隔離井而言,該HV井區域係以p型摻雜物輕摻雜。也可使用其他摻雜物濃度。也可使用HV井區域以及隔離井的其他配置。 At step 608, an HV well region is formed in the isolation well in the substrate. For example, the isolation well is surrounding the HV well region. In an embodiment, the HV well region is a common HV well region surrounding an array of interconnected memory cells. For example, the HV well region is implanted to a depth that is shallower than the isolation well but deeper than the isolation region of the device. Other techniques for forming the HV well can also be used. In an embodiment, for In the case of an isolation well of the first polarity type, an HV well region of the second polarity type is formed. For example, for an n-type isolation well, the HV well region is lightly doped with a p-type dopant. Other dopant concentrations can also be used. The HV well area as well as other configurations of the isolation well can also be used.

在步驟610,第一及第二井係形成在該HV井區域內。舉例來說,該HV井區域環繞該第一及第二井。該第一井形成在該主動電容區域中以及該第二井形成在該主動電晶體區域中。在一實施例中,該第一及第二井為植入至較淺於該HV井但較深於該裝置隔離區域的深度。舉例來說,該第一及第二井具有大約相同的深度。也可以提供具有不同深度的第一及第二井。也可以使用形成該井的其他技術。該第一井為以控制或電容類型摻雜物輕摻雜,以及該第二井係以電晶體類型摻雜物中度摻雜。也可以使用其他摻雜物濃度。 At step 610, first and second well systems are formed within the HV well region. For example, the HV well region surrounds the first and second wells. The first well is formed in the active capacitor region and the second well is formed in the active transistor region. In one embodiment, the first and second wells are implanted to a depth that is shallower than the HV well but deeper than the isolation region of the device. For example, the first and second wells have approximately the same depth. It is also possible to provide first and second wells having different depths. Other techniques for forming the well can also be used. The first well is lightly doped with a control or capacitance type dopant, and the second well is doped with a transistor type dopant. Other dopant concentrations can also be used.

在步驟612,裝置閘極係形成在該基板上。閘極介電質層係設置在該基板上並且跨過該裝置區域以形成各種裝置的閘極介電質。舉例來說,氧化矽層係形成在該基板上以形成閘極介電質層。可對於不同的裝置區域以不同的厚度界定該閘極介電質。在一實施例中,閘電極層(例如多晶矽層)係設置在該閘極介電質層上並且圖案化以形成該各種裝置的閘電極。在一實施例中,該閘電極層為摻雜多晶矽層。舉例來說,控制閘極的閘電極係以控制或電容類型摻雜物預摻雜以形成該控制閘極。該閘電極以及閘極介電質係圖案化以形成裝置(例如HV、MV及/或LV 裝置)的閘極。該製程可繼續形成記憶體單元,例如MTP記憶體單元。在一實施例中,該記憶體單元由HV及/或MV裝置所製成。舉例來說,該存取及儲存電晶體為MV裝置以及該控制電容為HV裝置。 At step 612, a device gate is formed on the substrate. A gate dielectric layer is disposed on the substrate and across the device region to form a gate dielectric of various devices. For example, a hafnium oxide layer is formed on the substrate to form a gate dielectric layer. The gate dielectric can be defined in different thicknesses for different device regions. In an embodiment, a gate electrode layer (eg, a polysilicon layer) is disposed over the gate dielectric layer and patterned to form gate electrodes of the various devices. In an embodiment, the gate electrode layer is a doped polysilicon layer. For example, the gate electrode of the control gate is pre-doped with a control or capacitance type dopant to form the control gate. The gate electrode and the gate dielectric are patterned to form a device (eg, HV, MV, and/or LV) The gate of the device). The process can continue to form a memory unit, such as an MTP memory unit. In one embodiment, the memory unit is made of HV and/or MV devices. For example, the access and storage transistor is an MV device and the control capacitor is an HV device.

在步驟614,形成擴散延伸區域。在一實施例中,LDD以及環狀區域形成在鄰近於該電晶體閘極的側邊、延伸在該閘極之下。舉例來說,採用一共同植入遮罩以形成該LDD以及環狀區域。舉例來說,係使用該植入遮罩以於第一植入步驟形成環狀區域,並且執行第二步驟以形成LDD區域進入該環狀區域以形成該電晶體的環狀及LDD區域。也可能使用其他合適的技術以形成該環狀及LDD區域。也可以在不具有環狀區域下提供LDD區域。 At step 614, a diffusion extension region is formed. In an embodiment, the LDD and the annular region are formed adjacent to a side of the gate of the transistor and extending below the gate. For example, a common implant mask is employed to form the LDD and the annular region. For example, the implant mask is used to form an annular region in a first implantation step, and a second step is performed to form an LDD region into the annular region to form an annular and LDD region of the transistor. Other suitable techniques may also be used to form the ring and LDD regions. It is also possible to provide the LDD region without having an annular region.

在步驟616,形成閘極側壁間隔件。介電質間隔件層可設置在該基板上並且覆蓋該裝置區域。該介電質間隔件層可圖案化以形成閘極側壁間隔件。舉例來說,該側壁間隔件重疊於該LDD及環狀區域。在一實施例中,鄰近於該側壁間隔件的暴露之基板區域是以第一或第二極性類型摻雜物重摻雜以形成電晶體擴散區域。舉例來說,該電晶體擴散區域植入更深於該LDD以及環狀區域並且大約對準至該閘極側壁間隔件。 At step 616, a gate sidewall spacer is formed. A dielectric spacer layer can be disposed on the substrate and cover the device area. The dielectric spacer layer can be patterned to form a gate sidewall spacer. For example, the sidewall spacers overlap the LDD and the annular region. In an embodiment, the exposed substrate region adjacent to the sidewall spacer is heavily doped with a first or second polarity type dopant to form a transistor diffusion region. For example, the transistor diffusion region is implanted deeper into the LDD and the annular region and is approximately aligned to the gate sidewall spacer.

在步驟618,係形成導電接觸栓。在一實施例中,電容接觸栓形成在該控制井之上。舉例來說,可使用單一鑲嵌製程於設置於該基板上的預金屬化介電質(PMD)層(未圖示)中來形成該電容接觸栓。該電容接觸栓耦 合至該主動電容區域介於該裝置隔離區域以及該電容之間。舉例來說,該電容接觸栓設置於鄰近該控制閘極的側邊。電容接觸栓的其他配置也可能是有用的。在一實施例中,該電容接觸栓為導電接觸栓。舉例來說,該電容接觸栓可為鎢接觸栓。導電接觸栓的其他類型也可能是有用的。該電容接觸栓係作為對於該電容的井拾取區域之井分接頭。 At step 618, a conductive contact plug is formed. In an embodiment, a capacitive contact plug is formed over the control well. For example, the capacitive contact plug can be formed using a single damascene process in a pre-metallized dielectric (PMD) layer (not shown) disposed on the substrate. Capacitor contact pin coupling The active capacitive region is between the device isolation region and the capacitor. For example, the capacitive contact plug is disposed adjacent to a side of the control gate. Other configurations of capacitive contact plugs may also be useful. In an embodiment, the capacitive contact plug is a conductive contact plug. For example, the capacitive contact plug can be a tungsten contact plug. Other types of conductive contact plugs may also be useful. The capacitive contact tether acts as a well tap for the well pick-up area of the capacitor.

該製程繼續完成形成該裝置。該製程可包括形成層間介電質(ILD)層、至該記憶體單元的終端的金屬矽化物接觸、導電接觸以及一個或更多個互連階層、最終鈍化(final passivation)、切割、組裝以及封裝。也可能包括用以完成形成該裝置的其他製程。也可使用其他合適製程以形成如第2a至2c圖所示的裝置。 The process continues to complete the formation of the device. The process can include forming an interlayer dielectric (ILD) layer, metal telluride contacts to the termination of the memory cell, conductive contacts, and one or more interconnect levels, final passivation, dicing, assembly, and Package. Other processes to complete the formation of the device may also be included. Other suitable processes can also be used to form the apparatus as shown in Figures 2a through 2c.

在未背離本案的精神或必要特徵之下,本發明的發明概念可實施於其他特定的形式。因此,前文的實施例在各方面都被認為是說明性的,而非限制本文所描述的本發明。因此由申請專利範圍指出本發明的範圍,而非由前文的描述,並且意圖包含在該申請專利範圍的均等物的意義及範圍之內的所有變換。 The inventive concept of the invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the foregoing embodiments are to be considered in all aspects illustrative illustrative The scope of the invention is to be construed as being limited by the scope of the claims

100‧‧‧記憶體單元 100‧‧‧ memory unit

110‧‧‧第一電晶體 110‧‧‧First transistor

112‧‧‧第一存取擴散區域 112‧‧‧First access diffusion area

114‧‧‧第二存取擴散區域 114‧‧‧Second access diffusion area

116‧‧‧存取閘極 116‧‧‧ access gate

130‧‧‧第二電晶體 130‧‧‧Second transistor

132‧‧‧第一儲存擴散區域 132‧‧‧First storage diffusion area

134‧‧‧第二儲存擴散區域 134‧‧‧Second storage diffusion area

136‧‧‧儲存閘極 136‧‧‧Storage gate

150‧‧‧控制電容 150‧‧‧Control Capacitor

152‧‧‧電容接觸栓 152‧‧‧Capacitive contact plug

156‧‧‧控制閘極 156‧‧‧Control gate

Claims (18)

一種非揮發性多次可程式記憶體單元,包括:備有隔離井的基板;設置於該隔離井內的高電壓井區域,其中,該高電壓井區域為記憶體陣列的共同井區域;設置於該高電壓井區域內的第一井及第二井;彼此相鄰且設置於該第二井之上的具有選擇閘極的第一電晶體以及具有浮動閘極的第二電晶體,所述電晶體包括設置鄰近於所述閘極的側邊的第一及第二擴散區域;以及設置於該第一井之上的控制閘極,其中,該控制閘極耦合至該浮動閘極,並且該控制閘極及浮動閘極包含延伸跨過該第一井及該第二井的相同閘極層,以及該控制閘極包括電容。 A non-volatile multi-programmable memory unit comprising: a substrate provided with an isolation well; a high voltage well region disposed in the isolation well, wherein the high voltage well region is a common well region of the memory array; a first well and a second well in the high voltage well region; a first transistor having a selected gate adjacent to each other and disposed above the second well; and a second transistor having a floating gate, the electricity The crystal includes first and second diffusion regions disposed adjacent to sides of the gate; and a control gate disposed over the first well, wherein the control gate is coupled to the floating gate, and the control gate The pole and floating gates comprise the same gate layer extending across the first well and the second well, and the control gate includes a capacitor. 如申請專利範圍第1項所述的記憶體單元,其中,該第一井為第一極性類型,以及該第二井為不同於該第一極性類型的第二極性類型。 The memory unit of claim 1, wherein the first well is of a first polarity type and the second well is of a second polarity type different from the first polarity type. 如申請專利範圍第2項所述的記憶體單元,其中,該第一井為n型井以及該第二井為p型井,其中該浮動閘極以及該選擇閘極之每一者係包含n型金屬氧化半導體,並且其中該控制閘極包含n型電容。 The memory unit of claim 2, wherein the first well is an n-type well and the second well is a p-type well, wherein each of the floating gate and the selection gate comprises An n-type metal oxide semiconductor, and wherein the control gate comprises an n-type capacitor. 如申請專利範圍第3項所述的記憶體單元,其中,藉由Fowler-Nordheim(FN)隧穿效應,該記憶體單元為可 程式。 The memory unit of claim 3, wherein the memory unit is compliant by a Fowler-Nordheim (FN) tunneling effect Program. 如申請專利範圍第3項所述的記憶體單元,其中,藉由Fowler-Nordheim(FN)隧穿效應,該記憶體單元為可抹除。 The memory unit of claim 3, wherein the memory unit is erasable by a Fowler-Nordheim (FN) tunneling effect. 如申請專利範圍第3項所述的記憶體單元,該記憶體單元包括耦合至該第一井的電容接觸栓。 The memory unit of claim 3, wherein the memory unit comprises a capacitive contact plug coupled to the first well. 如申請專利範圍第6項所述的記憶體單元,其中,該高電壓井區域包括深於該第一井及該第二井的深度。 The memory unit of claim 6, wherein the high voltage well region comprises a depth deeper than the first well and the second well. 如申請專利範圍第7項所述的記憶體單元,其中,該隔離井包括深於該高電壓井區域的深度。 The memory unit of claim 7, wherein the isolation well comprises a depth deeper than the high voltage well region. 如申請專利範圍第8項所述的記憶體單元,其中,該高電壓井區域為第二極性類型以及該隔離井為不同於該第二極性類型的第一極性類型。 The memory unit of claim 8, wherein the high voltage well region is of a second polarity type and the isolation well is of a first polarity type different from the second polarity type. 如申請專利範圍第1項所述的記憶體單元,其中,該第一井為第一極性類型,以及該高電壓井區域為不同於該第一極性類型的第二極性類型。 The memory unit of claim 1, wherein the first well is of a first polarity type and the high voltage well region is of a second polarity type different from the first polarity type. 如申請專利範圍第1項所述的記憶體單元,該記憶體單元包括設置於該基板中,介於該第一井及該第二井之間的原生層。 The memory unit of claim 1, wherein the memory unit comprises a native layer disposed in the substrate between the first well and the second well. 一種非揮發性多次可程式記憶體單元,包括:備有第一隔離井及第二隔離井的基板,其中該第二隔離井設置於該第一隔離井之內,且其中,該第二隔離井為環繞記憶體陣列的記憶體單元的共同第二隔離井; 設置於該第二隔離井內的第一井及第二井;彼此相鄰且設置於該第二井之上的具有選擇閘極的第一電晶體以及具有浮動閘極的第二電晶體,所述電晶體包括設置鄰近於所述閘極的側邊的第一及第二擴散區域;以及設置於該第一井之上的控制閘極,其中該控制閘極耦合至該浮動閘極,並且該控制閘極及浮動閘極包含延伸跨過該第一井及該第二井的相同閘極層。 A non-volatile multiple-programmable memory unit includes: a substrate provided with a first isolation well and a second isolation well, wherein the second isolation well is disposed within the first isolation well, and wherein the second The isolation well is a common second isolation well surrounding the memory unit of the memory array; a first well and a second well disposed in the second isolation well; a first transistor having a selection gate adjacent to each other and disposed above the second well; and a second transistor having a floating gate, The transistor includes first and second diffusion regions disposed adjacent to sides of the gate; and a control gate disposed over the first well, wherein the control gate is coupled to the floating gate, and the control gate The pole and floating gates comprise the same gate layer extending across the first well and the second well. 如申請專利範圍第12項所述的記憶體單元,其中,該第一井包括第一極性類型以及該第二井為不同於該第一極性類型的第二極性類型。 The memory unit of claim 12, wherein the first well comprises a first polarity type and the second well is a second polarity type different from the first polarity type. 如申請專利範圍第12項所述的記憶體單元,其中,該記憶體陣列包括AND型陣列設置。 The memory unit of claim 12, wherein the memory array comprises an AND type array arrangement. 如申請專利範圍第12項所述的記憶體單元,其中,該記憶體陣列包括NOR型陣列設置。 The memory unit of claim 12, wherein the memory array comprises a NOR type array arrangement. 如申請專利範圍第12項所述的記憶體單元,該記憶體單元包括介於該第一井及該第二井之間的原生層。 The memory unit of claim 12, wherein the memory unit comprises a native layer between the first well and the second well. 如申請專利範圍第12項所述的記憶體單元,其中:該第一隔離井包括第一極性類型;以及該第二隔離井包括第二極性類型。 The memory unit of claim 12, wherein: the first isolation well comprises a first polarity type; and the second isolation well comprises a second polarity type. 一種用於形成非揮發性多次可程式記憶體單元的方法,包括:提供基板;形成第一隔離井及第二隔離井在該基板中; 形成第一井及第二井在該第二隔離井內,其中,該第二隔離井為環繞記憶體陣列的記憶體單元的共同第二隔離井;形成具有選擇閘極的第一電晶體以及具有浮動閘極的第二電晶體彼此相鄰且於該第二井之上,所述電晶體包括形成於鄰近所述閘極的側邊的第一及第二擴散區域,其中,該第一電晶體及該第二電晶體以串聯耦合,及該第一電晶體及該第二電晶體分享共同第二擴散區域;以及形成控制閘極於該第一井之上,其中該控制閘極耦合至該浮動閘極,並且該控制閘極及浮動閘極包含延伸跨過該第一井及該第二井的相同閘極層,及該控制閘極包括電容。 A method for forming a non-volatile multi-programmable memory unit, comprising: providing a substrate; forming a first isolation well and a second isolation well in the substrate; Forming a first well and a second well in the second isolation well, wherein the second isolation well is a common second isolation well surrounding the memory unit of the memory array; forming a first transistor having a selected gate and a second transistor having a floating gate adjacent to and above the second well, the transistor including first and second diffusion regions formed adjacent sides of the gate, wherein the first transistor And the second transistor is coupled in series, and the first transistor and the second transistor share a common second diffusion region; and a control gate is formed over the first well, wherein the control gate is coupled to the floating gate And the control gate and the floating gate comprise the same gate layer extending across the first well and the second well, and the control gate comprises a capacitor.
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