CN101330107B - Time-after-time programmable memory and manufacturing method thereof - Google Patents
Time-after-time programmable memory and manufacturing method thereof Download PDFInfo
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- CN101330107B CN101330107B CN2007101101813A CN200710110181A CN101330107B CN 101330107 B CN101330107 B CN 101330107B CN 2007101101813 A CN2007101101813 A CN 2007101101813A CN 200710110181 A CN200710110181 A CN 200710110181A CN 101330107 B CN101330107 B CN 101330107B
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Abstract
The invention disclosed a multi-pass programmable memory and a manufacturing method thereof. The multi-pass programmable memory comprises a tunneling dielectric layer, a floating grid, an inter-grid dielectric layer and a control grid. The tunneling dielectric layer is arranged on a base. The floating grid is arranged on the tunneling dielectric layer. The inter-grid dielectric layer is arranged on the floating grid, wherein, the thickness of the part of inter-grid dielectric layer on the edge of the floating grid is larger than that of the part of inter-grid dielectric layer in the center of the floating grid. The control grid is arranged on the inter-grid dielectric layer. In the multi-pass programmable memory, because the thickness of the part of inter-grid dielectric layer on the edge of the floating grid is larger than that of the part of inter-grid dielectric layer in the center of the floating grid, the drain current is not easy to be formed between the apex angle of the floating grid and the control grid, and the rounded apex angle of the floating grid can prevent the point discharge caused by the concentrated electric field, and can also prevent the drain current of the device, thereby the data confining force is enhanced.
Description
Technical field
The present invention relates to a kind of semiconductor device, and be particularly related to a kind of time-after-time programmable memory and manufacture method thereof that can promote data confining force (dataretention).
Background technology
Time-after-time programmable memory (Multi-Time Programmable Memory, MTP) device can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the advantage that the data that deposit in also can not disappear after outage, thus become PC and electronic equipment a kind of storage component part of extensively adopting.
Typical time-after-time programmable memory device generally is to make floating grid (Floating Gate) and control grid (Control Gate) with doped polycrystalline silicon.Floating grid is being controlled between grid and the substrate, and is in floating state, is connected with any circuit.The control grid then joins with word line (Word Line).In addition, also comprise between tunnel oxide (Tunneling Oxide) and grid dielectric layer (Inter-GateDielectric Layer) lay respectively between substrate and the floating grid and floating grid and control grid between.
The problem that the time-after-time programmable memory device more often takes place is the problem of data confining force (data retention) difference.One of the principal element that causes the data confining force difference of time-after-time programmable memory device is a dielectric layer between grid between control grid and the floating grid.That is the data confining force of time-after-time programmable memory device can depend on the quality of dielectric layer between the grid of controlling between grid and the floating grid.
The technology of known multiple programmable storage component part is as follows.At first, form one deck polysilicon layer and one deck mask layer, patterned mask layer and polysilicon layer then, patterned polysilicon layer is as floating grid.Carry out the growth technology of the gate oxide of high tension apparatus (High voltage device), to form the gate oxide of high tension apparatus.Then, remove mask layer, carry out the growth technology of the gate oxide of middle voltage device (Mediumvoltage device) and low-voltage device (Low voltage device) more in regular turn, with the gate oxide of voltage device in forming respectively and low-voltage device, and while dielectric layer between floating grid top formation silicon oxide layer is as grid.Afterwards, form the control grid again.In above-mentioned technology, because dielectric layer is to form in the growth technology of the gate oxide of middle voltage device and low-voltage device between the grid at floating grid top, so its thickness has defective usually less than 150 dusts and make in the dielectric layer between grid.When defectiveness existed in the dielectric layer between the grid between control grid and the floating grid, the electric charge that is stored in the floating grid entered the control grid via above-mentioned defective, just caused the leakage current of device easily.And medium thickness is thinner between the grid between the top corner part of floating grid and the control grid, and easier top corner part at floating grid forms leakage current with controlling between the grid, and influences the reliability of device.
Summary of the invention
The invention provides a kind of time-after-time programmable memory and manufacture method thereof, it is provided with dielectric layer between grid between floating grid and control grid, dielectric layer greater than the thickness at the core of floating grid, therefore can promote the data confining force at the thickness of the marginal portion of floating grid between these grid.
The invention provides a kind of time-after-time programmable memory and manufacture method thereof, its technology is simple, and the drift angle that its floating grid has sphering can promote the data confining force.
The invention provides a kind of time-after-time programmable memory and manufacture method thereof, its technology is simple, and device technology that can peripheral circuit combines, and can reduce cost of manufacture.
The present invention proposes a kind of time-after-time programmable memory, and it comprises dielectric layer between tunnel dielectric layer, floating grid, the first grid, control grid.Tunnel dielectric layer is arranged in the substrate.Floating grid is arranged on the tunnel dielectric layer.Dielectric layer is arranged on the floating grid between the first grid, and wherein dielectric layer has first thickness, has second thickness at the core of floating grid between the first grid in the marginal portion of floating grid, and first thickness is greater than second thickness.The control grid is arranged between the first grid on the dielectric layer.
According to the described time-after-time programmable memory of embodiments of the invention, above-mentioned floating grid has the drift angle of sphering.
According to the described time-after-time programmable memory of embodiments of the invention, above-mentioned time-after-time programmable memory also comprises dielectric layer between second grid.Dielectric layer is arranged at the sidewall of this floating grid between second grid.
According to the described time-after-time programmable memory of embodiments of the invention, above-mentioned control grid extends and is arranged between second grid on the dielectric layer.
According to the described time-after-time programmable memory of embodiments of the invention, between the above-mentioned first grid between dielectric layer and this second grid the material of dielectric layer comprise silica.
According to the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned control grid comprises doped polycrystalline silicon.
According to the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned floating grid comprises doped polycrystalline silicon.
According to the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned tunnel dielectric layer comprises silica.
In the time-after-time programmable memory of the present invention and since between the first grid dielectric layer at the thickness of the marginal portion of floating grid greater than thickness at the core of floating grid.Therefore between the drift angle of floating grid and control grid, be difficult for the formation leakage current.And the drift angle of the sphering of floating grid can be avoided the electric field discharge of concentrating, taper off to a point, and can avoid device creepage, promotes the confining force of data.
The present invention proposes a kind of manufacture method of time-after-time programmable memory, comprises the following steps.At first, provide substrate, and in forming dielectric layer and mask layer between tunnel dielectric layer, first conductor layer, the first grid in the substrate in regular turn.Then, dielectric layer, first conductor layer, tunnel dielectric layer between patterned mask layer, the first grid, the first wherein patterned conductor layer is as floating grid.Form dielectric layer between second grid at the floating grid sidewall, and make the thickness thickening of dielectric layer between the first grid of the marginal portion of floating grid.Then, remove mask layer, and in substrate, form the control grid.
Manufacture method according to the described time-after-time programmable memory of embodiments of the invention, above-mentioned forms dielectric layer between second grid at the floating grid sidewall, and makes the method for the thickness thickening of dielectric layer between the first grid of the marginal portion of floating grid comprise thermal oxidation method.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, between the above-mentioned first grid between the dielectric layer and second grid material of dielectric layer comprise silica.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the method also comprises and carries out thermal oxidation technology after removing mask layer, so that the thickness thickening of dielectric layer between the first grid.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned mask layer is a silicon nitride.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the above-mentioned method that forms the control grid in substrate comprises the following steps.In substrate, form second conductor layer, patterning second conductor layer then earlier.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned control grid comprises doped polycrystalline silicon.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned floating grid comprises doped polycrystalline silicon.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned tunnel dielectric layer comprises silica.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned floating grid has the drift angle of sphering.
In the manufacture method of time-after-time programmable memory of the present invention, owing between mask layer and floating grid, be provided with dielectric layer between the first grid.Can make dielectric layer between the first grid at the thickness thickening of the marginal portion of floating grid and make the drift angle of floating grid therefore can be improved the data reserve force of device by thermal oxidation technology by sphering.And the manufacture method of time-after-time programmable memory of the present invention is simple, can combine with the device technology of general peripheral circuit, and can reduce cost of manufacture.
The present invention proposes a kind of manufacture method of time-after-time programmable memory, comprises the following steps.At first, provide substrate, this substrate comprises first district and second district at least.Forming dielectric layer and mask layer between tunnel dielectric layer, first conductor layer, the first grid in the substrate in regular turn.Then, remove dielectric layer, first conductor layer, tunnel dielectric layer between mask layer in second district, the first grid, and dielectric layer, first conductor layer, tunnel dielectric layer between the mask layer in patterning first district, the first grid, in first district, to form floating grid.Then, form first grid dielectric layer in the substrate in second district, the floating grid sidewall in first district forms dielectric layer between second grid simultaneously, and makes the thickness thickening of dielectric layer between the first grid of the marginal portion of floating grid.After removing mask layer, in the substrate in first district, form the control grid, in the substrate in second district, form first grid.
Manufacture method according to the described time-after-time programmable memory of embodiments of the invention, above-mentioned formation first grid dielectric layer in the substrate in second district, simultaneously the floating grid sidewall in first district forms dielectric layer between second grid, and makes the method for the thickness thickening of dielectric layer between the first grid of the marginal portion of floating grid comprise thermal oxidation method.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, between the above-mentioned first grid between the dielectric layer and second grid material of dielectric layer comprise silica.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned mask layer is a silicon nitride.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, grid is controlled in above-mentioned forming in the substrate in first district, and the step that forms first grid in the substrate in second district is as follows.In substrate, form second conductor layer, patterning second conductor layer then earlier.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned control grid, the material of first grid comprise doped polycrystalline silicon.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned floating grid comprises doped polycrystalline silicon.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the material of above-mentioned tunnel dielectric layer comprises silica.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned floating grid has the drift angle of sphering.
Manufacture method according to the described time-after-time programmable memory of embodiments of the invention, above-mentioned remove dielectric layer, first conductor layer, tunnel dielectric layer between mask layer in second district, the first grid, and dielectric layer, first conductor layer, tunnel dielectric layer between the mask layer in patterning first district, the first grid, as follows with the step that in first district, forms floating grid.At first, in substrate, form patterning photoresist layer, and be mask, remove dielectric layer between mask layer, the first grid, first conductor layer, tunnel dielectric layer with patterning photoresist layer.Then, remove patterning photoresist layer.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned substrate also comprises the 3rd district, comprises the following steps after removing mask layer.Remove dielectric layer between the first grid in the 3rd district, first conductor layer and tunnel dielectric layer, and in the substrate in the 3rd district, form second gate dielectric layer, make the thickness thickening of dielectric layer between the first grid in first district simultaneously.Afterwards, in the substrate in the 3rd district, form second grid
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned formation second gate dielectric layer in the substrate in the 3rd district makes the method for the thickness thickening of dielectric layer between the first grid in first district comprise thermal oxidation method simultaneously.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the step of dielectric layer, first conductor layer and tunnel dielectric layer is as follows between the above-mentioned first grid that removes in the 3rd district.Form patterning photoresist layer in substrate, patterning photoresist floor covers first district and second district.Then, be mask with patterning photoresist layer, remove dielectric layer between the first grid, first conductor layer, tunnel dielectric layer.Afterwards, remove patterning photoresist layer.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned substrate also comprises the 3rd district and the 4th district, after removing mask layer, comprises the following steps.Remove dielectric layer, first conductor layer and tunnel dielectric layer between the first grid in the 3rd district and the 4th district.Then, in the substrate in the 3rd district and the 4th district, form second gate dielectric layer, make the thickness thickening of dielectric layer between the first grid in first district simultaneously.Then, remove second gate dielectric layer in the 4th district, and in the substrate in the 4th district, form the 3rd gate dielectric layer, make the thickness thickening of second gate dielectric layer in dielectric layer between the first grid in first district and the 3rd district simultaneously.Afterwards, in the substrate in the 3rd district, form second grid, and in the substrate in the 4th district, form the 3rd grid.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, above-mentioned formation second gate dielectric layer in the substrate in the 3rd district and the 4th district makes the method for the thickness thickening of dielectric layer between the first grid in first district comprise thermal oxidation method simultaneously.
Manufacture method according to the described time-after-time programmable memory of embodiments of the invention, above-mentioned the 3rd gate dielectric layer that forms in the substrate in the 4th district makes the method for thickness thickening of second gate dielectric layer in dielectric layer between the first grid in first district and the 3rd district comprise thermal oxidation method simultaneously.
According to the manufacture method of the described time-after-time programmable memory of embodiments of the invention, the step of dielectric layer, first conductor layer and tunnel dielectric layer is as follows between the above-mentioned first grid that removes in the 3rd district and the 4th district.Form patterning photoresist layer in substrate, patterning photoresist floor covers first district and second district.With patterning photoresist layer is mask, removes dielectric layer between the first grid, first conductor layer, tunnel dielectric layer.Afterwards, remove patterning photoresist layer.
In the manufacture method of time-after-time programmable memory of the present invention, owing between mask layer and floating grid, be provided with dielectric layer between the first grid.When second district forms first grid dielectric layer, can make dielectric layer between the first grid at the thickness thickening of the marginal portion of floating grid and make the drift angle of floating grid therefore can be improved the data reserve force of device by sphering.
And, in the manufacture method of time-after-time programmable memory of the present invention, during second gate dielectric layer in (and the 4th district) in follow-up formation the 3rd district (reaching the 3rd gate dielectric layer), can make further that the thickness of dielectric layer thickens between the first grid, therefore the manufacture method of time-after-time programmable memory of the present invention is simple, and can reduce cost of manufacture.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below.
Description of drawings
Figure 1A illustrate is the vertical view of time-after-time programmable memory of the present invention.
Figure 1B illustrate among Figure 1A along the section of structure of A-A ' line.
Fig. 1 C illustrate among Figure 1A along the section of structure of B-B ' line.
Fig. 2 A to Fig. 2 F is the manufacturing process profile that illustrates a kind of time-after-time programmable memory of one embodiment of the invention.
Fig. 3 A to Fig. 3 H is the manufacturing process profile that illustrates a kind of time-after-time programmable memory of another embodiment of the present invention.
Description of reference numerals
100,200,300: substrate
102: device isolation structure
104: active area
106,202,202a, 310,310a: tunnel dielectric layer
108: floating grid
108a: drift angle
110,110a, 110b, 206,206a, 206b, 206c, 212,212a, 314,314a, 314b, 314c, 322,322a: dielectric layer between grid
112: the control grid
114,116,218,220,336a, 336b, 338a, 338b, 340a, 340b, 342a, 342b: source/drain regions
204,204a, 214,214a, 312,312a, 332,332a, 332b, 332c, 332d: conductor layer
208,208a, 316,316a: mask layer
210,216,318,324,328,334: patterning photoresist layer
302: memory cell areas
304: the low-voltage device district
306: middle voltage device region
308: high voltage device regions
320,320a, 326,326a, 326b, 330,330a: gate dielectric layer
MC: memory
Embodiment
Figure 1A illustrate is the vertical view of time-after-time programmable memory of the present invention.Figure 1B illustrate among Figure 1A along the section of structure of A-A ' line.Fig. 1 C illustrate among Figure 1A along the section of structure of B-B ' line.
Please be simultaneously with reference to Figure 1A, Figure 1B, Fig. 1 C, time-after-time programmable memory MC of the present invention is arranged in the substrate 100, and this time-after-time programmable memory MC for example is by dielectric layer 110 between tunnel dielectric layer 106, floating grid 108, grid (comprise between grid between dielectric layer 110a and grid dielectric layer 110b), control grid 112 and 114,116 formations of source/drain regions.
Floating grid 108 is arranged on the tunnel dielectric layer 106.The material of floating grid 108 comprises conductor material, for example is doped polycrystalline silicon.Doping in doped polycrystalline silicon can be that the N type mixes, and also can be that the P type mixes.Floating grid 108 for example has the drift angle 108a of sphering (rounding).
Between grid dielectric layer 110 for example by between grid between dielectric layer 110a and grid dielectric layer 110b constituted.Dielectric layer 110a is arranged on the floating grid 108 between grid.Dielectric layer 110a has thickness D1, has thickness D2 at the core of floating grid between grid in the marginal portion of floating grid 108.Thickness D1 is greater than thickness D2.Dielectric layer 110b for example is arranged at the sidewall of floating grid 108 between grid.Because dielectric layer 110a greater than the thickness D2 at the core of floating grid, therefore is difficult for the formation leakage current at the thickness D1 of the marginal portion of floating grid 108 between the drift angle 108a of floating grid 108 and control grid 112 between grid.And the drift angle 108a of the sphering of floating grid 108 can avoid the electric field discharge of concentrating, taper off to a point, and can avoid device creepage, promotes the confining force of data.The material of dielectric layer 110 between grid (between grid between dielectric layer 110a and grid dielectric layer 110b) for example is a silica etc.
Source/drain regions 114,116 for example is arranged in control grid 112 substrate on two sides 100.Source/drain regions 114,116 for example is P type or N type doped region.
Shown in Figure 1A to Fig. 1 C and since between the grid of time-after-time programmable memory of the present invention dielectric layer 110a at the thickness D1 of the marginal portion of floating grid 108 greater than thickness D2 at the core of floating grid.Therefore between the drift angle 108a of floating grid 108 and control grid 112, be difficult for the formation leakage current.And the drift angle 108a of the sphering of floating grid 108 can avoid the electric field discharge of concentrating, taper off to a point, and can avoid device creepage, promotes the confining force of data.
Then, manufacture method of the present invention is described.Fig. 2 A to Fig. 2 F is the manufacturing process profile that illustrates a kind of time-after-time programmable memory of one embodiment of the invention.At Fig. 2 A to Fig. 2 F for illustrating among Figure 1A profile along B-B '.
Please refer to Fig. 2 A, substrate 200 at first is provided.Substrate 200 for example is a silicon base.A plurality of isolation structures (not illustrating) in substrate 200, have been formed with, to define active area.
In substrate 200, form one deck tunnel dielectric layer 202 and one deck conductor layer 204 in regular turn.The material of tunnel dielectric layer 202 for example is a silica.The formation method of tunnel dielectric layer 202 for example is a thermal oxidation method.The material of conductor layer 204 for example is a doped polycrystalline silicon, its formation method for example is to utilize chemical vapour deposition technique to form (not illustrating) behind one deck undoped polycrystalline silicon layer, carry out the ion implantation step forming, or adopt the original position to inject the mode of mixing to form doped polysilicon layer with chemical vapour deposition technique.
Please refer to Fig. 2 B, forming dielectric layer 206 between grid on the conductor layer 204.The material of dielectric layer 206 for example is a silica between grid, and its formation method for example is chemical vapour deposition technique or thermal oxidation method.Certainly, the material of dielectric layer 206 can also be other insulating material between grid, and its formation method for example is to carry out chemical vapour deposition technique according to its material with different reacting gass.Then, dielectric layer 206 forms one deck mask layer 208 between grid.The material of mask layer 208 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Please refer to Fig. 2 C, in substrate 200, form one deck patterning photoresist layer 210.The formation method of patterning photoresist layer 210 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 200, exposes then, develops and form.Then, be mask with patterning photoresist layer 210, remove dielectric layer 206 between part mask layer 208, grid, conductor layer 204, tunnel dielectric layer 202, to form dielectric layer 206a, conductor layer 204a, tunnel dielectric layer 202a between mask layer 208a, grid.Patterned conductor layer 204a is as floating grid.The method that removes dielectric layer 206 between part mask layer 208, grid, conductor layer 204, tunnel dielectric layer 202 comprises the dry-etching method, for example is reactive ion-etching.
Please refer to Fig. 2 D, remove patterning photoresist layer 210.The method that removes patterning photoresist layer 210 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.After removing patterning photoresist layer 210, form dielectric layer 212 between another layer grid at conductor layer 204a (floating grid) sidewall.Dielectric layer 212 also can be formed on substrate 200 surfaces between grid.The formation method of dielectric layer 212 for example is a thermal oxidation method between grid.In the step that forms dielectric layer 212 between grid, the thickness of dielectric layer 206a can thickening between the grid of the marginal portion of conductor layer 204a (floating grid), and makes dielectric layer 206a between grid become dielectric layer 206b between the thickness of the marginal portion of conductor layer 204a (floating grid) is greater than the grid at the thickness of the core of conductor layer 204a (floating grid).The reason of the thickness of dielectric layer 206a meeting thickening is can be oxidized by the conductor layer 204a (floating grid) of mask layer 208a covering between the grid of the marginal portion of conductor layer 204a (floating grid), but the corner portions located of mask layer 208a (that is marginal portion of conductor layer 204a (floating grid)), then carry out the diffusion of horizontal direction because of oxygen, the feasible conductor layer 204a (floating grid) that is positioned at the corner portions located of mask layer 208a still has oxidation in various degree, and makes that the thickness of dielectric layer 206a can thickening between grid.And the drift angle of conductor layer 204a (floating grid) can be by sphering.
Please refer to Fig. 2 E, remove mask layer 208a.The method that removes mask layer 208a for example is dry-etching method or wet etching.After removing mask layer 208a, optionally carry out thermal oxidation technology, so that the integral thickness thickening of dielectric layer 206b between grid forms dielectric layer 206c between grid.Wherein, between grid dielectric layer 206c at the thickness of the marginal portion of conductor layer 204a (floating grid) greater than thickness at the core of conductor layer 204a (floating grid).Then, in substrate 200, form another layer conductor layer 214 in regular turn.The material of conductor layer 214 for example is a doped polycrystalline silicon, its formation method for example is to utilize chemical vapour deposition technique to form (not illustrating) behind one deck undoped polycrystalline silicon layer, carry out the ion implantation step forming, or adopt the original position to inject the mode of mixing to form doped polysilicon layer with chemical vapour deposition technique.The material of conductor layer 214 can also be other metal materials.
Then, in substrate 200, form one deck patterning photoresist layer 216.The formation method of patterning photoresist layer 216 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 200, exposes then, develops and form.
Please refer to Fig. 2 F, is mask with patterning photoresist layer 216, removes between segment conductor layer 214, grid dielectric layer 212 to form dielectric layer 212a between conductor layer 214a, grid.Patterned conductor layer 214a is as the control grid.The method that removes dielectric layer 212 between segment conductor layer 214, grid comprises the dry-etching method, for example is reactive ion-etching.Then, remove patterning photoresist layer 216.The method that removes patterning photoresist layer 216 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.After removing patterning photoresist layer 216, in conductor layer 214a (control grid) substrate on two sides 200, form source/drain regions 218,220.The formation method of source/drain regions 218,220 for example is to be mask with conductor layer 214a (control grid), the injection technology of mixing.Known as for the follow-up technology of finishing time-after-time programmable memory by those skilled in the art, do not repeat them here.
In the manufacture method of time-after-time programmable memory of the present invention, owing between mask layer 208a and conductor layer 204a (floating grid), be provided with dielectric layer 206a between grid.Forming between grid in the dielectric layer 212, can make dielectric layer 206a between grid at the thickness thickening of the marginal portion of conductor layer 204a (floating grid) and make the drift angle of conductor layer 204a (floating grid) therefore can be improved the data reserve force of device by sphering.And the manufacture method of time-after-time programmable memory of the present invention is simple, can combine with the device technology of general peripheral circuit, and can reduce cost of manufacture.
Below, please according to Fig. 3 A to Fig. 3 H, the embodiment that combines with the device technology of technology that time-after-time programmable memory of the present invention is described and general peripheral circuit.Fig. 3 A to Fig. 3 F is the manufacturing process profile that illustrates a kind of time-after-time programmable memory of another embodiment of the present invention.
Please refer to Fig. 3 A, substrate 300 at first is provided.Substrate 300 for example is a silicon base.A plurality of isolation structures (not illustrating) in substrate 300, have been formed with, to define active area.Substrate 300 comprises memory cell areas 302, low-voltage device district 304, middle voltage device region 306 and high voltage device regions 308.Memory cell areas 302 for example is the zone that forms memory cell.Low-voltage device district 304, middle voltage device region 306 for example are the zones that forms peripheral circuit with high voltage device regions 308.
In substrate 300, form one deck tunnel dielectric layer 310 and one deck conductor layer 312 in regular turn.The material of tunnel dielectric layer 310 for example is a silica.The formation method of tunnel dielectric layer 310 for example is a thermal oxidation method.The material of conductor layer 312 for example is a doped polycrystalline silicon, its formation method for example is to utilize chemical vapour deposition technique to form (not illustrating) behind one deck undoped polycrystalline silicon layer, carry out the ion implantation step forming, or adopt the original position to inject the mode of mixing to form doped polysilicon layer with chemical vapour deposition technique.
Please refer to Fig. 3 B, forming dielectric layer 314 between grid on the conductor layer 312.The material of dielectric layer 314 for example is a silica between grid, and its formation method for example is chemical vapour deposition technique or thermal oxidation method.Certainly, the material of dielectric layer 314 can also be other insulating material between grid, and its formation method for example is to carry out chemical vapour deposition technique according to its material with different reacting gass.Then, on dielectric layer between grid 314, form one deck mask layer 316.The material of mask layer 316 for example is a silicon nitride, and its formation method for example is a chemical vapour deposition technique.
Then, in substrate 300, form one deck patterning photoresist layer 318.The formation method of patterning photoresist layer 318 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 300, exposes then, develops and form.Patterning photoresist floor 318 covers low-voltage device district 304, middle voltage device region 306, and exposes high voltage device regions 308.And, patterning photoresist layer 318 in memory cell areas 302 for being used to define floating grid.
Please refer to Fig. 3 C, with patterning photoresist layer 318 is mask, remove dielectric layer 314, conductor layer 312, tunnel dielectric layer 310 between mask layer 316 in the high voltage device regions 308, grid, and between the mask layer 316 of patterning memory cell areas 302, grid dielectric layer 314, conductor layer 312, tunnel dielectric layer 310 to form dielectric layer 314a, conductor layer 312a, tunnel dielectric layer 310a between mask layer 316a, grid.Patterned conductor layer 312a is as floating grid.And dielectric layer 314, conductor layer 312, tunnel dielectric layer 310 can not be removed between the mask layer 316 in low-voltage device district 304, middle voltage device region 306, grid.The method that removes dielectric layer 314 between part mask layer 316, grid, conductor layer 312, tunnel dielectric layer 310 comprises the dry-etching method, for example is reactive ion-etching.
Then, remove patterning photoresist layer 318.The method that removes patterning photoresist layer 318 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.After removing patterning photoresist layer 318, form gate dielectric layer 320 in the substrate 300 in high voltage device regions 308, form dielectric layer 322 between another layer grid at the conductor layer 312a of memory cell areas 302 (floating grid) sidewall simultaneously.Dielectric layer 322 also can be formed on substrate 300 surfaces between grid.That is gate dielectric layer 320 dielectric layer 322 with between grid is being made with in the technology.The formation method of dielectric layer 322 for example is a thermal oxidation method between gate dielectric layer 320 and grid.In the step that forms dielectric layer 322 between gate dielectric layer 320 and grid, the thickness of dielectric layer 314a can thickening between the grid of the marginal portion of conductor layer 312a (floating grid), and make dielectric layer 314a between grid at the thickness of the marginal portion of conductor layer 312a (floating grid) greater than thickness at the core of conductor layer 312a (floating grid).The reason of the thickness of dielectric layer 314a meeting thickening is can be oxidized by the conductor layer 312a (floating grid) of mask layer 316a covering between the grid of the marginal portion of conductor layer 312a (floating grid), but the corner portions located of mask layer 316a (that is marginal portion of conductor layer 312a (floating grid)), then carry out the diffusion of horizontal direction because of oxygen, the feasible conductor layer 312a (floating grid) that is positioned at the corner portions located of mask layer 316a still has oxidation in various degree, and makes that the thickness of dielectric layer 314a can thickening between grid.And the drift angle of conductor layer 312a (floating grid) can be by sphering.
Please refer to Fig. 3 D, remove mask layer 316a.The method that removes mask layer 316a for example is dry-etching method or wet etching.Then, in substrate 300, form one deck patterning photoresist layer 324.The formation method of patterning photoresist layer 324 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 300, exposes then, develops and form.Patterning photoresist layer 324 covers memory cell areas 302, high voltage device regions 308, and exposes low-voltage device district 304, middle voltage device region 306.With patterning photoresist layer 324 is mask, removes dielectric layer 314, conductor layer 312, tunnel dielectric layer 310 between the grid in low-voltage device district 304, the middle voltage device region 306.
Please refer to Fig. 3 E, remove patterning photoresist layer 324.The method that removes patterning photoresist layer 324 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.Then, form gate dielectric layer 326 in the substrate 300 in low-voltage device district 304, middle voltage device region 306.The formation method of gate dielectric layer 326 for example is a thermal oxidation method.In the step that forms gate dielectric layer 326, the integral thickness thickening of dielectric layer 314a between the grid in memory cell areas 302 forms dielectric layer 314b between grid.
Then, in substrate 300, form one deck patterning photoresist layer 328.The formation method of patterning photoresist layer 328 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 300, exposes then, develops and form.Patterning photoresist layer 328 covers memory cell areas 302, high voltage device regions 308, middle voltage device region 306, and exposes low-voltage device district 304.
Please refer to Fig. 3 F, is mask with patterning photoresist layer 328, removes the gate dielectric layer 326 in low-voltage device district 304.The method that removes the gate dielectric layer 326 in low-voltage device district 304 for example is dry-etching method or wet etching.Then, remove patterning photoresist layer 328.The method that removes patterning photoresist layer 328 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.Then, in the substrate 300 in low-voltage device district 304, form gate dielectric layer 330.The formation method of gate dielectric layer 330 for example is a thermal oxidation method.In the step that forms gate dielectric layer 330, the integral thickness thickening of dielectric layer 314b between the grid in memory cell areas 302 forms dielectric layer 314c between grid.And the thickness of the gate dielectric layer 326 in the middle voltage device region 306 is thickening also, and forms gate dielectric layer 326a.The thickness of gate dielectric layer 320 is greater than the thickness of gate dielectric layer 326a.The thickness of gate dielectric layer 326a is greater than the thickness of gate dielectric layer 330.
Please refer to Fig. 3 G, in substrate 300, form another layer conductor layer 332 in regular turn.The material of conductor layer 332 for example is a doped polycrystalline silicon, its formation method for example is to utilize chemical vapour deposition technique to form (not illustrating) behind one deck undoped polycrystalline silicon layer, carry out the ion implantation step forming, or adopt the original position to inject the mode of mixing to form doped polysilicon layer with chemical vapour deposition technique.The material of conductor layer 332 can also be other metal materials.
Then, in substrate 300, form one deck patterning photoresist layer 334.The formation method of patterning photoresist layer 334 for example is to form one deck photo anti-corrosion agent material layer earlier in whole substrate 300, exposes then, develops and form.
Please refer to Fig. 3 H, with patterning photoresist layer 334 is mask, remove dielectric layer 322 between segment conductor layer 332, grid, gate dielectric layer 320, gate dielectric layer 326a, gate dielectric layer 330, to form dielectric layer 322a, gate dielectric layer 320a, gate dielectric layer 326b, gate dielectric layer 330a between conductor layer 332a, 332b, 332c, 332d, grid.Patterned conductor layer 332a is as the control grid.Patterned conductor layer 332b, 332c, 332d are as grid.The method that removes dielectric layer 322 between segment conductor layer 332, grid, gate dielectric layer 320, gate dielectric layer 326a, gate dielectric layer 330 comprises the dry-etching method, for example is reactive ion-etching.Then, remove patterning photoresist layer 334.The method that removes patterning photoresist layer 334 for example is that wet type is delustered and caused resist method or dry type and deluster and cause the resist method.After removing patterning photoresist layer 334, in conductor layer 332a (control grid) and conductor layer 332b, 332c, 332d (grid) substrate on two sides 300, form source/drain regions 336a, 336b, 338a, 338b, 340a, 340b, 342a, 342b respectively.The formation method of source/drain regions 336a, 336b, 338a, 338b, 340a, 340b, 342a, 342b for example is to be mask with conductor layer 332a (control grid) and conductor layer 332b, 332c, 332d (grid), the injection technology of mixing.
Shown in Fig. 3 H, the thickness of gate dielectric layer 320a is greater than the thickness of gate dielectric layer 326b.The thickness of gate dielectric layer 326b is greater than the thickness of gate dielectric layer 330a.In high voltage device regions 308, grid 322d, gate dielectric layer 320a, source/drain regions 342a, 342b constitute high tension apparatus.Gate dielectric layer 320a thickness for example is the 970 Izod right sides, and the start voltage of this high tension apparatus for example is 32 volts.In middle voltage device region 306, voltage device during grid 322c, gate dielectric layer 326b, source/drain regions 340a, 340b constitute.Gate dielectric layer 326b thickness for example is the 120 Izod right sides, and start voltage of voltage device for example is 5.5 volts in this.In low-voltage device district 304, grid 322b, gate dielectric layer 330a, source/drain regions 338a, 338b constitute low-voltage device.Gate dielectric layer 330a thickness for example is the 33 Izod right sides, and the start voltage of this low-voltage device for example is 1.8 volts.Known as for the follow-up technology of finishing time-after-time programmable memory by those skilled in the art, do not repeat them here.
In the above-described embodiments, having four districts such as memory cell areas 302, low-voltage device district 304, middle voltage device region 306 and high voltage device regions 308 with substrate 300 is that example explains.Certainly, the manufacture method of time-after-time programmable memory of the present invention can also be applicable to the substrate that only has a memory cell areas 302 and a periphery circuit region (one of them of high voltage device regions 308, low-voltage device district 304 or middle voltage device region 306); Go for only having memory cell areas 302 and more than or equal to two periphery circuit regions (high voltage device regions 308 and low-voltage device district 304 (or middle voltage device region 306 wherein more than two) substrate; Perhaps also applicable to having memory cell areas 302 and greater than the substrate of three periphery circuit regions.
In the manufacture method of time-after-time programmable memory of the present invention, owing between mask layer 316a and conductor layer 312a (floating grid), be provided with dielectric layer 314a between grid.In the gate dielectric layer 320 that forms high tension apparatus, can make dielectric layer 314a between grid at the thickness thickening of the marginal portion of conductor layer 312a (floating grid) and make the drift angle of conductor layer 312a (floating grid) therefore can be improved the data reserve force of device by sphering.
And, in follow-up formation between the gate dielectric layer 326a of voltage device and the low-voltage device during dielectric layer 330, the thickness of dielectric layer 314a between grid is thickened, therefore the manufacture method of time-after-time programmable memory of the present invention is simple, can combine with the device technology of general peripheral circuit, and can reduce cost of manufacture.
In sum, in the time-after-time programmable memory of the present invention since between grid dielectric layer at the thickness of the marginal portion of floating grid greater than thickness at the core of floating grid.Therefore between the drift angle of floating grid and control grid, be difficult for the formation leakage current.And the drift angle of the sphering of floating grid can be avoided the electric field discharge of concentrating, taper off to a point, and can avoid device creepage, promotes the confining force of data.
In the manufacture method of time-after-time programmable memory of the present invention, owing between mask layer and floating grid, be provided with dielectric layer between grid.Can make dielectric layer between grid at the thickness thickening of the marginal portion of floating grid and make the drift angle of floating grid therefore can be improved the data reserve force of device by thermal oxidation technology by sphering.And the manufacture method of time-after-time programmable memory of the present invention is simple, can combine with the device technology of general peripheral circuit, and can reduce cost of manufacture.
When the device technology of the manufacture method of time-after-time programmable memory of the present invention and general peripheral circuit combines, owing between mask layer and floating grid, be provided with dielectric layer between grid.When forming the gate dielectric layer of high tension apparatus, can make dielectric layer between grid at the thickness thickening of the marginal portion of conductor layer (floating grid) and make the drift angle of floating grid therefore can be improved the data reserve force of device by sphering.
And, in follow-up formation between the gate dielectric layer of voltage device and the low-voltage device during dielectric layer, can make further that the thickness of dielectric layer thickens between grid, therefore the manufacture method of time-after-time programmable memory of the present invention is simple, and can reduce cost of manufacture.
Claims (33)
1. time-after-time programmable memory comprises:
Tunnel dielectric layer is arranged in the substrate;
Floating grid is arranged on this tunnel dielectric layer;
Dielectric layer between the first grid is arranged on this floating grid, and wherein dielectric layer has first thickness, has second thickness at the core of this floating grid between this first grid in the marginal portion of this floating grid, and this first thickness is greater than this second thickness;
Dielectric layer between second grid is arranged at the sidewall of this floating grid; And
The control grid is arranged between this first grid on the dielectric layer, and extends and be arranged between these second grid on the dielectric layer.
2. time-after-time programmable memory as claimed in claim 1, wherein this floating grid has the drift angle of sphering.
3. time-after-time programmable memory as claimed in claim 1, wherein between this first grid between dielectric layer and this second grid the material of dielectric layer comprise silica.
4. time-after-time programmable memory as claimed in claim 1, wherein the material of this control grid comprises doped polycrystalline silicon.
5. time-after-time programmable memory as claimed in claim 1, wherein the material of this floating grid comprises doped polycrystalline silicon.
6. time-after-time programmable memory as claimed in claim 1, wherein the material of this tunnel dielectric layer comprises silica.
7. the manufacture method of a time-after-time programmable memory comprises:
Substrate is provided;
Forming dielectric layer and mask layer between tunnel dielectric layer, first conductor layer, the first grid in this substrate in regular turn;
Dielectric layer, this first conductor layer, this tunnel dielectric layer between this mask layer of patterning, this first grid, this wherein patterned first conductor layer is as floating grid;
Form dielectric layer between second grid at this floating grid sidewall, and make the thickness thickening of dielectric layer between this first grid of the marginal portion of this floating grid;
Remove this mask layer; And
In this substrate, form the control grid.
8. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein form dielectric layer between these second grid, and make the method for the thickness thickening of dielectric layer between this first grid of the marginal portion of this floating grid comprise thermal oxidation method at this floating grid sidewall.
9. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein between this first grid between dielectric layer and this second grid the material of dielectric layer comprise silica.
10. the manufacture method of time-after-time programmable memory as claimed in claim 7 wherein removes after this mask layer, also comprises and carries out thermal oxidation technology, so that the thickness thickening of dielectric layer between this first grid.
11. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein the material of this mask layer is a silicon nitride.
12. the manufacture method of time-after-time programmable memory as claimed in claim 7, the method that wherein forms this control grid in this substrate comprises:
In this substrate, form second conductor layer; And
This second conductor layer of patterning.
13. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein the material of this control grid comprises doped polycrystalline silicon.
14. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein the material of this floating grid comprises doped polycrystalline silicon.
15. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein the material of this tunnel dielectric layer comprises silica.
16. the manufacture method of time-after-time programmable memory as claimed in claim 7, wherein this floating grid has the drift angle of sphering.
17. the manufacture method of a time-after-time programmable memory comprises:
Substrate is provided, and this substrate comprises first district and second district at least;
Forming dielectric layer and mask layer between tunnel dielectric layer, first conductor layer, the first grid in this substrate in regular turn;
Remove dielectric layer, this first conductor layer, this tunnel dielectric layer between this mask layer in this second district, this first grid, and dielectric layer, this first conductor layer, this tunnel dielectric layer between this mask layer in this first district of patterning, this first grid, in this first district, to form floating grid;
Form first grid dielectric layer in this substrate in this second district, this floating grid sidewall in this first district forms dielectric layer between second grid simultaneously, and makes the thickness thickening of dielectric layer between this first grid of the marginal portion of this floating grid;
Remove this mask layer; And
In this substrate in first district, form the control grid, in this substrate in this second district, form first grid.
18. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein in this substrate in this second district, form this first grid dielectric layer, simultaneously this floating grid sidewall in this first district forms dielectric layer between these second grid, and makes the method for the thickness thickening of dielectric layer between this first grid of the marginal portion of this floating grid comprise thermal oxidation method.
19. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein between this first grid between dielectric layer and this second grid the material of dielectric layer comprise silica.
20. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein the material of this mask layer is a silicon nitride.
21. the manufacture method of time-after-time programmable memory as claimed in claim 17 wherein forms this control grid in this substrate in this first district, the step that forms this first grid in this substrate in this second district comprises:
In this substrate, form second conductor layer; And
This second conductor layer of patterning.
22. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein the material of this control grid, this first grid comprises doped polycrystalline silicon.
23. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein the material of this floating grid comprises doped polycrystalline silicon.
24. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein the material of this tunnel dielectric layer comprises silica.
25. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein this floating grid has the drift angle of sphering.
26. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein remove dielectric layer, this first conductor layer, this tunnel dielectric layer between this mask layer in this second district, this first grid, and dielectric layer, this first conductor layer, this tunnel dielectric layer between this mask layer in this first district of patterning, this first grid, comprise with the step that in this first district, forms this floating grid:
In this substrate, form patterning photoresist layer;
With this patterning photoresist layer is mask, removes dielectric layer between this mask layer, this first grid, this first conductor layer, this tunnel dielectric layer; And
Remove this patterning photoresist layer.
27. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein this substrate also comprises the 3rd district, after removing this mask layer, comprising:
Remove dielectric layer between this first grid in the 3rd district, this first conductor layer and this tunnel dielectric layer;
In this substrate in the 3rd district, form second gate dielectric layer, make the thickness thickening of dielectric layer between this first grid in this first district simultaneously; And
In this substrate in the 3rd district, form second grid.
28. the manufacture method of time-after-time programmable memory as claimed in claim 27 wherein forms this second gate dielectric layer in this substrate in the 3rd district, make the method for the thickness thickening of dielectric layer between this first grid in this first district comprise thermal oxidation method simultaneously.
29. the manufacture method of time-after-time programmable memory as claimed in claim 27, the step that wherein removes dielectric layer, this first conductor layer and this tunnel dielectric layer between this first grid in the 3rd district comprises:
Form patterning photoresist layer in this substrate, this patterning photoresist floor covers this first district and this second district;
With this patterning photoresist layer is mask, removes dielectric layer between this first grid, this first conductor layer, this tunnel dielectric layer; And
Remove this patterning photoresist layer.
30. the manufacture method of time-after-time programmable memory as claimed in claim 17, wherein this substrate also comprises the 3rd district and the 4th district, after removing this mask layer, comprising:
Remove dielectric layer between this first grid in the 3rd district and the 4th district, this first conductor layer and this tunnel dielectric layer;
In this substrate in the 3rd district and the 4th district, form second gate dielectric layer, make the thickness thickening of dielectric layer between this first grid in this first district simultaneously;
Remove this second gate dielectric layer in the 4th district;
In this substrate in the 4th district, form the 3rd gate dielectric layer, make the thickness thickening of this second gate dielectric layer in dielectric layer between this first grid in this first district and the 3rd district simultaneously; And
In this substrate in the 3rd district, form second grid, and in this substrate in the 4th district, form the 3rd grid.
31. the manufacture method of time-after-time programmable memory as claimed in claim 30, wherein in this substrate in the 3rd district and the 4th district, form this second gate dielectric layer, make the method for the thickness thickening of dielectric layer between this first grid in this first district comprise thermal oxidation method simultaneously.
32. the manufacture method of time-after-time programmable memory as claimed in claim 30, wherein in this substrate in the 4th district, form the 3rd gate dielectric layer, make the method for thickness thickening of this second gate dielectric layer in dielectric layer between this first grid in this first district and the 3rd district comprise thermal oxidation method simultaneously.
33. the manufacture method of time-after-time programmable memory as claimed in claim 30, the step that wherein removes dielectric layer, this first conductor layer and this tunnel dielectric layer between this first grid in the 3rd district and the 4th district comprises:
Form patterning photoresist layer in this substrate, this patterning photoresist floor covers this first district and this second district;
With this patterning photoresist layer is mask, removes dielectric layer between this first grid, this first conductor layer, this tunnel dielectric layer; And
Remove this patterning photoresist layer.
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| JP5458050B2 (en) * | 2011-03-30 | 2014-04-02 | 日本碍子株式会社 | Manufacturing method of electrostatic chuck |
| CN105047667B (en) * | 2014-04-16 | 2018-04-13 | 新加坡商格罗方德半导体私人有限公司 | Simple and cost free multiple programmable structure |
| CN107623003A (en) * | 2017-09-06 | 2018-01-23 | 上海华力微电子有限公司 | A kind of forming method of flash memory unit structure |
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