KR100250682B1 - Manufacturing method of a non-volatile memory device - Google Patents
Manufacturing method of a non-volatile memory device Download PDFInfo
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- KR100250682B1 KR100250682B1 KR1019930030786A KR930030786A KR100250682B1 KR 100250682 B1 KR100250682 B1 KR 100250682B1 KR 1019930030786 A KR1019930030786 A KR 1019930030786A KR 930030786 A KR930030786 A KR 930030786A KR 100250682 B1 KR100250682 B1 KR 100250682B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 125000006850 spacer group Chemical group 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Abstract
Description
제1도는 종래기술에 따른 플래쉬 EEPROM 셀 편면도,1 is a flash EEPROM cell one side view according to the prior art,
제2도는 제1도의 A-A' 단면도,2 is a cross-sectional view taken along line A-A 'of FIG.
제3도는 본 발명에 의해 최종적으로 얻어지는 플로팅 게이트 격리 형태를 나타내는 단면도,3 is a cross-sectional view showing a floating gate isolation form finally obtained by the present invention,
제4a도 내지 제4g도는 본 발명의 일실시예에 따른 플로팅 게이트 절연막 형성 공정도.4A through 4G are flowcharts of forming a floating gate insulating film according to an exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 필드 산화막 2 : 플로팅 게이트용 폴리실리콘막DESCRIPTION OF SYMBOLS 1: Field oxide film 2: Polysilicon film for floating gate
3 : 컨트롤 게이트용 폴리시리콘막 4 : 절연막 스페이서3: polysilicon film for control gate 4: insulating film spacer
5 : 희생 산화막 6 : 스페이서 형성용 폴리실리콘막5: sacrificial oxide film 6: polysilicon film for spacer formation
7 : 터널 산화막 8 : 평탄화용 물질7 tunnel oxide film 8 material for planarization
본 발명은 플래쉬 EEPROM, EPROM, EEPROM 등과 같이 플로팅 게이트(Floation Gate)에 전자를 주입시킴으로써 정보를 저장하고, 플로팅 게이트로부터 전자를 빼냄으로써 정보를 지우는 비휘발성 메모리(Non-Volatile memory) 소자 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a non-volatile memory device in which information is stored by injecting electrons into a floating gate, such as a flash EEPROM, EPROM, EEPROM, and the like, and information is erased by extracting electrons from the floating gate. It is about.
종래의 플래쉬 EEPROM 셀 은 플로팅 게이트로 쓰이는 폴리실리콘의 한 변을 포토리소그래피(Photolithography) 공정에 의해 형성하고 다른 한 변은 컨트롤 게이트(Control Gate) 로 쓰이는 폴리실리콘 패턴을 이용하여 자기 정렬방식으로 식각하였다.In the conventional flash EEPROM cell, one side of a polysilicon used as a floating gate is formed by a photolithography process, and the other side is etched by a self-aligning method using a polysilicon pattern used as a control gate. .
제1도는 상기 설명과 같은 종래기술에 따른 플래쉬 EEPROM 셀 평면도이고, 제2도는 제1도의 A-A' 단면도로서, 도면에서 1은 필드 산화막, 2는 플로팅게이트용 폴리실리콘막, 3은 컨트롤 게이트용 폴리실리콘막을 각각 나타낸다.1 is a plan view of a flash EEPROM cell according to the prior art as described above, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1, in which 1 is a field oxide film, 2 is a polysilicon film for floating gate, and 3 is a poly for control gate. Each silicon film is shown.
이때, 플로팅게이트용 폴리실리콘간의 공간(Space, 제2도의 S1)은 포토리소그래피 작업시 디파인(define)되는 관계로 리소그래피 장비가 디파인 할 수 있는 최소형상크기(Minimum Feature Size) 이하로 줄일 수 없다. 이 플로팅 게이트용 폴리실리콘 사이의 공간은 단순히 플로팅 게이트 간의 단절을 위한 것이므로, 플로팅 게이트 사이를 단절시키면서 공간의 길이를 줄일 수 있다면 그만큼 셀 크기가 줄어들어 경제적이다. 뿐만아니라 플로팅게이트용 폴리실리콘과 컨트롤 게이트용 폴리실리콘 사이의 오버랩되는 영역(제1도의 빗금부위)이 클수록 프로그램 및 이레이즈(Program/Erase) 특성에 영향을 미치는 컨트롤 게이트와 플로팅 게이트 간 커플링 율(Coupling Ratio)이 증가하여 프로그램 및 이레이즈 특성이 향상되는데, 플로팅게이트용 폴리실리콘막간의 공간 길이를 줄이는 대신 필드 산화막과 플로팅게이트용 폴리실리콘막의 오버랩(제1도의 W)길이를 늘이는 방법으로 동일한 셀 크기에서 프로그램 및 에라스 특성을 대폭 향상시킬 수 있다.At this time, the space between the floating gate polysilicon (S1 in FIG. 2) is defined as fine during the photolithography operation, and thus the lithography apparatus cannot be reduced below the minimum feature size that the lithography apparatus can define. Since the space between the polysilicons for the floating gate is simply for disconnection between the floating gates, if the length of the space can be reduced while disconnecting between the floating gates, the cell size is reduced and economical. In addition, the larger the overlapping area between the polysilicon for the floating gate and the polysilicon for the control gate (the hatched portion in FIG. 1), the higher the coupling rate between the control gate and the floating gate affecting the program and erase characteristics. (Coupling Ratio) is increased to improve program and erase characteristics.The same method is used to increase the overlap (W in Fig. 1) between the field oxide film and the floating gate polysilicon film, instead of reducing the space length between the floating gate polysilicon film. Program and Eras characteristics can be greatly improved in cell size.
따라서, 본 발명은 포토리소그래피 공정으로 디파인 해오던 플로팅 게이트용 폴리실리콘막간의 공간을 절연막 스페이서(Spacer) 및 에치백(Etch Back) 공정을 이용하여 형성하여 셀의 크기를 줄이거나 소자의 특성을 향상 시키는 비휘발성 메모리 소자 제조 방법을 제공함을 그 목적으로 한다.Accordingly, the present invention forms a space between the polysilicon films for floating gates, which have been defined by a photolithography process, using an insulating layer spacer and an etch back process to reduce the size of a cell or improve device characteristics. It is an object of the present invention to provide a method for manufacturing a nonvolatile memory device.
상기 목적을 달성하기 위하여 안출된 본 발명은 반도체 기판상에 필드 산화막, 희생 산화막을 차례로 형성하는 단계, 스페이서 형성용 물질막을 증착하고 포토리소그래피 공정에 의해 필드 산화막 중앙에서 스페이서 형성용 물질막이 절단되도록 패턴닝하는 단계, 웨이퍼 전체구조 상부에 절연막을 형성하고 다시 전면식각하여 상기 스페이서 형성용 물질막 패턴 측벽에 절연막 스페이서를 형성하는 단계, 상기 스페이서 형성용 물질막 패턴, 희생산화막를 차례로 제거하고 터널 산화막, 플로팅 게이트용 폴리실리콘막을 차례로 형성하는 단계, 웨이퍼 전체구조상부에 평탄화용 물질을 형성한 다음에 절연막 스페이서 상단의 플로팅 게이트용 폴리실리콘막이 제거될때까지 에치 백(Etch-Back)하고 남은 평탄화용 물질을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a field oxide film, a sacrificial oxide film on a semiconductor substrate, and depositing a material film for forming a spacer, and then cutting the material film for spacer formation at the center of the field oxide film by a photolithography process. Forming an insulating film on the sidewalls of the material layer pattern for forming the spacers, and forming an insulating film spacer on the sidewalls of the material forming the spacer layer; sequentially removing the material layer pattern for forming the spacers and the sacrificial oxide film, followed by tunnel oxide film and floating Forming a gate polysilicon film in sequence, forming a planarization material on the entire structure of the wafer, and then etching back until the floating gate polysilicon film on the insulating film spacer is removed, and remaining planarization material is removed. Including the steps to make And that is characterized.
이하, 본 발명을 제3도 내지 제4g도를 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 3 to 4g.
제3도는 본 발명에 의해 최종적으로 얻어지는 플로팅 게이트 및 절연막 단면을 나타낸 것으로, 도면에서 1은 필드 산화막, 2는 플로팅 게이트용 폴리실리콘막, 3은 컨트롤 게이트용 폴리실리콘막, 4는 절연막 스페이서를 각각 나타내며, 플로팅 게이트 사이의 공간(도면의 S2)이 제2도의 종래기술때(제2도의 S1)보다 대폭 감소하였음을 나타낸다. 따라서 다른 모든 레리아웃(Layout)이 동일하다면 플로팅 게이트와 컨트롤 게이트 사이의 오버랩되는 영역이 증가하므로 커플링 율(Coupling Ratio)이 매우 커지며, 동일한 커플링 율을 갖도록 레이아웃을 달리 할 경우에는 셀 크기가 감소하게 된다.3 is a cross-sectional view of a floating gate and an insulating film finally obtained by the present invention, in which 1 is a field oxide film, 2 is a polysilicon film for a floating gate, 3 is a polysilicon film for a control gate, and 4 is an insulating film spacer. This indicates that the space between the floating gates (S2 in the figure) is significantly reduced than in the prior art of FIG. 2 (S1 in FIG. 2). Therefore, if all other layouts are the same, the overlapping area between the floating gate and the control gate is increased, so the coupling ratio is very large, and the cell size is different when the layout is changed to have the same coupling ratio. Will decrease.
제4a도내지 제4g도를 통하여 본 발명의 실시예를 설명하면, 도면에서 1은 필드 산화막, 2는 플로팅 게이트용 폴리실리콘막, 3은 커트롤 게이트용 폴리실리콘막, 4는 절연막 스페이서, 5는 희생 산화막, 6은 스페이서 형성용 폴리실리콘막, 7은 터널 산화막, 8은 평탄화용 물질을 각각 나타낸다.4A through 4G, an embodiment of the present invention will be described with reference to FIG. 1, where 1 is a field oxide film, 2 is a polysilicon film for a floating gate, 3 is a polysilicon film for a control gate, 4 is an insulating film spacer, and 5 Is a sacrificial oxide film, 6 is a polysilicon film for spacer formation, 7 is a tunnel oxide film, and 8 is a planarization material.
제4a도는 반도체 기판상에 필드 산화막(1)을 형성하고 희생 산화막(Sacrificial Oxide, 2)을 300-500Å 형성한 상태의 단면도이다.4A is a cross-sectional view of a field oxide film 1 formed on a semiconductor substrate and a sacrificial oxide film 300-500 Å formed.
이어서, 제4b도와 같이 스페이서 형성용 폴리실리콘막(6)을 증착하고 포토리소그래피 공정에 의해 상기 필드 산화막(1) 중앙에서 스페이서 형성용 폴리실리콘막(6)이 절단되도록 패턴닝한다.Subsequently, as shown in FIG. 4B, a spacer-forming polysilicon film 6 is deposited and patterned so that the spacer-forming polysilicon film 6 is cut at the center of the field oxide film 1 by a photolithography process.
그리고, 제4c도에 도시된 바와같이 웨이퍼 전체구조 상부에 ONO막 또는 산화막과 같은 절연막을 형성하고 다시 전면식각하여 상기 스페이서 형성용 폴리실리콘막(6) 패턴 측벽에 절연막 스페이서(4)를 형성시킨다.As shown in FIG. 4C, an insulating film, such as an ONO film or an oxide film, is formed on the entire wafer structure and then etched back to form an insulating film spacer 4 on the sidewalls of the polysilicon film 6 for forming the spacer. .
계속해서, 제4d도와 같이 상기 스페이서 형성용 폴리실리콘막(6) 패턴을 식각공정에 의해 제거하면, 그 결과 모든 필드 산화막(1) 중간부위 상단에 절연막 스페이서(4)의 라인이 형성된다.Subsequently, as shown in FIG. 4D, when the pattern of the polysilicon film 6 for forming spacers is removed by an etching process, lines of the insulating film spacers 4 are formed on the upper ends of all the field oxide films 1.
이어서, 제4e도와 같이 희생산화막(5)를 제거하고 터널 산화막(tunnel oxide, 7)을 기른 후 웨이퍼 전체구조 상부에 플로팅 게이트용 폴리실리콘막(2)을 증착한다.Subsequently, as shown in FIG. 4E, the sacrificial oxide film 5 is removed, the tunnel oxide film 7 is grown, and the polysilicon film 2 for floating gate is deposited on the entire wafer structure.
끝으로, 제4f도와 같이 평탄화용 물질(8)을 플로팅 게이트용 폴리실리콘막(2) 상부에 형성하고, 제4g도와 같이 절연막 스페이서(4) 상단의 플로팅 게이트용 폴리실리콘(2)이 제거되어 플로팅 게이트간의 단절이 이루어질 때까지 에치 백(Etch-Back) 한 다음에 평탄화용 물질(8)을 제거한다.Finally, the planarizing material 8 is formed on the floating gate polysilicon film 2 as shown in FIG. 4f, and the floating gate polysilicon 2 on the insulating film spacer 4 is removed as shown in FIG. 4g. Etch-back is performed until disconnection between floating gates is made, and then the planarization material 8 is removed.
이후의 컨트롤 게이트로 사용되는 폴리실리콘 형성공정, 그리고 컨트롤 게이트용 폴리실리콘 패턴(pattern)을 이용한 플로팅 게이트로 사용되는 폴리실리콘의 자기정렬 식각 공정, 소오스/드레인 형성공정, 콘택형성공정등은 기존의 방식과 동일하다.The polysilicon forming process used as a control gate and the self-aligned etching process, the source / drain forming process, and the contact forming process of polysilicon used as a floating gate using a polysilicon pattern for the control gate are conventional. Same way.
앞에 기술한 스페이서 형성공정은 다음과 같은 방식에 의해서도 가능하다. 필드 산화막 및 희생 산화막 형성후, 스페이서 형성용 폴리실리콘을 증착하고, 이어 질화막(Nitride)를 그 위에 증착하고, 스페이서 형성용 마스크(Mask)를 사용하여 포토(Photo)작업을 하고, 감광막으로 덮히지 않은 부위의 상기 질화막 및 스페이서 형성용 폴리실리콘을 제거한다. 이어 열적 산화(thermal oxidation) 방식에 의해 폴리실리콘의 측벽 부위에 산화막을 키운 후, 남은 질화막 및 스페이서 형성용 폴리실리콘을 제거하면 필드 산화막 정중간에 산화막으로 이루어진 길다란 산화막 스페이서 라인을 얻을 수 있다.The spacer forming process described above can also be performed in the following manner. After forming the field oxide film and the sacrificial oxide film, polysilicon for spacer formation is deposited, and then a nitride film is deposited thereon, a photo operation is performed using a spacer formation mask, and is covered with a photosensitive film. The nitride film and the spacer polysilicon for forming the spacer are removed. Subsequently, after the oxide film is grown on the sidewall of the polysilicon by thermal oxidation, the remaining nitride film and the polysilicon for forming the spacer are removed to obtain a long oxide spacer line formed of an oxide film in the middle of the field oxide film.
본 발명의 특징은 플로팅 게이트로 사용되는 폴리실리콘간의 공간을 포토리소그래피 작업에 의해 디파인하지 않고 절연막 스페이서를 이용한다는 점이다. 이 방법에 의해 폴리실리콘간의 공간을 최소형상크기(Minimum Feture Size)보다 적은 0.2-0.3㎛으로 대폭 축소가 가능하다. 즉 셀 크기의 Y축 길이를 약 30-40% 정도 축소가 가능하다. 만일 셀 크기의 축소보다는 프로그램/이레이즈(Program/Erase) 특성에 영향을 미치는 플로팅 게이트와 컨트롤 게이트의 커플링 율(coupling Ratio)을 증가시키고자 한다면 기존의 방식과 동일한 셀 크기에서 커플링 율을 50% 이상 향상시킬 수 있으므로 프로그램 또는 이레이즈 동작에 필요한 고전압 (4M 소자인 경우 대개 12V 정도)을 3V이상 낮출 수 있다.A feature of the present invention is that the insulating film spacer is used without defining the space between polysilicon used as the floating gate by photolithography. By this method, the space between polysilicon can be greatly reduced to 0.2-0.3㎛ which is smaller than the minimum feature size. That is, the Y-axis length of the cell size can be reduced by about 30-40%. If you want to increase the coupling ratio of the floating gate and the control gate that affect the Program / Erase characteristics rather than reducing the cell size, reduce the coupling ratio at the same cell size. It can be improved by more than 50%, reducing the high voltage required for program or erase operations (typically 12V for 4M devices) by 3V or more.
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