KR100277891B1 - Flash memory cell manufacturing method - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a flash memory cell suitable for improving the reliability of a device by facilitating patterning of a control gate by preventing an insulating layer from remaining on a side of the floating gate, and preventing loss of a device isolation film. Forming an isolation layer on the substrate to define an active region, forming a first polysilicon layer on the substrate via a tunneling oxide film, and forming a thicker first insulating layer on the upper surface thereof; Selectively etching the first insulating layer to expose the first polysilicon layer corresponding to an area, and then forming a second polysilicon layer on the entire surface of the substrate, and having a height lower than that of the first insulating layer. Etching the second polysilicon layer to remove the first insulating layer, and then removing both sides of the second polysilicon layer. Forming a poly sidewall, removing a first polysilicon layer on both sides of the poly sidewall to form floating gate lines formed of the first and second polysilicon layers and the poly sidewall, and including the floating gate lines. After forming a second insulating layer on the entire surface, forming a control gate on the second insulating layer, and etching the second insulating layer and the floating gate line using the control gate as a mask to form a floating gate. Characterized in that comprises a.

Description

Flash memory cell manufacturing method

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a flash memory cell.

Hereinafter, a flash memory cell manufacturing method according to the related art will be described with reference to the accompanying drawings.

1A-1B are layout diagrams of flash memory cells according to the prior art.

FIG. 1A illustrates the control gate before the formation of the control gate, and FIG. 1B illustrates the case where the control gate is patterned and formed to the floating gate using the control gate.

First, as shown in FIG. 1A, the device isolation layers 11 are formed in one direction at a predetermined interval, and the floating gate line overlaps a predetermined portion of the device isolation layer 11 between the adjacent device isolation layers 11. To form (12a).

After that, as shown in FIG. 1B, an insulating layer (not shown) having an ONO structure is formed on the entire surface including the floating gate lines 12a, and then a second polysilicon layer for control gate is formed on the insulating layer. After that, the control gates 13a are formed by patterning, and the floating gate lines 12a below the control gate 13a are etched to form floating gates 12b.

As described above, a method of manufacturing a conventional flash memory cell constructed as follows will be described with reference to FIGS. 2A to 2D and 3A to 3C.

2A to 2D are process cross-sectional views taken along line II ′ of FIGS. 1A to 1B, and FIGS. 3A to 3D are process cross-sectional views taken along line II-II ′ of FIGS. 1A to 1B.

For the sake of understanding, FIG. 2 showing the channel width direction (Y-direction) and FIG. 3 showing the channel length direction (X-direction) will be described at the same time.

First, FIGS. 2A to 2B are cross-sectional views taken along the line II ′ of FIG. 1A, and FIGS. 2C to 2D are cross-sectional views taken along the line II ′ of FIG. 1B.

3A to 3B are cross-sectional views taken along the line II-II 'of FIG. 1A, and FIGS. 3C to 3D are cross-sectional views taken along the line II-II' of FIG. 1B.

First, the semiconductor substrate 10 is defined as an active region and a field region, and then device isolation layers 11 are formed in the field region for device isolation.

Subsequently, after the tunneling oxide film 21 is formed on the substrate 10 of the active region, the first polysilicon layer 12 is formed on the substrate 10 including the device isolation layers 11. 2a)

Here, the first polysilicon layer 12 is used as a floating gate.

3A is a cross-sectional view along the X-direction, so that the device isolation film is not shown, and the tunneling oxide film 21 formed on the entire surface of the substrate 10 and the first polysilicon layer 12 formed on the tunneling oxide film 21 are not shown. This is shown.

Subsequently, the first polysilicon layer 12 is selectively removed to form floating gate lines 12a patterned in the same direction as the device isolation layer 11, as shown in FIG. 2B.

At this time, FIG. 3B maintains the state of FIG. 3A.

Thus far, the process sectional drawing along the lines II 'and II' of FIG. 1A is demonstrated.

Next, the process along the lines II 'and II-II' of FIG. 1B will be described.

That is, as shown in FIG. 2C, an insulating layer 22 having an oxide film-nitride-oxide film (ONO) structure is formed on the entire surface including the floating gate lines 12a, and a second layer is formed on the insulating layer 22. The polysilicon layer 13 is formed.

In this case, an insulating layer 22 having the ONO structure is formed on the first polysilicon layer 12, and a second polysilicon layer 13 is formed on the insulating layer 22.

Here, the second polysilicon layer 13 is used as a control gate.

Subsequently, as illustrated in FIG. 2D, the second polysilicon layer 13 is selectively etched to form the control gate 13a.

In this case, as shown in FIG. 3D, after the control gate 13a is formed, the floating gate line 12a is etched using the control gate 13a as a mask to form floating gates 12b.

Here, the control gate 13a is patterned to have a predetermined distance from each other, as shown in Figure 1b, but Figure 2d is a cross-sectional view along the Y direction is not shown that the control gate is separated. However, in FIG. 3D, the control gate 13a and the floating gate 12b which are separated from each other can be seen because they are cross sections along the X direction.

As shown in FIG. 3D, the floating gate 12b and the control gate 13a of the stacked structure are formed, and sidewall spacers 23 are formed on both sides thereof.

When the source / drain impurity diffusion regions 24 are formed by performing impurity ion implantation, the flash memory cell manufacturing process according to the prior art is completed.

As can be seen in this process, the floating gate 12b and the control gate 13a have a vertical structure by patterning the floating gate 12b at the same time when the control gate is formed, without patterning the floating gate before forming the control gate in advance. .

FIG. 4 is a cross-sectional view taken along the line III-III ′ of FIG. 1B. In the etching of the insulating layer 22 and the floating gate line 12a using the control gate as a mask, the device isolation film 11 is not etched. The insulating layer 22 remaining above is shown.

Such flash memory cells share a source impurity region between adjacent cells, and a positive voltage is applied to the common source impurity region for data erasing to release charges trapped in the floating gate.

Data erasing is mainly performed by applying a positive voltage to the gate and the drain so that high temperature hot electrons generated at the drain terminal of the channel are injected into the floating gate.

However, the conventional flash memory cell manufacturing method as described above has the following problems.

First, after forming an insulating layer having an ONO structure on the first polysilicon layer for the floating gate, and forming a second polysilicon layer for the control gate on the insulating layer, and then patterning patterning the control gate and the floating gate, When the insulating layer is etched using the control gate as a mask to pattern the floating gate, a phenomenon in which the insulating layer is not etched well and remains is generated.

When the insulating layer is left in this manner, the first polysilicon layer is not completely removed when the first polysilicon layer is etched, thereby shortening the adjacent floating gate.

The remaining insulating layer and thus not removed first polysilicon layer act as a source of particles, making it difficult to proceed with subsequent processes.

Second, when the excessive etching is performed to completely remove the remaining insulating layer, it is impossible to prevent the device isolation layer from being etched, and in the worst case, all the device isolation layers may be etched. In order to prevent this, the thickness of the device isolation layer can be made very large, but this causes a reduction in the degree of integration.

Third, when looking at the vertical profile of the floating gate, the upper edge of the floating gate becomes sharp, which increases the leakage current from the floating gate to the control gate, causing damage to the gate and deteriorating data retention characteristics.

Fourth, since the side surface of the floating gate has a vertical step, over-etching is induced during control gate etching, which causes a problem of damaging the gate oxide film and the substrate of the peripheral circuit device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is suitable for improving the reliability of devices by facilitating the patterning of the control gates by preventing the insulating layer from remaining on the side of the floating gates and preventing the loss of device isolation films. It is an object of the present invention to provide a method of manufacturing a flash memory cell.

1A to 1B are layout views of flash memory cells according to the prior art.

2A to 2D are cross-sectional views taken along the line II ′ of FIGS. 1A to 1B.

3A to 3D are cross-sectional views taken along line II-II 'of FIGS. 1A to 1B.

4 is a cross-sectional view taken along line III-III ′ of FIG. 1B.

5A through 5F are cross-sectional views illustrating a method of manufacturing a flash memory cell of the present invention.

Explanation of symbols for main parts of the drawings

50 semiconductor substrate 51 device isolation film

52: thermal oxide film 53: first polysilicon layer

54: first insulating layer 55: photoresist

56 Second Polysilicon Layer 57 Third Polysilicon Layer

57a: poly sidewall 58: second insulating layer

59: control gate

The flash memory cell manufacturing method of the present invention for achieving the above object is a process for defining an active region by forming a device isolation film on a semiconductor substrate, and forming a first polysilicon layer on the substrate via a tunneling oxide film, Forming a thicker first insulating layer on the upper surface thereof, and selectively etching the first insulating layer to expose the first polysilicon layer corresponding to the active region, and then second polysilicon on the entire surface of the substrate. Forming a layer, etching the second polysilicon layer so as to have a height lower than that of the first insulating layer, and removing the first insulating layer, and then removing the polysilicon layer on both sides of the second polysilicon layer. Forming a sidewall, and removing the first polysilicon layers on both sides of the polysidewall to form the floating gates comprising the first and second polysilicon layers and the polysidewalls. And forming a second insulating layer on the entire surface including the floating gate lines, forming a control gate on the second insulating layer, and using the control gate as a mask. And forming a floating gate by etching the floating gate line.

Hereinafter, a method of manufacturing a flash memory cell of the present invention will be described with reference to the accompanying drawings.

5A through 5F are cross-sectional views illustrating a method of manufacturing a flash memory cell of the present invention.

5A to 5F are taken along line II ′ of FIG. 1A.

First, as shown in FIG. 5A, the semiconductor substrate 50 is defined as a field region and an active region, and then an element isolation film 51 is formed in the field region.

In this case, the device isolation layers 51 are defined at regular intervals from each other.

As described above, after the device isolation layer 51 is selectively formed, the tunneling oxide layer 52 is formed in the active region, and the first polysilicon layer 53 having a thin thickness is formed on the entire surface of the semiconductor substrate 50.

Thereafter, the first insulating layer 54 is formed on the first polysilicon layer 53 relatively thicker than the first polysilicon layer 53.

In this case, the material of the first insulating layer 54 uses a high temperature low pressure dielectric (HLD).

After the photoresist 55 is coated on the first insulating layer 54, the photoresist 55 is patterned by an exposure and development process.

Subsequently, as illustrated in FIG. 5B, the first insulating layer 54 is selectively removed by an etching process using the patterned photoresist 55 as a mask.

That is, the portion from which the first insulating layer 54 is removed is a region corresponding to the active region in which the device isolation layer 51 is not formed and is etched to expose the surface of the first polysilicon layer 53.

Thereafter, after forming the second polysilicon layer 56 on the first polysilicon layer 53 including the selectively removed first insulating layer 54, the surface is planarized.

Subsequently, as shown in FIG. 5C, the second polysilicon layer 56 is etched until the surface of the first insulating layer 54 is exposed, and then the first insulating layer 54 is over-etched again. Leave only at the bottom in between.

That is, the second polysilicon layer 56 is excessively etched until the step with the device isolation layer 51 can be optimized.

Subsequently, as shown in FIG. 5D, only the first insulating layer 54 is selectively removed. In this case, the first insulating layer 54 is removed by wet etching.

As shown in FIG. 5E, a third polysilicon layer 57 is formed on the first polysilicon layer 53 including the second polysilicon layer 56.

Thereafter, the third polysilicon layer 57 is etched back to form poly sidewalls 57a on both sides of the second polysilicon layer 56, as shown in FIG. 5F.

The first polysilicon layer 53 is removed using the poly sidewall 57a and the second polysilicon layer 56 as a mask.

Accordingly, a floating gate line including the poly sidewall 57a and the first and second polysilicon layers 53 and 56 is formed, and both sides of the floating gate line are rounded by the poly sidewall 57a. Has

When the first polysilicon layer 53 is etched, the second polysilicon layer 56 is also etched to a predetermined depth.

After forming the floating gate line formed of the second polysilicon layer 56 through the above process, the second insulating layer 58 having the ONO structure is formed on the entire surface including the floating gate line.

Thereafter, a fourth polysilicon layer is formed on the second insulating layer 58 and then patterned to form a control gate 59.

The second insulating layer 58 and the floating gate line are etched by an etching process using the control gate 59 as a mask.

Therefore, since both sides of the floating gate line are rounded, the second insulating layer 58 deposited thereon is also rounded to completely remove the second insulating layer 58 during the etching process using the control gate 59 as a mask. You can do it.

As described above, the flash memory cell manufacturing method of the present invention has the following effects.

First, since the side of the floating gate is smooth and ONO is completely removed, there is no need to overetch because the ONO is completely removed, thereby preventing damage to the device isolation layer.

Second, there is no sharp edge on the top of the floating gate, reducing the leakage current from the floating gate to the control gate.

Third, since the height of the floating gate can be made almost constant with the height of the device isolation layer, the flatness of the cell region is improved after the floating gate process.

Therefore, there is no distortion of the pattern due to the step of the floating gate at the time of control gate fineness, and there is no need for excessive dry etching at the time of control gate dry etching, thereby preventing damage to the gate oxide film of the peripheral circuit element.

Fourth, since the growth thickness of the device isolation layer can be lowered, it is easy to cope with miniaturization of the field oxidation pattern, and the damage to the active region can be reduced as much as possible in the self-aligned source process.

Claims (3)

Forming an isolation layer on the semiconductor substrate to define an active region; Forming a first polysilicon layer on the substrate via a tunneling oxide film, and forming a thicker first insulating layer on the upper surface thereof; Selectively etching the first insulating layer to expose the first polysilicon layer corresponding to the active region, and then forming a second polysilicon layer on the entire surface of the substrate; Etching the second polysilicon layer to have a height lower than that of the first insulating layer; Removing the first insulating layer and forming poly sidewalls on both sides of the second polysilicon layer; Removing the first polysilicon layers on both sides of the poly sidewall to form floating gate lines formed of the first and second polysilicon layers and the poly sidewall; Forming a second insulating layer on the entire surface including the floating gate lines, and then forming a control gate on the second insulating layer; And etching the second insulating layer and the floating gate line using the control gate as a mask to form a floating gate. The process of claim 1, wherein the second polysilicon layer is etched to have a height lower than that of the first insulating layer. Planarizing the surface of the second polysilicon layer formed on the entire substrate; Etching the second polysilicon layer until the surface of the first insulating layer is exposed; And overetching the second polysilicon layer so as to have a lower height than the first insulating layer. The method of claim 1, wherein the second insulating layer is an insulating film having an ONO structure in which an oxide film-nitride film-oxide film is stacked.