KR20020091984A - Self align type flash memory device and method of forming the same - Google Patents

Abstract

PURPOSE: A self-aligned flash memory device and a manufacturing method thereof are provided to improve a coupling ratio and to prevent an over-etching of ONO dielectric film by forming a floating gate line using a self-alignment. CONSTITUTION: By sequentially forming and patterning a gate oxide layer(11) as a tunneling oxide layer, the first polysilicon layer(13) and an etch stopper on a substrate(10), a trench and a floating gate line are formed in and on the substrate(10), respectively. A trench isolation layer is formed by filling a silicon oxide into the trench. A recessed isolation layer(211) is formed by recess-etching the surface of the trench isolation layer. A polysilicon spacer(33) is formed at both sidewalls of the floating gate pattern. By selectively etching the etch stopper, the spacer(33) is protruded in the shape of horn. ONO dielectric film(35) is then formed on the resultant structure.

Description

Self-aligning flash memory device and its formation method {SELF ALIGN TYPE FLASH MEMORY DEVICE AND METHOD OF FORMING THE SAME}

The present invention relates to a flash memory device and a method of forming the same, and more particularly, to a gate structure and a method of forming the self-aligned flash device.

Flash memory is a nonvolatile memory device in which a gate of a cell memory is composed of a floating gate and a control gate, and the carrier is injected or withdrawn from the floating gate by an electrical method through voltage distribution to each electrode, and the state is read. All.

In order for the carrier to be efficiently injected or withdrawn into the floating gate, a coupling ratio indicating the ratio of this voltage to the floating gate when a high voltage is applied to the control gate is a problem. The coupling ratio depends on the capacitance between the control gate and the floating gate and the capacitance of the floating gate and the channel portion of the substrate. For example, in order to inject electrons efficiently, a large coupling ratio requires that a large portion of the voltage applied to the control gate be distributed to the floating gate, which requires a large capacitance of the capacitor including the control gate and the floating gate.

Figure 1 shows a typical gate electrode configuration of a memory transistor in a NAND flash memory device. The control gate 9, the floating gate 13, the dielectric film 5, the gate insulating film 11, the device isolation film 3, and the substrate 10 are displayed. According to this configuration, in order to increase the coupling ratio between the control gate 9 and the floating gate 13, it is important to increase the height H of the floating gate rather than increasing the channel length W.

2 to 5 show several steps of a self-aligned method of forming a gate structure in a conventional flash memory, which is shown in the data published by IEDM 1994, p61 by TOSHIBA.

Referring to FIG. 2, a turnnel oxide film 11 and a first polysilicon layer 13 are stacked on a silicon substrate 10, a silicon oxide film 7 to be used as a hard mask is stacked, and then trenched 19 through patterning. ) Is formed. Referring to a typical patterning process, a photoresist is laminated on a silicon oxide film, exposed and developed to form a photoresist pattern. The lower silicon oxide layer is etched using the photoresist pattern as an etching mask, and the photoresist pattern is removed. The primary polysilicon film, the turnnel oxide film, and the substrate are etched using the silicon oxide film pattern as an etching mask.

Referring to FIG. 3, the trench formed in FIG. 1 is filled with an oxide film 40 formed by a low deposition chemical vapor deposition (LPCVD) method.

3 and 4, a planarization etching process using CMP or the like is performed on the oxide film 40 filling the trench, and the silicon oxide film used as the hard mask and the oxide film 40 on the first polysilicon layer 13 ( 7) Remove. Again, a certain amount of etching is performed on the oxide film 40 filled in the trench so that a portion of the sidewall of the pattern made of the first polysilicon layer 13 is exposed. The ONO dielectric film 5 is conformally formed on the entire substrate 10.

Referring to FIG. 5, a second polysilicon layer for forming the control gate 9 is stacked on a substrate on which the dielectric film 5 is formed. The second polysilicon layer, the ONO dielectric layer 5, and the first polysilicon layer 13 are partially etched through the patterning operation.

However, according to the conventional method described above, the coupling ratio is sensitively related to the exposed sidewall of the pattern made of the first polysilicon layer, as shown in FIG. Accordingly, the planarization etch step using CMP or the like, in which the coupling ratio exposes a part of the sidewall of the pattern, and the etching step of partially recessing the oxide film filling the trench after the planarization etch are performed. As the trench pattern pitch decreases, these etching variations show a significant coupling ratio variation, which makes it difficult to improve cell uniformity, resulting in poor device operation or deterioration of characteristics.

According to US Pat. No. 6,074,917, another problem of the prior art is that it is difficult to etch the vertical portion of the ONO film, which is a dielectric film, in the process of patterning the gate line. If the vertical portion of the ONO film is not sufficiently etched through anisotropic etching, a portion of the first polysilicon layer below the vertical portion of the slightly inclined ONO film is not removed and thus a bridge between transistors of the series of flash memory strings connected in series is removed. bridge) can be formed.

In order to prevent such a problem, spacers may be formed on both sidewalls of the floating gate pattern or ONO overetch may be performed to easily etch the ONO dielectric layer by anisotropic etching. When the ONO layer is sufficiently etched, the device isolation layer of the trench is etched to expose the substrate under the first polysilicon layer pattern. When the substrate is exposed, a portion of the substrate is also etched in the step of selectively etching the first polysilicon layer pattern after the ONO to form the floating gate, thereby causing deterioration of device characteristics or defects.

In addition, since the area where the control gate and the floating gate overlap is small, the height of the floating gate needs to be increased to increase the coupling ratio. As described above, when the floating gate height H is increased, the vertical portion of the ONO film increases, and when the etching is performed again, It is a problem. ,

Disclosure of Invention The present invention aims at eliminating the structural problems of the conventional self-aligned flash memory device as described above and the problem of the formation method thereof, and to provide a flash memory device and a method for forming the same, which can increase the coupling ratio. do.

In addition, the present invention is reliable to prevent dielectric breakdown due to high voltage even when the dielectric film between the control gate and the floating gate and the turnneling insulating film between the floating gate and the substrate are formed below a certain value in order to increase the coupling ratio. An object of the present invention is to provide a flash memory device and a method of forming the same.

1 is a cross-sectional view showing a conventional gate electrode configuration of a memory transistor in a NAND flash memory device;

2 to 5 are cross-sectional views illustrating several steps of a method for fabricating a self-aligned flash memory to form a gate structure in a conventional flash memory;

6-9 are cross-sectional views illustrating several steps of a method of forming a gate structure in an embodiment of the present invention;

10-13 are cross-sectional views illustrating several steps of a method of forming a gate structure in another embodiment of the present invention;

14 to 16 are cross-sectional views showing several steps of a method of forming a gate structure in a third embodiment of the present invention;

17 to 18 are sectional views showing some steps of a method of forming a gate structure in a fourth embodiment of the present invention.

In order to achieve the above object, the flash memory device of the present invention is formed by alternately forming an active region and a device isolation region in a line form extending in one direction from a cell region, as in a conventional flash memory apparatus. In the cell region, a memory gate line is also formed to cross the active region. In the channel region where the active region and the memory gate line cross each other, a gate insulating layer, a floating gate, a dielectric layer, and a control gate are sequentially provided on the substrate. In particular, when the region in which the memory gate line is formed is viewed in a cross section cut in the forming direction of the memory gate line, the trench element isolation layer upper surface of the floating gate upper element isolation region of the active region has a step. Spacers are formed on the sidewalls forming the step, the spacer and the floating gate are covered with a dielectric film, and a control gate film is formed on the dielectric film.

When the floating gate upper surface is formed higher than the trench device isolation layer and the sidewall forming the step is the floating gate sidewall, spacers are formed on the device isolation layer on both sides of the device isolation region. That is, when viewed from above, both sides of the region where the spacer is formed and the device isolation region overlap.

The spacer may be formed to have a height defined by the stepped sidewall portion of the floating gate, or may be formed higher than the stepped sidewall portion and have a horn shape protruding on both sides of the floating gate.

The upper side of the trench isolation layer is formed higher than the upper surface of the floating gate so that the sidewalls forming the step are the trench isolation layer sidewalls, and the spacers are formed on the floating gate on both sides of the active region. In this case, a groove may be formed in a portion of the thickness of the floating gate, which is not covered by the spacer.

According to a first configuration of the method of the present invention for achieving the above object, forming a gate insulating film on the substrate, and sequentially laminating the first conductive layer and the etch stop layer, by selectively etching from the etch stop layer to a portion of the substrate through patterning Forming a floating gate line in a self-aligned manner while forming a trench in the substrate, filling an insulating layer in the trench formed in the substrate, and forming an isolation layer through planarization etching, and forming the isolation layer as a first conductive layer of the floating gate line Recessing a portion of the sidewall to be exposed, removing the etch stop layer pattern covering the floating gate line, conformally forming a second conductive layer over the floating gate line, and forming an spacer by anisotropically etching the entire surface, floating Forming a dielectric film covering the gate line and the spacer, Conductive film made up by a step of depositing a third conductive layer.

In this case, it is possible to form a thin etch stop layer that may have an etch selectivity with the etch stop layer and the polysilicon layer between the first conductive layer and the etch stop layer by an oxide film or the like. The etch stop layer is typically etched to form a predetermined pattern in the patterning process for trench formation and then removed together with the upper etch stop layer in a subsequent process.

Forming the spacer and removing the etch stop layer on the floating gate line may be performed in a reversed order.

According to a second aspect of the method of the present invention for achieving the above object, the step of forming a gate insulating film on the substrate, and sequentially laminating the first polysilicon layer and the etch stop layer, and selectively etching from the etch stop layer to a portion of the substrate through patterning Forming a floating gate line in a self-aligned manner while forming a trench in the substrate; forming an isolation layer through a planarization etching and filling an insulating layer in the trench formed on the substrate; and removing the etch stop layer pattern covering the floating gate line. Protruding the device isolation layer, forming a second polysilicon layer conformally on the substrate and etching anisotropically to form sidewall spacers in the spacer protruding device isolation layer, forming a dielectric layer covering the sidewall spacers, and forming a control gate over the dielectric layer. Laminating the film is provided.

Hereinafter, the present invention will be described in more detail with reference to the following examples.

Example 1

Referring to FIG. 6, a gate insulating film 11, that is, a turningen oxide film, is formed on a substrate 10 through substrate thermal oxidation. Subsequently, the first polysilicon layer 13, the etch stop layer 15 formed of the silicon oxide film, and the etch stop layer 17 formed of the silicon nitride film are sequentially stacked. These films are sequentially patterned through photolithography and etching. A trench 19 having a predetermined depth is formed in the substrate 10, and a line-shaped pattern formed of films on the substrate is formed in the active region. In one of these patterns, the first polysilicon layer 13 forms a floating gate line.

6 and 7, the silicon oxide film is filled in the substrate on which the trench 19 is formed by CVD. The silicon oxide layer deposited on the pattern of the etch stop layer 17 covering the first polysilicon layer 13 forming the floating gate line is removed through planar etching such as CMP. Thus, the device isolation film 21 is formed.

Referring to FIGS. 7 and 8, a recess etching for lowering the upper surface of the isolation layer 21 filling the trench is performed. The recess continues until the upper surface of the resulting isolation layer 211 is lower than the upper surface of the first polysilicon layer 13 forming the floating gate line. Next, the etch stop layer 17 pattern is etched. The second polysilicon layer is conformally stacked on the entire surface of the substrate, and the spacer 23 is formed by performing anisotropic front etching. At this time, the spacer is formed to be lower than the top of the etch stop layer 15 in which the top of the spacer 23 remains through overetching.

8 and 9, the etch stop layer 15 is selectively removed. The dielectric layer 25 is formed to cover an exposed portion of the first polysilicon layer 13 constituting the floating gate line and the spacers 23 formed on the upper sidewalls on both sides thereof. The dielectric film 25 is usually formed of an ONO film to increase the capacitance between the floating gate and the control gate. The third polysilicon layer 27 is stacked on the dielectric film 25.

Although not shown, the gate line is subsequently formed through patterning. After etching the third polysilicon layer 27 to form the control gate in the gate line, the dielectric layer 25 is etched. In this case, since the dielectric layer 25 is formed with a predetermined inclination, not vertical, by the spacers 23 formed on the sidewalls of the floating gate line, the dielectric layer 25 may be easily etched and the overetch time may be reduced. Even when the lower layer is etched by the over-etching, the periphery of the isolation layer 211 and the periphery of the spacer 23 do not extend in a straight line, but the periphery of the spacer 23 contacts the inner region of the isolation layer 211. Therefore, even when over-etching of the dielectric layer 25 is performed, damage is performed at the central portion of the device isolation layer 211, and the problem of exposing the substrate 10 by damaging the periphery of the device isolation layer 211 by overetching It is effectively avoided.

Example 2

Referring to FIG. 10, a gate insulating film 11, which is a tunneling oxide film, is formed on a substrate 10, and a first polysilicon layer 13 and an etch stop layer 17 are stacked thereon. The etch stop layer 17, the first polysilicon layer 13, and the substrate 10 are sequentially etched through the patterning operation to form a trench 19 having a predetermined depth in the substrate, and the upper portion of the substrate 10 in the active region. A pattern in the form of lines consisting of films is formed. In one of these patterns, a floating gate line is formed in the first polysilicon layer 13.

10 and 11, a silicon oxide film is filled in the substrate on which the trench 19 is formed by CVD. The silicon oxide layer deposited on the etch stop layer pattern 17 covering the floating gate line is removed through planar etching such as CMP. Thus, the device isolation film 21 is formed.

11 and 12, recess etching is performed to lower the upper surface of the isolation layer 21 filling the trench. The recess continues until the resulting top surface of the isolation layer 211 is lower than the top surface of the first polysilicon layer 13 of the floating gate line. Next, the second polysilicon layer is conformally stacked on the entire surface of the substrate, and anisotropic etching is performed on the entire surface of the substrate to form a floating gate pattern including the etch stop layer 17 pattern and the first polysilicon layer 13 on the stacked integrated pattern sidewalls. The spacer 33 is formed.

12 and 13, the etch stop layer pattern 17 is selectively etched by a phosphoric acid strip or the like. A portion of the spacer 33, which is in contact with the etch stop layer 17 pattern sidewall, protrudes like a horn on both sides of the first polysilicon layer 13 forming the floating gate line. The dielectric layer 35 is formed to cover the exposed portion of the first polysilicon layer 13 forming the spacer 33 and the floating gate line. The dielectric film 35 is usually formed of an ONO film. The third polysilicon layer 37 is stacked on the dielectric film 35.

In this embodiment, the same effects as those of Embodiment 1 can be obtained. In addition, since the spacer protrudes like a horn, the surface area of the floating gate electrode including the spacer is increased, and thus the capacitance between the control gate and the floating gate electrode is increased.

Example 3

Referring to FIG. 14, in the step of FIG. 11 of Embodiment 2, the etch stop layer 17 pattern is selectively removed. Therefore, the portion of the device isolation layer 21 protrudes relative to the active region.

Referring to FIG. 15, a conductive spacer 43 is formed on the sidewall of the device isolation layer 21 protrudingly stacked on the entire surface of the substrate 10 and anisotropically etching the second polysilicon layer. The lower end of the spacer 43 is formed to contact the upper surface of the first polysilicon layer 13 forming the floating gate line.

Referring to FIG. 16, an ONO dielectric film 45 is stacked on the entire surface of the substrate, and a third polysilicon layer 47 is stacked on the dielectric film 45.

This embodiment has the same advantages as the previous embodiment except that the spacers are formed on the sidewalls of the protruding device isolation layers. That is, in the etching step for forming the gate lines, the ONO film is formed to have a predetermined slope by the spacers so that the etching is performed. It is easy and the time for overetching is reduced. In addition, even when over-etching is performed, it is possible to avoid that the lower film is damaged to cause operational problems in the device.

Example 4

Referring to FIG. 17, the second polysilicon layer is stacked on the protruding device isolation layer 21 as in Example 3, and overetching is performed in the anisotropic etching of the entire surface. Therefore, the first polysilicon layer 131 having a groove according to overetching is formed in the intermediate region not covered by the spacer 43.

Referring to FIG. 18, a dielectric film 55 is formed over the entire substrate 10, and a third polysilicon layer 57 is formed on the dielectric film 55.

In this embodiment, a groove is formed in the middle portion of the upper surface of the floating gate line. In this case, an effect of increasing the area where the floating gate electrode and the control gate electrode are in contact with each other can be expected.

According to the present invention, the coupling ratio can be increased when the floating gate line is formed by forming a floating gate line in a self-aligned method in a flash memory device, and there is no burden of overetching during the etching of the ONO film, and the substrate is exposed. The probability of causing device malfunction can be lowered.

Claims (12)

The cell region includes a plurality of active regions in a line shape extending in one direction, device isolation regions alternately formed with the active regions between the plurality of active regions, and at least one memory gate line crossing the active regions upwards. A flash memory device comprising a gate insulating film, a floating gate, a dielectric film, and a control gate sequentially disposed over a substrate in a channel region where the active region and the memory gate line cross each other. The trench device isolation layer of the device isolation region has a step with the floating gate of the active region in a cross section of the region in which the memory gate line is formed in the direction in which the memory gate line is formed. And a conductive spacer connected to the floating gate, a dielectric layer covering the spacer and the floating gate, and a control gate layer covering the dielectric layer on sidewalls forming the step. The method of claim 1, A flash memory having a top surface of the floating gate formed higher than an upper surface of the trench device isolation layer so that a sidewall forming the step is a sidewall of the floating gate, and the spacer is formed on the device isolation layer on both sides of the device isolation region. Device. The method of claim 2, And the spacer is formed at a height defined by a stepped sidewall portion of the floating gate. The method of claim 2, And the spacer is formed higher than a stepped sidewall portion of the floating gate and is formed in a horn shape protruding from both sides of the floating gate. The method of claim 1, A top surface of the trench device isolation layer is formed higher than a top surface of the floating gate such that a sidewall forming the step is a sidewall of the trench device isolation layer, and the spacer is formed on the floating gate at both sides of the active region. Memory device. The method of claim 5, And a groove is formed in a portion of the floating gate, the thickness of which is not covered by the spacer. Sequentially laminating a gate insulating film, a first conductive layer, and an etch stop layer on the substrate; Forming a floating gate line formed of the first conductive layer while forming a trench by selectively etching a portion of the substrate from the etch stop layer to a thickness of the substrate through patterning; Filling an insulating layer in the trench and forming an isolation layer through planarization etching; Recessing the device isolation layer to expose a portion of the sidewall of the floating gate line; Removing an etch stop layer pattern covering the floating gate line; Forming a spacer by conformally forming a second conductive layer over the recessed device isolation layer and etching the entire surface anisotropically, Forming a dielectric film covering the floating gate line and the spacer; and And depositing a third conductive layer over the dielectric layer. The method of claim 7, wherein And the first conductive layer and the second conductive layer are formed of a polysilicon layer. The method of claim 7, wherein Forming an etch stop layer between the first conductive layer and the etch stop layer and having an etch selectivity therebetween; And removing the etch stop layer pattern formed by the self-aligning method in the removing of the etch stop layer pattern. The method of claim 7, wherein Forming the spacers And removing the etch stop layer pattern. Sequentially laminating a gate insulating film, a first conductive layer, and an etch stop layer on the substrate; Forming a trench by selectively etching a portion of the substrate thickness from the etch stop layer in a self-aligning manner through patterning to form a floating gate line formed of the first conductive layer; Filling an insulating layer in the trench and forming an isolation layer through planarization etching; Protruding the device isolation layer by removing the etch stop layer pattern covering the floating gate line; Forming a spacer by conformally forming a second conductive layer over the protruding device isolation layer and anisotropically etching the entire surface; Forming a dielectric film covering the spacer and the floating gate; And depositing a control gate layer on the dielectric layer. The method of claim 11, And forming a groove in an area not covered by the spacer of the floating gate by overetching the second conductive layer in the forming of the spacer.