CN105047667B - Simple and cost free multiple programmable structure - Google Patents
Simple and cost free multiple programmable structure Download PDFInfo
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- CN105047667B CN105047667B CN201510177999.1A CN201510177999A CN105047667B CN 105047667 B CN105047667 B CN 105047667B CN 201510177999 A CN201510177999 A CN 201510177999A CN 105047667 B CN105047667 B CN 105047667B
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Abstract
The present invention proposes a kind of simple and cost free multiple programmable structure for non-volatile memory cells.The storage unit includes having substrate, the HV well areas being arranged in the substrate and first and second well of isolation well.The storage unit further comprises adjacent to each other and the first transistor with selection gate being arranged on second well and the second transistor with floating grid.The transistor includes the first and second diffusion zone for being arranged adjacently to the side of the grid.Control gate is arranged on first well and is coupled to the floating grid.The control and floating grid include the identical grid layer for extending across first and second well.The control gate includes capacitance.
Description
Technical field
The present invention is on a kind of non-volatile memory cells and forming method thereof.
Background technology
In recent years, multiple programmable (multi-time programmable, MTP) memory is introduced into right at some
In needing customized application aspect to have beneficial use in numerical digit and Analogy.Application includes data encryption, benchmark trims for these
(reference trimming), manufacture mark (ID), safe ID and other a variety of applications.However, MTP memories are received
Enter generally also to bring the expense of some additional technical steps.Some existing methods of manufacture MTP memories often have slow access
The problem of time, smaller coupling ratio and/or big unit size.Some existing methods employ band-to-band-tunneling heat for computing of erasing
Electric hole (band-to-band tunneling hot hole, BBHH), but need height to engage with voltage and more Alternative step
Suddenly.Other existing methods need extra coupling to erase grid and coupled capacitor, thus need more many areas.
Therefore, it is necessary to multiple programmable structure that is a kind of simple and exempting from cost to manufacture with standard complimentary metal oxidation half
The non-volatile memory cells of conductor (CMOS) platform.
The content of the invention
Embodiment is generally about a kind of simple and exempt from the multiple programmable structure of cost.In one embodiment, it is non-volatile
MTP storage units include having the substrate of isolation well, high voltage (HV) well area being arranged in the isolation well and are arranged on
First and second well in the HV well areas in the substrate.The first transistor with selection gate and with floating grid
Second transistor position it is adjacent to each other and be arranged on second well.The transistor includes being arranged adjacently to the grid
First and second diffusion zone of the side of pole.Control gate is arranged on first well and is coupled to the floating grid.Should
Control gate and floating grid include the identical grid layer for extending across first and second well.The control gate includes electricity
Hold.
In a further embodiment, a kind of non-volatile MTP storage units are disclosed.The storage unit include have first and
The substrate of second isolation well.The second isolation well is arranged in the first isolation well.First and second well be arranged on this first every
From in well.The first transistor with selection gate and the second transistor position with floating grid are adjacent to each other and set
It is placed on second well.The transistor includes first and second diffusion zone for setting the side of the neighbouring grid.Control
Grid processed is arranged on first well and is coupled to the floating grid.The control gate and floating grid include extending across
The identical grid layer of first and second well.
In another further embodiment, a kind of method for forming non-volatile MTP storage units is disclosed.Base is provided
Plate and formed in the substrate first and second isolation well.First and second well is formed in the second isolation well.With choosing
Select the first transistor of grid and second transistor position with floating grid is adjacent to each other and be formed in second well
On.The transistor includes first and second diffusion zone for being arranged adjacently to the side of the grid.This first and second
Transistor is with series coupled and shares shared second diffusion zone.Control gate is formed on first well and is coupled to
The floating grid.The control and floating grid include the identical grid layer for extending across first and second well.The control gate
Including capacitance.
These and other advantages and features of presently disclosed embodiment, through with reference to being described below and institute's accompanying drawings
It will become obvious.More specifically, it should be noted that the advantages of various embodiments described herein and do not have to be mutually exclusive, and
And it may be present in various embodiments and displacement.
Brief description of the drawings
In the drawings, identical symbol typicallys represent identical part in each different viewpoint.Also, schema is simultaneously not required to
Will in proportion, emphasis is generally placed upon the principle for illustrating various embodiments on the contrary.In the following description, the invention has been described
Various embodiments and with reference to it is following wherein：
Fig. 1 shows the schematic diagram of storage unit；
Fig. 2 a show that the top view of the embodiment of storage unit, and Fig. 2 b-2c show the embodiment of the storage unit
Various profiles；
Fig. 3 a-3b show the schematic diagram of the embodiment of the array of storage unit；
Fig. 4 a-4c show the various operations of storage unit；
Fig. 5 shows the plan of the array of the embodiment of storage unit；And
Fig. 6 shows the processing procedure of the embodiment for shaping storage unit.
Embodiment
Embodiment generally relates to semiconductor device.Specifically, some embodiments are on storage device, such as non-volatile
Store (NVM) device.For example, this kind of storage device may be incorporated into independent storage, such as USB or other kinds of can
Take formula storage element, or IC, such as microcontroller or chip system (system on chips, SoCs).For example, the dress
Put or IC may be incorporated into or is used together with consumer electronics product or relevant other types device.
Fig. 1 shows the schematic diagram of the embodiment of storage unit 100.In one embodiment, which is non-volatile
(NV) multiple programmable (MTP) storage unit 100.As shown in figure the 1st, storage unit 100 includes the first transistor 110, second
Transistor 130 and control capacitance 150.In one embodiment, which makees as storage element and the control capacitance
For voltage coupling element.For example, which is metal-oxide semiconductor (MOS) transistor.Transistor
Including the grid between first and second diffusion zone.The diffusion zone of transistor is with the first polarity type dopant
Heavily doped region.The polarity type determines the type of transistor.For example, which can be that N-shaped represents N-shaped crystalline substance
Body pipe can be that p-type represents p-type transistor.
In one embodiment, transistor diffusion region may include diffusion extension region domain (not shown).For example, transistor
Diffusion zone may include that extend beyond the diffusion zone is lightly doped diffusion to be overlapped under a part for the transistor gate
Region.Diffusion extension region domain may include lightly doped drain (LDD) elongated area and ring-type (halo) region.For example, should
LDD elongated areas are phase contra-doping with the annular section.For example, the annular section include the second polarity type dopant with
For first kind transistor, and the LDD elongated areas include the first polarity type dopant with for first kind transistor.
The other configurations in diffusion extension region domain are also likely to be useful.For example, only with LDD elongated areas without annular section
Diffusion extension region domain is also likely to be useful.
Grid includes gate electrode and gate-dielectric.The second transistor as access transistor of the first transistor 110
130 are used as storage transistor.For example, which includes the first access access expansion of diffusion zone 112, second
Dissipate region 114 and access gate 116；Storage transistor 130 includes the first storage diffusion zone 132, second and stores diffusion region
Domain 134 and storage grid 136.Access gate 116 can be referred to as can be referred to as floating gate for selection gate and storage grid 136
Pole.
In one embodiment, which is mos capacitance.For example, which includes having control
Gate electrode processed and the dielectric control gate 156 of control gate.Control gate 156 forms control capacitance 150.The control capacitance
Including first and second capacitor plate separated by dielectric layer.For example, the control grid electrode is as first (or the grid
Capacitance) pole plate and control well 209 (will afterwards describe) to be used as second (or well) capacitor plate.For example, it is arranged on this
Dielectric layer on second capacitor plate separates first and second capacitor plate.Capacitance contact bolt 152 (or well tap
Well tap) (will afterwards describe) be arranged on the substrate and coupled to active capacitor (or well pickup well pickup)
Region is biased to the control well with providing.In one embodiment, which is arranged adjacently to the control capacitance.Citing
For, which is arranged adjacently to the side of the control gate.It is active that capacitance contact bolt offer is conductively connected to this
Capacitor regions.In one embodiment, which is coupled to the storage grid.Have for example, the grid is by common gate conductor
Formed.The control Capacitor apart stores grid 136, becomes floating grid.
The access and storage transistor 110 and 130 are with series coupled.For example, this second access diffusion zone and
Second storage diffusion zone 114 and 134 forms the shared diffusion zone of the transistor.On the control gate 156 and storage grid
Pole 136, they are coupling altogether.For example, there is provided be total to gate electrode and gate-dielectric to form the storage grid and control
Grid.The other configurations of the storage and control gate are also likely to be useful.By common coupling control and storage 156 He of grid
136, generate floating storage grid.
This first or access transistor 110 first access diffusion zone 112 be coupled to the storage device source electrode line
(SL).This second or storage transistor 130 first storage diffusion zone 132 be coupled to the storage device bit line (BL).Deposit
The selection gate of storage unit 100, or the access gate 116 of the first transistor 110, coupled to the selection gate of the storage device
Line (SGL).The capacitance contact bolt 152 of the control capacitance couples the control gate polar curve (CGL) of the storage device.In an embodiment
In, which is set along a first direction, such as word-line direction, and the BL is set along second direction, such as bit line direction.Lift
For example, which is orthogonal.On the CGL, it sets along the word-line direction and the SL and sets edge
The bit line direction.The other configurations of BL, CGL, SGL and SL are also likely to be useful.For example, storage list of array
Member is also coupled to the shared SL (CSL) set along word-line direction.
Fig. 2 a show that the top view of the various embodiments of storage unit, and Fig. 2 b show the storage unit of an embodiment
Profile, and Fig. 2 c show the profile of another embodiment of storage unit.For example, which is along the storage list
A-A ', B-B ' and the C-C ' of member.The storage device includes storage unit 200.The storage unit is similar to described in Fig. 1
's.General element may not be described or be described in detail.Shown storage unit 200 is NVM cell.For example, should
Storage unit is non-volatile MTP storage units.
The device may include the doped region with different concentration of dopant.For example, which may include heavy doping
(x+), medium-doped (x) and (x is lightly doped-) region, the polarity type that it can be p-type or n-type dopant that wherein x, which is,.It is lightly doped
Region may have about 1E11-1E12cm-2Concentration of dopant, medium-doped region may have about 1E12-1E13cm-2's
Concentration of dopant, and heavily doped region may have about 1E13-1E14cm-2Concentration of dopant.To different types of doping
It is also likely to be useful that region, which provides other concentration of dopant,.For example, which can be varied from, root
According to technology node.P-type dopant may include boron (B), fluorine (F), aluminium (Al), indium (In) or combinations thereof, and n-type dopant can
Including phosphorus (P), arsenic (As), antimony (Sb) or combinations thereof.
The device is arranged on substrate 205.The substrate is semiconductor substrate, such as silicon substrate.Other kinds of semiconductor
Substrate is also likely to be useful.In one embodiment, substrate 205 is that substrate is lightly doped.In one embodiment, the substrate is with second
The dopant of polarity type is lightly doped.For example, which is lightly doped p-type (p-) substrate.It is other kinds of to provide doping
The substrate of dopant or undoped substrate are also likely to be useful.
Unit area 284 is provided in the substrate.For example, which is the cellular zone for setting the storage unit
Domain.Although shown as a unit area, which may include multiple there is interconnection to form the unit area of storage array
Storage unit.In addition, the substrate may include other kinds of device region, according to the type of device or IC.For example, the dress
Put the device region that may include to be used for high voltage (HV), medium or middle voltage (MV) and/or low-voltage (LV) device.
The unit area includes first and second well 209 and 207.First well as the control well for control gate and
Second well is as crystal pipe well.For example, the crystal pipe well be used as be used to accessing (or selection) and storage transistor 110 and
130 well.In one embodiment, which includes control capacitance 150.The control capacitance can be mos capacitance.Other types
Control gate be also likely to be useful.
As shown in the figure, well setting is adjacent each other.First well 209 accommodates the control capacitance and the second well 207 accommodates this and deposits
Take and storage transistor.First (or control) well includes crystal including capacity type dopant and second (or transistor) well
Pipe well type dopants.In one embodiment, this controls well as well is lightly doped.For example, the concentration of dopant of the control well
It may be about 1E11-1E12cm-2.On the crystal pipe well, it can be mild to moderate impure well.For example, the crystal pipe well
Concentration of dopant may be about 1E12-1E13cm-2.The concentration of dopant of other controls and/or crystal pipe well is also likely to be to have
.First and second well can be as the device well for being respectively used to HV and MV devices.For example, which is fully to mix
It is miscellaneous to form HV device wells, and second well is fully doping to form MV device wells.
First well 209 includes the depth D on the surface of the substrateW1And second depth that includes from the surface of the substrate of well 207
Spend DW2.Although schema illustrates that first and second well has the about the same depth dimensions from the surface of the substrate, it should be understood that
Different depth dimensionses is may also comprise to first and second well.For example, the D of first wellW1It may differ from second well
DW2。
The polarity type of the control well dopant may depend on the polarity type of the control gate.In one embodiment, should
The polarity type of well is controlled to depend on the polarity type of the control capacitance.Control capacitance example in, this control well be and this
The identical polarity of capacity type.For example, it is p-type with for p-type mos capacitance that this, which controls well dopant, or N-shaped is with for n
Type mos capacitance.On the crystal pipe well dopant, it is the polarity type opposite with the transistor.In one embodiment, the crystalline substance
Body pipe well dopant is the dopant of the second polarity type with for the first kind crystal with the first polarity type dopant
Pipe.For example, which is p-type with for n-type transistor.In one embodiment, the pole of the crystal pipe well
Property type is opposite with the polarity type of the control well.For example, there is provided the crystal pipe well of the second polarity type gives the first polarity
The control well of type.First polarity type can be N-shaped and second polarity type can be p-type.Transistor and control well
Other configurations are also likely to be useful.For example, which can be p-type and second polarity type can be n
Type.
Isolation well 208 may be provided in the substrate, as shown in Fig. 2 b-2c.The isolation well can be that deep isolation well is arranged at this
Under first and second well.In one embodiment, which is the shared isolation well of storage chip.For example, the isolation
Multiple storage arrays of the well around storage chip.The isolation well includes isolation well dopant.In one embodiment, which is
It is lightly doped with isolating well dopant.For example, the polarity type of the isolation well dopant and the type of substrate polarity type phase
Instead.In one embodiment, which is the first polarity type dopant with for the second polarity type substrate.Citing
For, there is provided N-shaped isolation well gives p-type substrate.The other configurations for isolating well and substrate are also likely to be useful.Isolate well 208
Isolating with the substrate first and second well to improve the noise immunity (immunity) of the storage device.Isolate well
208 have the depth D from the surface of the substrateN.Isolation well 208 can be described as the first isolation well.
In certain embodiments, HV well areas 210 may be provided in the isolation well 208 in the substrate.In one embodiment,
The HV well areas are around first and second well.For example, the HV regions by first and second well 209 and 207 with isolating
Well 208 separates.In one embodiment, which is the shared HV well areas of storage array.For example, the HV well areas
Around multiple storage units of storage array.The HV well areas include HV well dopants.In one embodiment, HV well areas 210
It is being lightly doped with HV well dopants.For example, the polarity type of the HV well dopants isolates the polarity of well dopant with this
Type is opposite.In one embodiment, which is mixed for the second polarity type with the isolation well for the first polarity type
Debris.For example, there is provided p-type HV well areas isolate well to N-shaped.HV well areas and the other configurations of isolation well are also likely to be
Useful.In one embodiment, the HV well areas and control well are the dopant doping with opposite polarity type.Citing comes
Say, there is provided p-type HV well areas isolate to N-shaped and control well 208 and 209.During device or programming operation, which uses
To improve the isolation of the control well.The offer of HV well areas causes selectively program and lower unit size layout.The HV
Well area has the depth D from the surface of the substrateP.The HV well areas can be referred to as the second isolation well.
In one embodiment, DPCompare DNIt is shallow and compare DWIt is deep.In general, DWLess than DP, DPLess than DN(DW<DP<DN).Citing
For, DNMay be about 1.8 μm and DPIt may be about 0.8-1.2 μm.For DW、DNAnd DPOther appropriate depth sizes also may be used
Can be useful.
Cell isolation region 280, as shown in the figure, separating first and second well and other device regions.Implement one
In example, cell isolation region 280 is fully overlapped in first and second well 209 and 207 to isolate the different well.For example,
The cell isolation region is overlapped in a part for first and second well.In one embodiment, the bottom of first and second well
Extend under the cell isolation region.For example, first and second well extend to and repeatedly in the cell isolation region it
Under.The other configurations of first and second well are also likely to be useful.Set between first and second well carry his type every
It is also likely to be useful from region.Active region of the cell isolation region deviding in first and second well.For example,
Active transistor regions 222 of the cell isolation region deviding in the second well 207, and the active electrical in the first well 209
Hold region 220.For example, which is shallow-trench isolation (STI) region.The other types of area of isolation may also
It is useful.
Cell isolation region has depth DI.For example, which has the depth from the substrate surface
DI.In one embodiment, which has the depth more shallower than first and second well.For example, DIThan this
One and second well and the HV well areas the less (D of depthI<DW<DP).For example, DIIt may be about 0.5 μm.For DIIts
His suitable depth dimensions is also likely to be useful.
In other embodiments, primary layer (native layer) 290 is overlapped under the cell isolation region, and separation should
First and second well 209 and 207, as shown in Figure 2 c.Primary layer 290 is set between the bottom of first and second well.Lift
For example, which separates first and second well.In one embodiment, design and manufacture technology is to include maintaining substrate 205
Low doping concentration substrate regions to form primary layer 290.For example, which is substantially doped layer and conduct
To maintain the original of the substrate that part is lightly doped, it may be changed into heavily doped region in logic (or main) operation stage on barrier layer.
The other types of primary layer are also likely to be useful.The primary layer extends to about D from the bottom in the cell isolation regionWDepth
Degree.For example, which is not overlapped under the cell isolation region.On critical voltage (Vt) typical case very
It is low, for example, about 0.2V and the primary layer are to be lightly doped with very similar or characteristic close to the initial substrate
Layer.Therefore, the presence of the primary layer improves the isolation between first and second well and increases breakdown voltage.
Access and storage transistor be arranged on this second or crystal pipe well in the active transistor regions on.Transistor
Including the grid being arranged between first and second diffusion zone.For example, which includes and the transistor
The dopant of type dopants identical polar type.For example, p-type transistor has the diffusion zone of p-type dopant.Lift
For example, which is heavily doped region.The grid set on the substrate and the diffusion zone is arranged on the substrate
In active region.Grid includes gate electrode 258 and gate-dielectric 257.For example, gate electrode 258 can be polysilicon gate
Electrode and gate-dielectric 257 can be silica gate-dielectric.The other types of gate electrode and dielectric substance also may be used
Can be useful.
Dielectric spacer (not shown) may be provided on the gate lateral wall of the transistor.The distance piece can be used to promote shape
Into transistor diffusion region.For example, distance piece is formed after being formed in diffusion extension region domain.For example, can by
Spacer layers are formed on the substrate and by its anisotropic etching to remove horizontal component, left on the side wall of the grid
The mode of distance piece forms distance piece.After the distance piece is formed, implantation is performed to form the transistor diffusion region.
As discussed, access transistor 110 is included in active transistor regions 222 with transistor types dopant weight
First and second access diffusion zone 212 and 214 of doping and access gate 216 on the substrate.In one embodiment,
Transistor diffusion region may include to extend beyond under the diffusion zone with the expansion under a part for the overlapping what transistor gate
Dissipate elongated area (not shown).The access gate includes access gate electrode 258 and is covered on access gate dielectric 257.Should
Access gate can be referred to as selection gate.Storage transistor 130 is included in the transistor types dopant heavy doping in the substrate
First and second storage diffusion zone 232 and 234 and storage grid 236 on the substrate.The storage grid includes storage
Gate electrode 258 is deposited to be covered on storage gate-dielectric 257.The storage grid can be referred to as floating grid.Access and storage
Transistor 110 and 130 is series coupled.In one embodiment, the second access diffusion zone 214 and second stores diffusion zone
234 form the shared diffusion zone of the transistor.May also for the other configurations being connected in series of the access and storage grid
It is useful.
Control capacitance 150 is arranged on first well.The control capacitance includes setting on the substrate in the active capacitor
Control gate 256 on region.The control gate is included in the control grid electrode 258 on control gate dielectric 257.Lift
For example, control grid electrode 258 can be polysilicon control grid electrode, and control gate dielectric 257 can be that silica controls
Gate-dielectric.The other types of gate electrode or dielectric substance are also likely to be useful.In one embodiment, control gate electricity
Pole with control or capacity type dopant adulterate.For example, which is with the polarity class identical with the control well
The heavy doping of type dopant.Capacitance contact bolt 252 is arranged on the control well and is adjacent to the side of the control gate.Lift
For example, which removes from the side of the control gate.In one embodiment, the capacitance contact bolt be coupled between
Active capacitor region (or well picking region) between the unit area of isolation and the side of the control gate.For example,
The capacitance contact bolt can be conductive contact bolt, such as tungsten contact bolt.The other types of conductive contact bolt are also likely to be useful.Electricity
Hold contact bolt 252 as well tap with the well picking region for the capacitance.Although shown as a capacitance contact bolt, Ying Li
Solve this and may have more than a capacitance contact bolt and expose top end surface coupled to the active capacitor region or the control well.Control
Well 209 processed as this second or well capacitor plate and the gate electrode 258 as this first or gate capacitance pole plate.In an embodiment
In, adulterate the capacitance gate electrode before the capacitance contact bolt is formed.For example, setting gate electrode layer on the substrate is
Pre-doping has control dopant and patterns to shape the capacitance gate electrode.
In one embodiment, the control gate and storage gate electrode 258 are coupling altogether.In one embodiment, control gate
Pole 256 and storage grid 236 are formed with identical grid layer.For example, pattern the grid layer be produce the control with
And storage grid.In such example, control gate 256 and storage grid 236 are formed with identical material.Citing comes
Say, the control grid electrode and dielectric layer are formed with the material identical with the storage gate electrode and dielectric layer.Citing comes
Say, which is adulterated with capacity type dopant.Other type dopants of offer gate electrode are also likely to be useful.It is real one
Apply in example, the access, storage and control gate are formed by identical grid layer.The other configurations of the grid are also likely to be useful
's.For example, which can be formed by different grid layers.
Metal silicide connection (not shown) may be provided on the join domain of the storage unit.For example, the metal
Silicide connection can be that nickel or nickel based metal silicide connect.Other of metal silicide connection are adapted to type, including cobalt or cobalt
Base Metal silicide connects, it is also possible to useful.In one embodiment, metal silicide connection may be provided in transistor expansion
Dissipate in region, active capacitor region and the access gate.Silicide stop block 261 is arranged on the storage and control gate.
For example, which is dielectric substance, such as silica or silicon nitride.The other types of silicide stop block may also
It is useful.There is provided silicide stop block prevented on the storage and control gate silicide connect be formed in the grid it
On.Which improve data holding.
First access diffusion zone 212 is coupled to the SL of the storage device.First storage diffusion zone 232 is deposited coupled to this
The BL of storage device.Access gate 216 is coupled to the SGL of the storage device.Capacitance contact bolt 252 is coupled to the storage device
CGL.In certain embodiments, control gate 256 implements capacitance 150 in order to control.In certain embodiments, the SGL set along
First direction, such as wordline (WL) direction, and the bit line is set along second direction, such as the bit line perpendicular to the WL directions
(BL) direction.The CGL can set along the word-line direction and the SL and set along the bit line direction.BL, CGL, SGL and SL
Other configurations be also likely to be useful.For example, the storage unit of array can be coupled to along what word-line direction was set and be total to
With SL (CSL).
The various conducting wires of the storage unit may be disposed in the metal stratum of the device.The conducting wire for being arranged at equidirectional can
There is provided in identical metal stratum.For example, the conducting wire along the BL directions is set to may be provided at MX, and set along this
The conducting wire in WL directions may be provided in the M of the deviceX+1.The other configurations of conducting wire and metal stratum are also likely to be useful.
Described storage unit has improve or programming more efficiently, because adding capacitive coupling ratio.Citing
For, the layout of the control gate (CG) and floating grid (FG) may be designed as having an area than to produce the required electricity
Hold coupling ratio.In certain embodiments, CG:The area ratio of FG may be about 0.8:0.2.For example, the width of the floating grid
(W) x long (L) may be about 0.4x 0.28, and the W x L of the control gate may be about 1.6x 0.84.Other CG are provided:FG
Area ratio be also likely to be useful.The control gate is given by large area is provided, moderate bias can be produced on the capacitance well.
This bias is transferred to the floating grid and is programmed for the high efficiency of the storage unit.Reduce the high voltage needed for the capacitance well
Allow to form less charge pump.This further reduces the size of the device.
In certain embodiments, connect by the multiple contacts for providing the well capacitor plate coupled to the capacitance, such as capacitance
Bolt is touched, may achieve the low-resistance pressure drop of drop and so as to improve technique stability.For example, one or more contact bolts can
The control gate is arranged adjacently to electrical couplings well capacitor plate to CGL.The number of the contact bolt may depend on the control
The size and spacing of the girth of grid, the size in the active capacitor region and the contact.More the contact of big figure will reduce more
More resistance.
Fig. 3 a-3b show the schematic diagram of the embodiment of the array 300 of storage unit.For example, the part of array is shown
For with four storage units 100, such as those descriptions are in Fig. 1 and Fig. 2 a-2c.General element may not be described or
It is described in detail.The array of storage unit can be formed with first and second well 209 and 207 being arranged in HV well areas 210
Substrate on.In certain embodiments, which enclosed by the common isolation well 208 of the storage array of storage chip
Around.In one embodiment, which extends across multiple row of the interconnection storage unit of array.For example, should
First and second well forms first and second shared well of storage array.The other configurations of first and second well are also likely to be useful
's.
As shown in Figure 3a, the storage unit is interconnected to form connected by BL (BL0 and BL1) and SL (SL0 and SL1) two
Row, and two rows by SGL (SGL0 and SGL1) and CGL (CGL0 and CGL1) storage unit connected.In one embodiment,
The SL (SL0 and SL1) of each row of storage unit is coupled to separated source terminal.For example, SL0 and SL1 is coupled to first
And second source terminal and BL0 and BL1 be coupled to first and second terminal.The separation of coupled memory cell arrange to it is separated (or
It is dedicated) source terminal formation one AND type arrays configuration.For example, it is illustrated that AND type arrays configuration have couple respectively
Access and storage transistor to each row of separated SL and BL terminals.It is more reliable with AND type arrays configuration provides
Storage unit operate in array.
In other examples, the SL of each row of storage unit is coupled to shared source terminal.As shown in Figure 3b, deposit
The SL of each row of storage unit can use source terminal (CSL) coupled to the common of WL directions is arranged at.Couple the separation of storage element
Row to shared source terminal forms NOR type array configuration.Illustrated NOR type array configuration have coupled to CSL in
Access transistor in separation row, and the storage transistor in separation arranges is coupled to separation BL (or drain electrode) terminal.With NOR
The arbitrary access of type arrays configuration provides is to the storage unit and reduces the occupied space of array.The other configurations of array
It is probably useful.
Although shown as the 2x2 parts of array, it should be noted that the array may include numerous rows and columns.For example, should
Storage array can form memory block.
In an embodiment, the storage unit of Fig. 1 and Fig. 2 a-2c is to including first kind transistor and the first kind
Type capacitance.For example, the access and storage transistor are the polarity type identical with the control capacitance.In an embodiment,
The first kind is N-shaped.For example, which is to n-type transistor and N-shaped capacitance.In such example
In son, transistor (or second) well 207 and capacitance (or first) well 209 include the dopant of opposite polarity type.The crystalline substance
Body pipe well includes the second polarity type or p-type dopant, and the control well includes the first polarity type or n-type dopant.The crystalline substance
Body pipe diffusion zone is N-shaped.More specifically, which is adulterated with capacity type dopant.For example, the gate electrode
Adulterated with the first polarity type or n-type dopant.Other gate configurations are also likely to be useful.
For the storage unit with first kind transistor and capacitance, various operator schemes are described in Fig. 4 a-4c.
For example, which is N-shaped.Table 1 below shows the various various terminals for being biased in storage unit with order to program, smear
Remove and read mode：
Table 1
Numerical value in table 1 is using Fowler-Nordheim (FN) tunnellings in the computing that programs and erase.For example, should
Numerical value is for the operation voltage V equal to about 5Vdd.Other suitable voltage values are also likely to be useful.
The storage unit is operable in Fowler-Nordheim (FN) tunneling program pattern 400a, as shown in fig. 4 a.In order to
Realize that FN tunneling programs operate, there is provided various selections (sel) signal for such programming operation is single in selected storage
The various terminals of member.In the programming mode, electron carrier 465 is tunneled through to the floating grid (FG) from the crystal pipe well.
Other suitable types of programming mode, such as channel hot electron (CHE) injection programming pattern, it is also possible to useful.Citing comes
Say, in the CHE programming modes, electron carrier is injected into the FG in the drain side from the transistor channels.
The storage unit is operable in FN tunnellings and erases pattern 400b, as shown in Figure 4 b.In order to realize that FN tunnellings are erased mould
Formula, there is provided the various sel signals for such operation of erasing are in the various terminals of selected storage unit.In the mould of erasing
In formula, electron carrier 465 is moved to the crystal pipe well from the FG, from the drain side of the grid.The pattern of erasing can be realized and deposited
Store up the operation of erasing of block or row.
On read operation 400c, it is shown in Fig. 4 c.Various selections (sel) signal for read operation is provided in institute
The various terminals of the storage unit of selection, to influence the read operation.
Fig. 5 shows the plan of the embodiment of the array 500 of the storage unit of storage device.The storage unit is similar to
Described in Fig. 1 and Fig. 2 a-2c.General element may not be described or be described in detail.Shown storage unit 200 is non-easy
The property lost storage unit.For example, which is non-volatile MTP storage units.As shown in the figure, the storage unit includes
Access and storage transistor 110 and 130 are with series coupled, and control gate 256 is floating to produce coupled to storage grid 236 altogether
Moving grid pole.The transistor is arranged on active transistor regions and the control gate is arranged on active capacitor region.Storage
Cellular array may be formed on the substrate with isolation well, HV well areas and first and second well.
In one embodiment, array 500 includes multiple storage units in opposite directions configuration.For example,
The storage unit is mutual mirror image on first and second side and the storage unit is mutual on top side and bottom side
Mirror image.In other examples, along Y or word-line direction, which can dispose according to him (such as without mirror
Picture).In one embodiment, primary layer 290 is arranged in the substrate between the active transistor and capacitor regions.Citing comes
Say, which adds breakdown voltage and improve the insulation between the transistor and control well.
Multiple storage units can be interconnected by various lines to form array.For example, storage unit can by SGL and
CGL and interconnect row to form storage unit and by BL and SL to form the row of storage unit.By the suitable signal of application
To a storage unit various lines or terminal may achieve access the storage unit.By FN tunnellings with electric from the crystal pipe well tunnelling
It is the position programming for reaching the storage unit that son, which enters the floating grid,.By from the FG tunnelling FN electronics to the crystal pipe well, from
The drain side of the grid, erases up to blocking or row.
Fig. 6 shows the technique 600 of the embodiment for forming storage unit as described herein.In details of the words, technique 600 is said
The semiconductor fabrication process technique of bright example is to form storage unit of the description in Fig. 1 and Fig. 2 a-2c.General element can
It can not be described or be described in detail.
602, forming the technique of the device includes providing the substrate for having one or more unit or device regions.Lift
For example, which is to be lightly doped with the second polarity type dopant, such as p-type dopant.There is provided with other kinds of doping
The substrate or undoped substrate of thing doping are also likely to be useful.By device area of isolation, such as shallow-trench isolation (STI) area
Domain, by a device region and other device zone isolations.In one embodiment, which defines active region, example
Such as active transistor and capacitor regions.For example, device area of isolation isolates the transistor and capacitor regions and its
His device region, such as HV, MV and/or LV device.In one embodiment, the device area of isolation is formed including forming groove to exist
In the substrate and the insulating layer of the groove is filled in formation.
In one embodiment, formed isolation well in the substrate before, the technological process it is sustainable along arrow A with shape
Into primary layer.In the alternative embodiment, the technological process it is sustainable along arrow B to form the isolation well in the substrate and
Do not form primary layer.
604, primary layer is formed between the transistor and capacitor regions.The primary layer may be provided at the substrate
In, under the device area of isolation, as shown in Figure 2 c.The primary layer is the essence doping introduced during the manufacture processing procedure
Layer.In one embodiment, which is shaped as the primary layer on barrier layer to maintain the original of the substrate gently to mix
Hetero moiety, it may form in logic (or main) operation stage and be changed into heavily doped region.For example, the design and manufacture technology into
Including maintain substrate 205 the low doping concentration substrate regions to form the primary layer 290.To formed the primary layer its
His suitable technology is also likely to be useful.The primary layer includes being deeper than the depth of the device area of isolation.For example, device
Area of isolation is arranged on the primary layer.In an embodiment, the primary layer for lightly-doped layer be overlapped in separation this first and
Under the device area of isolation of second well.For example, which may be about 0.39 μm wide.Other suitable rulers of primary layer
Very little is also likely to be useful.Primary layer separation extends in the bottom of the well under the device area of isolation.The depth of the primary layer
Degree may be about the depth of first and/or second well.In example existing for primary layer, which adds breakdown voltage
And improve insulation between first and second well.
606, isolation well is formed in the substrate.In one embodiment, which is the storage around storage chip
The shared isolation well of array.For example, which isolates well for the deep of next depth of implantation to the device area of isolation.
The other methods for forming the isolation well are also likely to be useful.In one embodiment, form the first polarity type and isolate well with right
In the second polarity type substrate.For example, which is to be lightly doped with n-type dopant with for p-type substrate.Others are mixed
Dopant concentrations and type dopant are also likely to be useful.
It is formed in 608, HV well areas in the isolation well, in the substrate.For example, the isolation well is around the HV wells
Region.In one embodiment, which is the common HV well areas around the array of the storage unit of interconnection.Citing comes
Say, which is implantation to being relatively shallower than the isolation well but be relatively deeper than the depth of the device area of isolation.For forming the HV
The other technologies of well are also likely to be useful.In one embodiment, the HV well areas of the second polarity type are formed with for first
The isolation well of polarity type.For example, which is lightly doped with p-type dopant to isolate well for N-shaped.Other doping
Thing concentration is also likely to be useful.HV well areas and the other configurations for isolating well are also likely to be useful.
610, first and second well is formed in the HV well areas.For example, the HV well areas around this first and
Second well.First well is formed in the active capacitor region and second well is formed in the active transistor regions.
In one embodiment, which is implantation to being relatively shallower than the HV wells but be relatively deeper than the depth of the device area of isolation.Lift
For example, which has about the same depth.There is provided first and second well with different depth may also
It is useful.Other technologies for forming the well are also likely to be useful.First well is to be adulterated with control or capacity type
Thing is lightly doped, and second well is with transistor types dopant medium doped.Other concentration of dopant are also likely to be useful.
612, device grid is formed on the substrate.Gate dielectric layer is set on the substrate and across the device
Region is to form the gate-dielectric of various devices.For example, silicon oxide layer is formed on the substrate to form grid electricity to be situated between
Matter layer.The gate-dielectric can be defined in different thickness for different device regions.In one embodiment, gate electrode layer,
Such as polysilicon layer, it is arranged on the gate dielectric layer and patterns forms the gate electrode of the various devices.It is real one
Apply in example, which is doped polysilicon layer.For example, the gate electrode of control gate with control or capacity type adulterate
Thing pre-doping is to form the control gate.The gate electrode and gate-dielectric patterning with the grid of forming apparatus, such as HV,
MV and/or LV devices.The sustainable formation storage unit of the technique, such as MTP storage units.In one embodiment, the storage list
Member is as made by HV and/or MV devices.For example, the access and storage transistor be MV devices and this to control capacitance be HV
Device.
614, diffusion extension region domain is formed.In one embodiment, LDD and annular section, which are formed in, is adjacent to the crystal
The side of tube grid, extend under the grid.For example, one is used to share implantation shade to form the LDD and ring-type
Region.For example, the implantation shade is to form annular section in the first implantation step, and performs second step to be formed
LDD region domain enters the annular section to form the ring-type of the transistor and LDD region domain.It is also possible that with other suitable technologies with
Form the ring-type and LDD region domain.It is being also likely to be useful without LDD region domain is provided under annular section.
616, gate lateral wall distance piece is formed.Dielectric spacer layer may be provided on the substrate and cover the device
Region.The dielectric spacer layer patternable is to form gate lateral wall distance piece.For example, which is overlapped in
The LDD and annular section.In one embodiment, the substrate regions for being adjacent to the exposure of the sidewall spacer are with first or second
The heavy doping of polarity type dopant is to form transistor diffusion region.For example, transistor diffusion region implantation is more deeper than
The LDD and annular section and it is approximately aligned with to the gate lateral wall distance piece.
618, conductive contact bolt is formed.In one embodiment, capacitance contact bolt is formed on the control well.Citing comes
Say, single mosaic technology can be used in pre-metal dielectric (PMD) layer (not shown) being arranged on the substrate to be formed
The Capacity control bolt.The capacitance contact bolt coupled to the active capacitor region between the device area of isolation and the capacitance it
Between.For example, which is arranged adjacently to the side of the control gate.The other configurations of Capacity control bolt may also
It is useful.In one embodiment, which is conductive contact bolt.For example, which can connect for tungsten
Touch bolt.The other types of conductive contact bolt are also likely to be useful.The capacitance contact bolt is as well tap with for the capacitance
Well picking region.
The technique is persistently completed to form the device.The technique may include to be formed interlayer dielectric (ILD) layer, to the storage list
Metal-silicides Contact, conductive contact and one or more interconnection hierarchies of the terminal of member, final passivation (final
Passivation), cut, assemble and pack.It may also include to complete to be formed other techniques of the device.Other are closed
Suitable technique is also likely to be useful with the device formed as shown in figs. 2 a-2 c.
Under the spirit or essential characteristics without departing from this case, inventive concept of the invention may be implemented in other specific shapes
Formula.Therefore, embodiment above is considered as illustrative in every respect, and unrestricted invention as described herein.Cause
This points out the scope of the present invention by claims, rather than by description above, and be intended to encompass in the claims
The meaning of equipollent and within the scope of all conversion.
Claims (20)
1. a kind of non-volatile multiple programmable storage unit, including：
The substrate of first and second isolation well is had, wherein, which is arranged in the first isolation well；
First and second well being arranged in the second isolation well；
It is adjacent to each other and be arranged at the first transistor with selection gate on second well and with floating grid
Second transistor, the transistor include first and second diffusion zone for being arranged adjacently to the side of the grid；And
The control gate being arranged on first well, wherein,
The control gate is coupled to the floating grid, and the control gate and floating grid include extend across this first and the
The identical grid layer of two wells,
The control gate includes capacitance, and
The second isolation well is configured to improve the isolation of first well during device operates.
2. storage unit according to claim 1, wherein, which is the first polarity type, and second well is
Different from the second polarity type of first polarity type.
3. storage unit according to claim 2, wherein, which is N-shaped well and second well is p-type well, its
In each floating grid and the selection grid include N-shaped metal-oxide semiconductor, and wherein the control gate includes N-shaped
Capacitance.
4. storage unit according to claim 3, wherein, by Fowler-Nordheim (FN) tunneling effect, the storage
Unit is programmable.
5. storage unit according to claim 3, wherein, by Fowler-Nordheim (FN) tunneling effect, the storage
Unit is to erase.
6. storage unit according to claim 3, which includes the capacitance contact bolt coupled to first well.
7. storage unit according to claim 1, wherein, which includes high voltage well area, and height electricity
Kill-job region includes being deeper than the depth of first and second well.
8. storage unit according to claim 7, wherein, which includes being deeper than the depth of the high voltage well area
Degree.
9. storage unit according to claim 8, wherein, the high voltage well area for the second polarity type and this first
It is the first polarity type different from second polarity type to isolate well.
10. storage unit according to claim 9, wherein, which is the shared well area of storage array.
11. storage unit according to claim 8, wherein, which is the height electricity different from the second polarity type
First polarity type in kill-job region.
12. storage unit according to claim 1, the storage unit include being arranged in the substrate between this first and the
Primary layer between two wells.
13. a kind of non-volatile multiple programmable storage unit, including：
The substrate of first and second isolation well is had, wherein the second isolation well is arranged within the first isolation well；
First and second well being arranged in the second isolation well；
It is adjacent to each other and be arranged at the first transistor with selection gate on second well and with floating grid
Second transistor, the transistor include first and second diffusion zone for being arranged adjacently to the side of the grid；And
The control gate being arranged on first well, the wherein control gate are coupled to the floating grid, and the control gate
Pole and floating grid include the identical grid layer for extending across first and second well,
Wherein, the second isolation well is configured to improve the isolation of first well during device operates.
14. storage unit according to claim 13, wherein, which is the storage unit around storage array
Share second isolation well.
15. storage unit according to claim 14, wherein, which includes the first polarity type and well area is
Different from the second polarity type of first polarity type.
16. storage unit according to claim 14, wherein, which is set including AND type.
17. storage unit according to claim 14, wherein, which is set including NOR type.
18. storage unit according to claim 13, which includes the original between first and second well
Generating layer.
19. storage unit according to claim 13, wherein：
The first isolation well includes the first polarity type；And
The second isolation well includes the second polarity type.
20. a kind of method for forming non-volatile multiple programmable storage unit, including：
Substrate is provided；
First and second isolation well is formed in the substrate；
First and second well is formed in the second isolation well；
Form the first transistor with selection gate and the second transistor with floating grid adjacent to each other and in this
On two wells, the transistor includes first and second diffusion zone for being formed adjacent to the side of the grid, wherein,
First and second transistor with series coupled, and
First and second transistor shares shared second diffusion zone；And
Control gate is formed on first well, wherein
The control gate is coupled to the floating grid, and the control gate and floating grid include extend across this first and the
The identical grid layer of two wells,
The control gate includes capacitance, and
The second isolation well is configured to improve the isolation of first well during device operates.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/253,878 | 2014-04-16 | ||
| US14/253,878 US9362374B2 (en) | 2013-06-27 | 2014-04-16 | Simple and cost-free MTP structure |
| US14/684,298 | 2015-04-10 | ||
| US14/684,298 US9406764B2 (en) | 2013-06-27 | 2015-04-10 | Simple and cost-free MTP structure |
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| Publication Number | Publication Date |
|---|---|
| CN105047667A CN105047667A (en) | 2015-11-11 |
| CN105047667B true CN105047667B (en) | 2018-04-13 |
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| CN201510177999.1A Expired - Fee Related CN105047667B (en) | 2014-04-16 | 2015-04-15 | Simple and cost free multiple programmable structure |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197377A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Single layer polysilicon grid MTP device and manufacturing method thereof |
| CN101330107A (en) * | 2007-06-18 | 2008-12-24 | 联华电子股份有限公司 | Time-after-time programmable memory and manufacturing method thereof |
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| US20070247915A1 (en) * | 2006-04-21 | 2007-10-25 | Intersil Americas Inc. | Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide |
| US8344443B2 (en) * | 2008-04-25 | 2013-01-01 | Freescale Semiconductor, Inc. | Single poly NVM devices and arrays |
| KR101688831B1 (en) * | 2010-04-07 | 2016-12-22 | 삼성전자 주식회사 | Semiconductor integrated circuit device and fabricating method the device |
| JP2013187534A (en) * | 2012-03-08 | 2013-09-19 | Ememory Technology Inc | Erasable programmable single-poly nonvolatile memory |
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2015
- 2015-04-15 CN CN201510177999.1A patent/CN105047667B/en not_active Expired - Fee Related
- 2015-04-16 KR KR1020150053989A patent/KR20150119819A/en unknown
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101197377A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Single layer polysilicon grid MTP device and manufacturing method thereof |
| CN101330107A (en) * | 2007-06-18 | 2008-12-24 | 联华电子股份有限公司 | Time-after-time programmable memory and manufacturing method thereof |
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| KR20150119819A (en) | 2015-10-26 |
| TWI594401B (en) | 2017-08-01 |
| CN105047667A (en) | 2015-11-11 |
| TW201605025A (en) | 2016-02-01 |
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