CN107316867A - Flash memory storage array and its manufacture method - Google Patents
Flash memory storage array and its manufacture method Download PDFInfo
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- CN107316867A CN107316867A CN201710487584.3A CN201710487584A CN107316867A CN 107316867 A CN107316867 A CN 107316867A CN 201710487584 A CN201710487584 A CN 201710487584A CN 107316867 A CN107316867 A CN 107316867A
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
The present invention provides a kind of flash memory storage array and its manufacture method, the new storage array by defining, cancel the isolation structure between active area and the conductive contact plug structure of each storage position drain region, the source area and drain region for making all storages position of same column are connected respectively by two conductive contact connectors, so as to significantly lower the area of single storage position, the etching and filling difficulty of the process window of conductive contact connector is greatly reduced, the design size micro for control gate polar curve direction provides feasibility.
Description
Technical field
The present invention relates to ic manufacturing technology field, more particularly to a kind of flash memory storage array and its manufacture method.
Background technology
Current floating gate type NOR Flash (or non-flash) storage array be using floating transistor as elementary cell, it is therein
Multiple floating transistors are connected with parallel way, and each floating transistor has contact hole (Contact) phase in drain terminal (Drain)
Even, to be connected on corresponding bit line (BL), thus, single storage position (Bit, i.e. memory cell) size is on the one hand caused
Greatly, so cause whole storage array area it is big；On the other hand the complex manufacturing technology of NOR Flash storage arrays is caused,
When being further continued for small size micro (Shrink), the challenge of meet casual labourer's skill and the increase of cost.
The content of the invention
It is an object of the invention to a kind of flash memory storage array and its manufacture method, the area of memory cell can be reduced,
Reduce technology difficulty.
To achieve these goals, the present invention provides a kind of flash memory storage array, including：
Semiconductor substrate；
A plurality of source area and a plurality of drain region, are arranged in the Semiconductor substrate by row are parallel and alternate, and adjacent
Source area and drain region between there is spacer region；
A plurality of control gate polar curve, it is arranged in parallel on the semiconductor substrate by row；
Multiple memory nodes, positioned at the overlapping place of the control gate polar curve and the spacer region, and positioned at the control gate
Between polar curve and the spacer region；
Multiple conductive contact connectors, are arranged on above one end of every source area and every drain region accordingly
One end above, and be respectively positioned on the outside of the control gate polar curve at the adjacent edge at the end.
Optionally, the memory node include being sequentially located at tunneling medium layer on the spacer region surface at the overlapping place,
Dielectric layer between floating gate layer and grid.
Optionally, the tunneling medium layer includes at least one of silica, silicon nitride, silicon oxynitride and high K dielectric；
Dielectric layer includes at least one of silica, silicon nitride and silicon oxynitride between the grid.
Optionally, the conductive contact connector and the first metal interconnecting wires electricity above one end of the source area of even column connect
Touch, conductive contact connector and the electrical contact of the second metal interconnecting wires above one end of the source area of odd column；Described in every
Conductive contact connector above one end of drain region makes electrical contact with corresponding 3rd metal interconnecting wires, to form bit line.
Optionally, the multiple conductive contact connector is respectively positioned on same one end of the flash memory storage array；Or institute is active
Conductive contact connector above polar region is located at the conductive contact connector above one end of the flash memory storage array, all drain regions
Positioned at the other end of the flash memory storage array.
Optionally, the flash memory storage array be or non-flash storage array.
The present invention also provides a kind of manufacture method of flash memory storage array, comprises the following steps：
Semiconductor substrate is provided, tunneling medium layer and floating gate layer are sequentially formed on the semiconductor substrate；
The floating gate layer is at least etched in column direction, to form a plurality of groove by row arrangement；
Semiconductor substrate to the channel bottom carries out source area ion implanting or drain region ion implanting, to be formed
By arranging the parallel and alternate a plurality of source area being arranged in the Semiconductor substrate and a plurality of drain region, and adjacent source area
There is spacer region between drain region；
Dielectric layer and control gate layer between grid are sequentially formed above the floating gate layer and source area and drain region；
Dielectric layer, floating gate layer and tunneling medium layer are sequentially etched between the control gate layer, grid to described half by line direction
Conductor substrate surface, to form control gate polar curve and floating boom；And
Conductive contact connector is formed above one end of one end side of the source area and drain region.
Optionally, the Semiconductor substrate to the channel bottom carries out source area ion implanting or drain region ion implanting
Before, the Semiconductor substrate first to the channel bottom carries out lightly doped drain ion implanting.
Optionally, the tunneling medium layer includes at least one of silica, silicon nitride, silicon oxynitride and high K dielectric；
Dielectric layer includes at least one of silica, silicon nitride and silicon oxynitride between the grid.
Optionally, the manufacture method also includes：
Formed on the floating gate layer and source area and drain region between grid before dielectric layer, in the floating gate layer and described
The blanket dielectric layer exposed at the top of the floating gate layer is formed in flute surfaces；
The floating gate layer of diverse location to exposing is etched back
Optionally, the step of conductive contact connector is formed on the source area of the channel bottom and drain region includes：
Self-aligned metal silicate is formed on the source area, drain region and control gate polar curve surface；
The dielectric layer between the whole surface upper caldding layer comprising the self-aligned metal silicate；
The interlayer dielectric layer above one end of the source area and above one end of the drain region is etched, described in certainly
Metal silicide surface is directed at, to form contact window；
Conducting metal is filled in the contact window, to form conductive contact connector.
Optionally, the manufacture method also includes：Covered in the whole surface comprising the self-aligned metal silicate
Before interlayer dielectric layer, one layer of contact etching is first covered in the whole surface comprising the self-aligned metal silicate and is stopped
Layer；The interlayer dielectric layer and contact etching stop layer above one end side of the source area and one end of the drain region are etched,
Until the self-aligned metal silicate surface, to form contact window.
Optionally, a plurality of metal interconnecting wires, institute are formed in the top of the interlayer dielectric layer and the conductive contact connector
A plurality of metal interconnecting wires are stated including first metal interconnecting wires, second metal interconnecting wires and a plurality of are different from the first metal
Conduction above 3rd metal interconnecting wires of interconnection line and the second metal interconnecting wires, and one end of the source area of even column connects
Touch connector and first metal interconnecting wires electrical contact, conductive contact connector above one end of the source area of odd column and
The second metal interconnecting wires electrical contact；Conductive contact connector and corresponding 3rd gold medal above one end of every drain region
Belong to interconnection line electrical contact, to form bit line.
Optionally, the flash memory storage array be or non-flash storage array.
Compared with prior art, technical scheme has the advantages that：
1st, flash memory storage array of the invention, including put down by the parallel and spaced source area of row and drain region, by row
The storage at the overlapping place of control gate polar curve (CG), the spacer region between control gate polar curve and source area and drain region of row arrangement
Node and the conductive contact connector above every source area one end and above the one end of every drain region, i.e., one storage position
The source area of (Bit, or be memory cell) and drain region adhere to two row separately, and the drain region of each storage position no longer needs conduction to connect
The source electrode and drain electrode for touching the storage position in connector (contact), same row are connected respectively by two common conductive contact connectors,
The isolation structure and the conductive contact connector of each storage position drain region of the storage interdigit in existing storage array are avoided, greatly
Width reduces the area of single storage position, is the design size micro in control gate polar curve direction (i.e. line direction, wordline WL directions)
(Shrink) provide feasibility, such as when the flash memory storage array is the storage array of 65nm NOR flash memories, Mei Gecun
The area of storage space is reduced to 180nm (WL) * 120nm (BL), is that the single storage plane of current 45nm NOR flash memories is accumulated
81.4%.
2nd, the manufacture method of flash memory storage array of the invention, is initially formed and described partly leads by arranging parallel and alternate be arranged in
A plurality of source area and a plurality of drain region in body substrate, it is rear formed by row control gate polar curve arranged in parallel and in spacer region and
Form floating boom between control gate polar curve, eliminate for store interdigit isolation STI isolation technologies and for each storage position
The conductive contact plug process of drain region, significantly reduces etching and the filling of contact window for forming conductive contact connector
Technology difficulty, the design size micro for control gate polar curve direction (i.e. line direction, word-line direction) provides feasibility.
Brief description of the drawings
Figure 1A is a kind of storage array equivalent circuit diagram of floating gate type NOR flash memory；
Figure 1B is the storage array domain structure schematic diagram of the floating gate type NOR flash memory shown in Figure 1A；
Fig. 1 C are the cross-sectional views in the xx ' directions of the storage array domain shown in Figure 1B；
Fig. 1 D are the cross-sectional views in the yy ' directions of the storage array domain shown in Figure 1B；
Fig. 2A is the domain structure schematic diagram of the flash memory storage array of the specific embodiment of the invention；
Fig. 2 B are the cross-sectional views in the xx ' directions of the flash memory storage array domain shown in Fig. 2A；
Fig. 2 C are the schematic equivalent circuits of the flash memory storage array shown in Fig. 2A；
Fig. 3 is the manufacture method flow chart of the flash memory storage array of the specific embodiment of the invention；
Fig. 4 A to 4F are that the device architecture section in the manufacture method of the flash memory storage array of the specific embodiment of the invention shows
It is intended to.
Embodiment
Figure 1A is refer to, in current floating gate type NOR Flash (or non-/ anti-or flash memory), its storage array is with floating
Gate transistor Cell is elementary cell, and multiple floating transistor MOS pass through parallel way by matrix (i.e. by row by row) arrangement
It is connected with each other, each floating transistor MOS source S is common by Common Source (common source line) connections, drain D difference
Be connected to corresponding bit line (Bitline, BL) BL0, BL1 ..., on BLn-1, BLn, grid G is connected to corresponding wordline
(wordline, WL, i.e. control gate polar curve) WL0, WL1, WL2, WL3 ....The corresponding domain of the storage array (layout) is as schemed
Shown in 1B, including active area (AA) 101, fleet plough groove isolation structure (STI) 102, control gate polar curve (CG, i.e. wordline) 103, floating boom
(FG) the conductive contact connector (Contact) 107 on 104, source area 105, drain region 106 and drain region 106, active area
101 by row arrangement, and by rows, the overlapping place of every control gate polar curve 103 and active area 101 is to deposit to control gate polar curve 103
Storage unit Cell position, the memory cell Cell of same column shares same active area 101, and each memory cell Cell source
Polar region 105 and drain region 106 are located in same row active area 101, and the memory cell Cell of colleague shares same control gate
Line, Fig. 1 C and Fig. 1 D respectively illustrates the often row structure of the storage array and the cross-section structure per array structure, each column active area
101 are kept apart by fleet plough groove isolation structure 102, there is tunnel oxide 108, floating boom between active area 101 and floating boom 104
There is ONO (oxide layer-nitride layer-oxide layer) layer 109 between 104 and control gate polar curve 103, conductive contact connector 107 is formed
In interlayer dielectric layer 110, and made electrical contact with by silicide 112 with drain region 105.A kind of manufacture of current this storage array
Method comprises the following steps：
First there is provided Semiconductor substrate 100, tunnel oxide 108 is sequentially depositing in the Semiconductor substrate 100 and floating
Gate layer 104；
Then, the floating gate layer 104, tunnel oxide 108 and the formation of Semiconductor substrate 100 are etched by the multiple of row arrangement
Shallow trench；
Then, top is filled in the shallow trench and is higher than the spacer medium of floating gate layer 104, then pass through flatening process
The spacer medium and floating gate layer 104 is in same plane, and further return quarter the spacer medium with remove be located at it is adjacent
Part between floating gate layer 104, so as to form STI 102 and the active area 101 by row arrangement；
Then, ONO layer 109 and control grid layer are deposited on floating gate layer 104, STI 102 and the surface of active area 101, and
Control grid layer, ONO layer 109 and floating gate layer 104 are etched, to form control gate polar curve 103 and independent floating boom by rows
104, independent floating boom 104 is located at the overlapping place of control gate polar curve 103 and active area 101；
Then, side wall is formed in the laminated construction both sides of floating boom 104 to control gate polar curve 103, and to the laminated construction
The active area 101 gone out with side wall exposed at both sides carries out source and drain ion implanting, forms source area 105 and drain region 106；
Then, self-aligned silicide 112 is formed on control gate polar curve 103 and drain region 106；
Afterwards, interlayer dielectric layer 110, and etch the formation contact hole of interlayer dielectric layer 110 of the top of drain region 106
Mouthful, the conductive materials such as tungsten are filled in contact window to form conductive contact connector 107.
Because above-mentioned floating gate type NOR Flash each memory cell cell has conductive contact to insert in drain region 105
Plug 107 is connected, and the size of of one side conductive contact connector 107 itself make it that the size of single storage position (Bit) is larger, and then makes
The area of whole storage array is larger, such as single using the storage array of self-aligned contact hole technique formation under 45nm processing procedures
Bit size is 225nm (WL, wordline) * 118nm (BL, bit line), and its grid length (i.e. CG length) is 105nm, and it has
The line width (i.e. AA width) of source region 101 is that the line width (i.e. AA space) of the STI 102 between 59nm, its active area 101 is
59nm, the line width (i.e. Source space) of its source area 106 is 120nm, line width (the i.e. Drain of its drain region 105
Space) it is 120nm；The storage array formed again for example under 65nm processing procedures using self-aligned contact hole technique, single Bit chi
Very little is 300nm (WL, wordline) * 150nm (BL, bit line), and its grid length (CG length) is 125nm, its active area 101
Line width is 70nm, and the line width of the STI 102 between its active area 101 is 59nm, the line width (SAS space) of its silicide 112
It is 95nm, the line width of its drain region 105 is 225nm；On the other hand, due to needing on the drain region 105 of each memory cell
Make conductive contact connector 107, complex process, when storage array continues to small size micro the challenge of meet casual labourer's skill and into
This increase.
Technical scheme mainly by defining new storage array, cancel in above-mentioned storage array active area it
Between STI 102 (STI for cancelling colleague floating boom bottom), while cancelling the conductive contact connector of each Bit drain regions, make same
The source area (source) and drain region (drain terminal) of all storages position of row are connected respectively by two conductive contact connectors, so that significantly
Lower single Bit area, the etching and filling difficulty of the process window of conductive contact connector is greatly reduced, is control gate polar curve
The design size micro in (i.e. wordline) direction provides feasibility.
To become apparent the purpose of the present invention, feature, the embodiment to the present invention is made below in conjunction with the accompanying drawings
Further instruction, however, the present invention can be realized with different forms, should not be to be confined to described embodiment.
Fig. 2A and Fig. 2 B are refer to, the present invention provides a kind of flash memory storage array, including：Semiconductor substrate 200, a plurality of source
Polar region 201, a plurality of drain region 202, multiple memory node cell, a plurality of control gate polar curve 203 and multiple conductive contact connectors
205.Wherein, source area 201 is arranged in the Semiconductor substrate 200 with drain region 202 by row are parallel and alternate, and adjacent
Source area 201 and drain region 202 between there is spacer region and (arrange and do not carry out the Semiconductor substrate of source-drain area ion doping upwards
200).Control gate polar curve (CG) 203 is wordline WL, is arranged in parallel within by row in the Semiconductor substrate 200, every control gate
Line 203 intersects vertically with each bar source area 201 and drain region 202.Memory node cell (storing position) is located at every respectively
The overlapping place of control gate polar curve 203 and every spacer region, and be located between this control gate polar curve 203 and the spacer region, institute
Some memory node cell by row form storage array by row, refer to Fig. 2 B, the memory node cell of the present embodiment include according to
Dielectric layer 208, the Tunnel dielectric between the secondary tunneling medium layer 206 being located on the surface of Semiconductor substrate 200, floating gate layer 204, grid
Layer 206 can be single layer structure, or laminated construction, its material can include silica, silicon nitride, silicon oxynitride and height
At least one of K media；Dielectric layer 208 can be single layer structure between the grid, or laminated construction, its material includes
Dielectric layer 208 is ONO (oxide-nitrides-oxidation between at least one of silica, silicon nitride and silicon oxynitride, such as grid
Layer) laminated construction.Memory node cell and the control gate of the part of source area 201, the part of drain region 202 and top of its both sides
The part of line 203 forms a floating gate type metal-oxide-semiconductor (i.e. one memory cell), real under the signal that conductive contact connector 205 is transmitted
Existing data storage, erasing etc..Each conductive contact connector 205 is arranged on one end of source area 201 described in each bar accordingly respectively
Above one end of drain region 202 described in top and each bar, and be respectively positioned on the control gate polar curve 203 at the adjacent edge at the end
Outside.Thus, the source area 201 (i.e. the source of floating gate type metal-oxide-semiconductor) of the memory cell on same column passes through the end of row source area 201
A conductive contact connector 205 in portion is connected, the drain region 202 of the memory cell on the same column (i.e. floating gate type metal-oxide-semiconductor
Drain terminal) connected by a conductive contact connector 205 on the end of row drain region 202, and the one of the source area 201 of even column
The metal interconnecting wires of conductive contact connector 205 and first electrical contact (not shown) above end, one end of the source area 202 of odd column
The metal interconnecting wires of conductive contact connector 205 and second electrical contact (not shown) of top；Above one end of drain region described in each bar
Conductive contact connector 205 respectively with corresponding one article of the 3rd metal interconnecting wires it is (not shown) electrical contact, to form each bar bit line.
Fig. 2 C are refer to, Fig. 2 C are the equivalent circuit of the flash memory storage array domain shown in Fig. 2A, the storage array circuit
Including m*n floating gate type metal-oxide-semiconductor of the matrix form for being arranged in m rows n row, grid (G, i.e. control gate of each row floating gate type metal-oxide-semiconductor
Pole) be connected to corresponding wordline WL1, WL2 ..., on WLm-1, WLm, wordline WL1, WL2 ..., WLm-1, WLm be m bar control gates
Polar curve 203 is formed by rows, the drain terminal (D) of each row floating gate type metal-oxide-semiconductor be connected to corresponding bit line BL0, BL1 ..., BLn-1,
On BLn, bit line BL0, BL1 ..., BLn-1, BLn can be above n bars drain region 202 or the end of n bars drain region 202
Conductive contact connector 205 connect n articles of the 3rd metal interconnecting wires (not shown), the source (S) of each row floating gate type metal-oxide-semiconductor is repeatedly
Be connected to corresponding source line SL0, SL1 ..., on SLn-1, SLn, and source line SL0, SL2, SL4 ... of even column one end are connected to
" even column source " is formed together, source line SL1, SL3, SL5 ... of odd column one end are joined together to form " odd column source
End ", thus inputs corresponding signal, while inputting corresponding signal on bit line and wordline in even column source and odd column source
When, can choose data storage of floating gate type metal-oxide-semiconductor of relevant position etc. operate, source line SL0, SL1 ..., SLn-1, SLn be n
Bar source area 201, the source area 201 of even column is connected to the first metal by the conductive contact connector 205 of respective end and interconnected
Line, the signal input part of the first metal interconnecting wires is used as " even column source ", and the source area 201 of odd column passes through respective end
Conductive contact connector 205 be connected to the second metal interconnecting wires, the signal input part of the second metal interconnecting wires is used as " odd column
Source ".
Optionally, all conductive contact connectors 205 are respectively positioned on same one end of the flash memory storage array, to reduce technique
Stack alignment difficulty；Or the conductive contact connector 205 of all tops of source area 201 is located at the one of the flash memory storage array
End, the conductive contact connector 205 of all tops of drain region 202 is located at the other end of the flash memory storage array, to be conducive to subtracting
The size of small conductive contact connector, increases the effective area of storage array.
In summary, flash memory storage array of the invention, including by arrange parallel and spaced source area and drain region,
By row control gate polar curve (CG) arranged in parallel, the overlapping place of the spacer region between control gate polar curve and source area and drain region
Memory node and the conductive contact connector above every source area one end and above the one end of every drain region, i.e., one
The source area and drain region for storing position (Bit, or be memory cell) adhere to two row separately, and the drain region of each storage position no longer needs
The source electrode of storage position in conductive contact connector (contact), same row and drain electrode are by two common conductive contact connectors point
Do not connect, it is to avoid the isolation structure of the storage interdigit in existing storage array and the conductive contact of each storage position drain region
Plug structure, significantly reduces the area of single storage position, is setting for control gate polar curve direction (i.e. line direction, wordline WL directions)
Count size micro (Shrink) and provide feasibility, such as when the flash memory storage array of the present invention is applied to 65nm NOR flash memories
When, the area of each storage position is reduced to 180nm (WL) * 120nm (BL), is the single storage plane of current 45nm NOR flash memories
Long-pending 81.4%.
Fig. 3 is refer to, the present invention provides a kind of manufacture method of flash memory storage array, comprised the following steps：
S1 sequentially forms tunneling medium layer and floating gate layer on the semiconductor substrate there is provided Semiconductor substrate；
S2, at least etches the floating gate layer in column direction, to form a plurality of groove by row arrangement；
S3, the Semiconductor substrate to the channel bottom carries out source area ion implanting or drain region ion implanting, with
Formed by the parallel and alternate a plurality of source area being arranged in the Semiconductor substrate of row and a plurality of drain region, and adjacent source
There is spacer region between polar region and drain region；
S4, sequentially forms dielectric layer and control gate between grid above the floating gate layer and source area and drain region
Layer；
S5, dielectric layer, floating gate layer and tunneling medium layer are sequentially etched between the control gate layer, grid to described by line direction
Semiconductor substrate surface, to form control gate polar curve and floating boom；And
S6, forms conductive contact connector above one end of one end side of the source area and drain region.
Refer to Fig. 4 A, in step sl there is provided Semiconductor substrate 400 can for silicon (Si), SiGe (SiGe), insulation
Layer overlying silicon (SOI), silicon-on-insulator germanium (SGOI) or insulating barrier overlying germanium (GOI) etc..The side of ion implanting can be used
Formula can form the well region of difference in functionality, and such as Semiconductor substrate 400 is p-substrate, can first using traditional photomask and from
Sub- injection technique, forms deep n-well region (not shown), p-well region is then formed in deep n-well region, can carry out being used to adjust afterwards
The ion implanting of the threshold voltage of memory block and external zones, and remove photomask after ion implanting is completed.Then it can use
Thermal oxidation technology or low-pressure chemical vapor deposition (LPCVD) technique etc. form tunnel in the whole surface of Semiconductor substrate 400
Dielectric layer 401 is worn, the tunneling medium layer 401 can be single layer structure or laminated construction, and its material includes oxidation
At least one of silicon, silicon nitride, silicon oxynitride and high K dielectric.Then using chemical vapor deposition method etc. in Tunnel dielectric
Floating gate layer 402 is formed on 401 surface of layer, the material of floating gate layer 402 can include in polysilicon, silicon nitride, silicon point or metal dots
At least one.When floating gate layer 402 is polysilicon, doping (in-situ) in situ is preferably carried out while deposition, to carry
High device performance.
Please continue to refer to Fig. 4 A, in step s 2, the floating gate layer 402, tunneling medium layer 401 and semiconductor are sequentially etched
Substrate 400 forms a plurality of groove 403, and groove 403 is arranged on the surface of Semiconductor substrate 400 by row and quantity is even number, with
The groove formation source area 404 of later use odd column, utilizes the groove formation drain region 405 of even column；In its of the present invention
In his embodiment, in order to preferably protect base semiconductor substrate 400, the formation of floating gate layer 402 ditch can also be only etched
Groove 403, to prevent Semiconductor substrate 400 from producing extra damage in follow-up source-drain area ion implanting using tunneling medium layer 401
Wound.
, in step s3, can be first to the bottom of groove 403 after the formation of groove 403 by row arrangement please continue to refer to Fig. 4 A
The Semiconductor substrate 400 in portion carries out lightly doped drain (Lightly Doped Drain, LDD) ion implanting, is lightly doped with being formed
The ion used in area 406, the lightly doped drain ion implantation technology can be arsenic, to reduce short channel effect, lifting
Performance, enhancing internal memory write efficiency.Then the Semiconductor substrate 400 respectively to the bottom of groove 403 of odd column and even column is entered
The different heavy doping source and drain ion implanting of row, so that the formation source area 404 of Semiconductor substrate 400 of the bottom of odd column groove 403
(or drain region 405), makes the formation of Semiconductor substrate 400 drain region 405 (or source area 404) of the bottom of even column groove 403.Phase
The half of the remaining bottom of floating gate layer 402 after the spacer region i.e. step S2 etchings existed between adjacent source area 404 and drain region 405
The part of conductor substrate 400.When Semiconductor substrate 400 is P type substrate, the ion injected in source area 404 can be phosphorus and arsenic, leakage
The ion injected in polar region 405 can be phosphorus.When the NOR flash memory for making 65nm, the line width of source area 404 can be
60nm, the line width of drain region 405 can be 60nm.This obvious step is directly using groove formation source area and drain region, and this is
Different from utilizing the technology of groove formation fleet plough groove isolation structure in the prior art.
Fig. 4 B to 4D are refer to, in order to adjust the altitudinal gradient between each memory node of storage array and strengthen follow-up shape
Into floating boom and control gate polar curve between insulating properties, first can use low thermal oxidation (LTO) technique or depositing operation extremely
It is few to form blanket dielectric layer 407 in the side wall of floating gate layer 402 and top；Then, Fig. 4 C are refer to, pass through cmp
(CMP) technique removes the blanket dielectric layer 407 at the top of floating gate layer 402, and entering to the floating gate layer 402 of diverse location that exposes
Row is a certain degree of to be etched back to, and the depth being etched back to can be with identical in diverse location, can also be different, such as 402a in Fig. 4 D
Put that to be etched back to depth with the floating gate layer 402 of 402b positions different.
Fig. 4 E are refer to, in step s 4, can be using chemical vapor deposition method etc. in floating gate layer 402, the table of groove 403
Be sequentially depositing on face dielectric layer 408 between dielectric layer 408 and control gate layer 409 between grid, grid can be single layer structure or
Laminated construction, its material can include at least one of silica, silicon nitride and silicon oxynitride.It is preferred that, dielectric layer between grid
408 be ONO (silicon oxide-silicon nitride-silica) three-decker of high temperature chemical vapor deposition technique formation, to improve absolutely
Edge performance, improves data storage performance.The material of control gate layer 409 can be polysilicon, or polysilicon and thereon
The metal or metal silicide of side, carry out doping (in-situ) in situ, to improve device while control gate layer 409 is deposited
Part performance.
Please continue to refer to Fig. 4 E, in step s 5, by line direction (with source area 404 i.e. in the plane of Semiconductor substrate 400
The vertical direction with drain region 405) it is sequentially etched dielectric layer 408 between control gate layer 409, grid, blanket dielectric layer 407, floating boom
Layer 402 and tunneling medium layer 401, to form control gate polar curve and independent floating boom, each control gate polar curve and source area
404th, drain region 405 is vertical, and independent floating boom is located above the spacer region between adjacent source area 404, drain region 405.When
During NOR flash memory for making 65nm, the line width (CG length) of control gate polar curve can be 60nm, every control gate polar curve
Left side interval (CG left space) can be 60nn, right side interval (CG right space) can be 60nm.
It is preferred that, laminated construction that can be using side wall technique in control gate polar curve to tunneling medium layer 401 (stores section
Point) manufacture grid curb wall (not shown) on the wall of side, to ensure the isolation performance between control gate polar curve and floating boom, and protect grid processed
The sidewall profile of polar curve to the laminated construction of tunneling medium layer 401 is not subjected to adverse effect in subsequent technique.
Fig. 4 F are refer to, the present embodiment in step s 6, is selected above same one end of source area 404 and drain region 405
Conductive contact connector is made, detailed process is as follows：
First, in control gate polar curve and including on the surface of Semiconductor substrate 400 including source area 404, drain region 405
The protective dielectric layers 410 such as one layer of silica are formed, now protective dielectric layer 410 covers the whole of the top of Semiconductor substrate 400 comprehensively
Individual surface, etches protective dielectric layer 410 to expose one end, drain region 405 and one end and control gate of source area 404 afterwards
It is used for the surface for forming conductive contact connector on one end of line；
Then, carry out an autoregistration silication technique for metal, i.e., elder generation including protective dielectric layer 410 and control gate polar curve,
Deposit cobalt (Co) on source area 404, the whole device surface of the exposed surface of drain region 405, titanium (Ti), nickel (Ni), tungsten (W) or
Molybdenum (Mo) ... waits heating resisting metal, then carries out a quick thermal annealing process technique, with described one end of source area 404, drain region
It is each on 405 one end and described control gate polar curve one end to form a self-aligned metal silicate (salicide layer) 411, use
In reduction dead resistance, unnecessary unreacted metal is removed by techniques such as cmps (CMP) afterwards, now substantially
Only remain control gate polar curve, source area 404, the self-aligned metal silicate on the exposed surface of drain region 405；
Then, sunk successively on the whole device surface comprising self-aligned metal silicate by chemical vapor deposition method
A product one contact etching stop layer 412 and interlayer dielectric layer 413, contact etching stop layer 412 can be silica, silicon nitride or
Silicon oxynitride, for the self-aligned metal silicate 411 below protection, the material of interlayer dielectric layer 413 includes silica, phosphorus silicon
Glass, boron-phosphorosilicate glass or carborundum etc.；And by cmp (CMP) or eatch-back lithography (Etch Back) to interlayer
The top of dielectric layer 413 is planarized, to provide flat artistic face for subsequent technique；
Then, etching interlayer dielectric layer 413 and contact etching stop layer, with above one end of the drain region 405
Self-aligned metal silicate 412 and control gate polar curve one above self-aligned metal silicate 411, one end of source area 404
A contact openings are formed in self-aligned metal silicate above end；
Then, filling conductive material is formed in contact window to form conductive contact connector 414, specifically, is first existed
One layer of adhesion layer is formed on the surface of interlayer dielectric layer 413 and contact window, the material of adhesion layer can be titanium, titanium nitride, tantalum
Or tantalum nitride, conductive metallic material is continued to fill up into contact window by sputtering process afterwards, until filling up contact window, led
The material of body metal is, for example, aluminium, titanium, chromium, tungsten, cobalt, nickel, copper etc., is then removed by techniques such as CMP beyond contact window
Adhesion layer and conducting metal, to form conductive contact connector 414.
Deposited metal interlayer dielectric layer can be continued on interlayer dielectric layer 413 and the surface of conductive contact connector 414 afterwards,
To manufacture first metal interconnecting wires at the top of conductive contact connector 414 on electrical contact even column source area 404, electrical contact odd column
Conductive contact on the second metal interconnecting wires, each bar drain region 405 of electrical contact on source area 404 at the top of conductive contact connector 414
Each article of the 3rd metal interconnecting wires at the top of connector 414, so as to complete the manufacture of flash memory.
It should be noted that for the manufacture method of the apparent flash memory storage array for intuitively understanding the present invention, Fig. 4 A
Device profile knot in have chosen domain shown in Fig. 2 to Fig. 4 E along control gate polar curve direction and at control gate line position
Structure schematic diagram, and the cross-section structure that Fig. 4 F illustrate only along control gate polar curve direction and at conductive contact plug position shows
It is intended to, those skilled in the art can learn the shaping structures feelings above Semiconductor substrate whole surface according to Fig. 4 A to Fig. 4 F
Condition.In addition, in other embodiments of the invention, the conductive contact connector 414 of source area 404 and the conductive contact of drain region are inserted
The position of plug 414 can belong to the two ends of storage array, to be conducive to the size reduction and technology difficulty of conductive contact connector
Reduction.
In summary, the manufacture method of flash memory storage array of the invention, first with the groove formed after etching floating gate layer,
Formed by the parallel and alternate a plurality of source area being arranged in the Semiconductor substrate and a plurality of drain region is arranged, re-formed afterwards
Floating boom is formed by row control gate polar curve arranged in parallel and between spacer region and control gate polar curve, is eliminated for storing position
Between the STI isolation technologies isolated and the conductive contact plug process for each storage position drain region, significantly reducing is used for
The etching and the technology difficulty of filling of the contact window of conductive contact connector are formed, is control gate polar curve direction (i.e. line direction, word
Line direction) design size micro provide feasibility.
Obviously, those skilled in the art can carry out the spirit of various changes and modification without departing from the present invention to invention
And scope.So, if these modifications and variations of the present invention belong to the claims in the present invention and its equivalent technologies scope it
Interior, then the present invention is also intended to comprising including these changes and modification.
Claims (14)
1. a kind of flash memory storage array, it is characterised in that including：
Semiconductor substrate；
A plurality of source area and a plurality of drain region, are arranged in the Semiconductor substrate by row are parallel and alternate, and adjacent source
There is spacer region between polar region and drain region；
A plurality of control gate polar curve, it is arranged in parallel on the semiconductor substrate by row；
Multiple memory nodes, positioned at the overlapping place of the control gate polar curve and the spacer region, and positioned at the control gate polar curve
Between the spacer region；
Multiple conductive contact connectors, are arranged on the one of above one end of every source area and every drain region accordingly
End top, and it is respectively positioned on the outside of the control gate polar curve at the adjacent edge at the end.
2. flash memory storage array as claimed in claim 1, it is characterised in that the memory node includes being sequentially located at the friendship
Dielectric layer between tunneling medium layer, floating gate layer and grid on the spacer region surface at folded place.
3. floating gate type flash memory storage array as claimed in claim 2, it is characterised in that the tunneling medium layer includes oxidation
At least one of silicon, silicon nitride, silicon oxynitride and high K dielectric；Dielectric layer includes silica, silicon nitride and nitrogen oxygen between the grid
At least one of SiClx.
4. flash memory storage array as claimed in claim 1, it is characterised in that above one end of the source area of even column
Conductive contact connector above conductive contact connector and the electrical contact of the first metal interconnecting wires, one end of the source area of odd column
With the electrical contact of the second metal interconnecting wires；Conductive contact connector and corresponding 3rd metal above one end of every drain region
Linear contact lay is interconnected, to form bit line.
5. flash memory storage array as claimed in claim 1, it is characterised in that the multiple conductive contact connector is respectively positioned on described
Same one end of flash memory storage array；Or the conductive contact connector above all source areas is located at the one of the flash memory storage array
Conductive contact connector above end, all drain regions is located at the other end of the flash memory storage array.
6. flash memory storage array as claimed in claim 1, it is characterised in that the flash memory storage array is or non-flash is deposited
Store up array.
7. a kind of manufacture method of flash memory storage array, it is characterised in that comprise the following steps：
Semiconductor substrate is provided, tunneling medium layer and floating gate layer are sequentially formed on the semiconductor substrate；
The floating gate layer is at least etched in column direction, to form a plurality of groove by row arrangement；
Semiconductor substrate to the channel bottom carries out source area ion implanting or drain region ion implanting, to be formed by row
The parallel and alternate a plurality of source area being arranged in the Semiconductor substrate and a plurality of drain region, and adjacent source area and leakage
There is spacer region between polar region；
Dielectric layer and control gate layer between grid are sequentially formed above the floating gate layer and source area and drain region；
Dielectric layer, floating gate layer and tunneling medium layer are sequentially etched between the control gate layer, grid to the semiconductor by line direction
Substrate surface, to form control gate polar curve and floating boom；And
Conductive contact connector is formed above one end of one end side of the source area and drain region.
8. the manufacture method of flash memory storage array as claimed in claim 7, it is characterised in that to partly leading for the channel bottom
Body substrate is carried out before source area ion implanting or drain region ion implanting, and first the Semiconductor substrate to the channel bottom is entered
Row lightly doped drain ion implanting.
9. the manufacture method of flash memory storage array as claimed in claim 7, it is characterised in that the tunneling medium layer includes oxygen
At least one of SiClx, silicon nitride, silicon oxynitride and high K dielectric；Dielectric layer includes silica, silicon nitride and nitrogen between the grid
At least one of silica.
10. the manufacture method of flash memory storage array as claimed in claim 7, it is characterised in that the manufacture method also includes：
On the floating gate layer and source area and drain region between formation grid before dielectric layer, in the floating gate layer and the groove
The blanket dielectric layer exposed at the top of the floating gate layer is formed on surface；
The floating gate layer of diverse location to exposing is etched back.
11. the manufacture method of flash memory storage array as claimed in claim 10, it is characterised in that in the source of the channel bottom
The step of conductive contact connector is formed on polar region and drain region includes：
Self-aligned metal silicate is formed on the source area, drain region and control gate polar curve surface；
The dielectric layer between the whole surface upper caldding layer comprising the self-aligned metal silicate；
The interlayer dielectric layer above one end of the source area and above one end of the drain region is etched, until the autoregistration
Metal silicide surface, to form contact window；
Conducting metal is filled in the contact window, to form conductive contact connector.
12. the manufacture method of flash memory storage array as claimed in claim 11, it is characterised in that also include：Comprising described
Between the whole surface upper caldding layer of self-aligned metal silicate before dielectric layer, first the self-aligned metal silicate is being included
One layer of contact etching stop layer is covered in whole surface；Etch above one end side of the source area and one end of the drain region
Interlayer dielectric layer and contact etching stop layer, until the self-aligned metal silicate surface, to form contact window.
13. the manufacture method of flash memory storage array as claimed in claim 12, it is characterised in that in the interlayer dielectric layer and
The top of the conductive contact connector forms a plurality of metal interconnecting wires, and it is mutual that a plurality of metal interconnecting wires include first metal
Line, one article of second metal interconnecting wires and a plurality of it is different from the first metal interconnecting wires and the 3rd metal of the second metal interconnecting wires is mutual
Conductive contact connector and first metal interconnecting wires electrical contact above line, and one end of the source area of even column,
Conductive contact connector and second metal interconnecting wires electrical contact above one end of the source area of odd column；Described in every
Conductive contact connector above one end of drain region makes electrical contact with corresponding 3rd metal interconnecting wires, to form bit line.
14. the manufacture method of flash memory storage array as claimed in claim 7, it is characterised in that the flash memory storage array is
Or the storage array of non-flash.
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