JP4758951B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device including a nonvolatile semiconductor memory device.

  EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used as a nonvolatile semiconductor memory device that can be electrically written and erased. These storage devices (memory) typified by currently used flash memory have a conductive floating gate electrode and a trapping insulating film surrounded by an oxide film under the gate electrode of the MISFET. The charge accumulation state in the floating gate and the trapping insulating film is stored information and is read as the threshold value of the transistor. This trapping insulating film refers to an insulating film capable of accumulating charges, and examples thereof include a silicon nitride film. The threshold value of the MISFET is shifted by such charge injection / release to / from the charge storage region to operate as a memory element. As this flash memory, there is a split gate type cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film. In such a memory, by using a silicon nitride film as a charge storage region, it is superior in data retention reliability because it accumulates charges discretely compared to a conductive floating gate film, and also in data retention reliability. Therefore, the oxide films above and below the silicon nitride film can be made thinner, and the voltage of the write / erase operation can be lowered.

  Japanese Patent Laid-Open No. 2003-100915 describes a technique related to contact arrangement with respect to a gate electrode of a nonvolatile semiconductor memory device (see Patent Document 1).

Japanese Patent Application Laid-Open No. 6-333397 describes a technique for applying different voltages to the word lines of memory cells facing each other across a bit line during a write operation (see Patent Document 2).
JP 2003-100915 A JP-A-6-333397

  According to the study of the present inventor, the following has been found.

  In two memory cells adjacent to each other through the source region as shown in FIG. 8, since the source region is common, the potential of the source region is always the same. Further, when the potential of the memory gate electrode is taken out with a common pad in two memory cells adjacent via the source region, the same potential is always applied to the memory gate electrode of the two memory cells. .

  In a write operation, when a predetermined write voltage is applied to each part of a selected memory cell to be written, a selected memory cell and a non-selected memory cell adjacent to the selected memory cell via a source region, The source regions have the same potential in common, and the memory gate electrode also has the same potential as described above. Therefore, when a write voltage is applied to the selected memory cell, the same voltage as that of the selected memory cell is applied to the source region and the memory gate electrode of the non-selected memory cell adjacent to the selected memory cell via the source region. Applied.

  For this reason, in the non-selected memory cell adjacent to the selected memory cell to be written through the source region, the channel current is cut off by the potential of the selection gate electrode of the non-selected memory cell, thereby preventing disturbance of the non-selected memory cell. In practice, however, a high voltage similar to that of the selected memory cell is applied to the source region and the memory gate electrode of the unselected memory cell as described above, so that a junction leakage current is generated between the source and the substrate. As a result, hot electrons generated in this way are taken into the trapping insulating film of the non-selected memory cell, and the threshold voltage of the memory transistor of the non-selected memory cell may increase. As described above, the write disturb applied to the non-selected memory cell adjacent to the write selected memory cell via the source region becomes a problem, which may reduce the performance of the semiconductor device.

  In addition, if the planar layout of the semiconductor device is not designed in consideration of the alignment margin and the dimensional variation margin in the photolithography process, the manufacturing yield of the semiconductor device may be reduced and the semiconductor device may be enlarged. There is.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

The present invention includes a memory array including a plurality of nonvolatile memory cells formed on a semiconductor substrate, the plurality of first nonvolatile memory cells including a first charge storage layer and a first gate electrode, The second nonvolatile memory cell has a second charge storage layer and a second gate electrode, and is disposed adjacent to the first nonvolatile memory cell in the first direction, and the first gate electrode is the first gate electrode. By extending in the second direction crossing the direction, the plurality of first nonvolatile memory cells are arranged in the second direction in an electrically connected state, and the second gate electrode extends in the second direction. Thus, the plurality of second nonvolatile memory cells are arranged in the second direction in an electrically connected state, and the first gate electrode extends toward the second gate electrode in the first direction. The second gate electrode includes the first contact portion and the first gate electrode A second contact portion extending in the direction toward the first gate electrode, wherein the first and second contact portions are formed so as to be shifted in the second direction, and the first gate electrode and the first contact In the portion, the second gate electrode and the second contact portion are electrically separated.

The present invention includes a memory array including a plurality of nonvolatile memory cells formed on a semiconductor substrate, the plurality of first nonvolatile memory cells including a first charge storage layer and a first gate electrode, The second nonvolatile memory cell has a second charge storage layer and a second gate electrode, and is disposed adjacent to the first nonvolatile memory cell in the first direction, and the first gate electrode is the first gate electrode. By extending in the second direction crossing the direction, the plurality of first nonvolatile memory cells are arranged in the second direction in an electrically connected state, and the second gate electrode extends in the second direction. Thus, the plurality of second nonvolatile memory cells are arranged in the second direction in an electrically connected state, and the first gate electrode extends toward the second gate electrode in the first direction. The second gate electrode includes the first contact portion and the first gate electrode A second contact portion extending in the direction toward the first gate electrode, wherein the first and second contact portions are formed shifted in the second direction, and the first nonvolatile memory cell is rewritten. In operation, different voltages are applied to the front gate electrode and the second gate electrode, respectively.

  According to the present invention, a plurality of memory cells are arranged in an array, and a selection gate line connecting the selection gate electrodes of the memory cells arranged in the first direction and a memory gate electrode of the memory cells arranged in the first direction are provided. A plurality of memory gate lines to be connected, and the memory gate lines connected to the memory gate electrodes of memory cells adjacent to each other in the second direction intersecting the first direction via the source region are electrically connected to each other; The voltage can be applied independently.

  According to the present invention, a plurality of memory cells are arranged in an array, and a selection gate line connecting the selection gate electrodes of the memory cells arranged in the first direction and a memory gate electrode of the memory cells arranged in the first direction are provided. A plurality of memory gate lines to be connected, the select gate line including a first portion extending in the first direction and a second portion having one end connected to the first portion and intersecting the first direction; A second portion extending in a direction, and the memory gate line includes a third portion adjacent to the first and second portions of the selection gate line via an insulating film, and a second portion of the selection gate line. And a fourth portion extending in a third direction that intersects the second direction and is formed in an interlayer insulating film on the fourth portion of the memory gate line The conductive portion embedded in the contact hole and the fourth portion of the memory gate line are electrically connected Are those connected.

  The outline | summary of the other invention shown in this application is as follows.

Item 1: (a) A drain region and a source region formed in a semiconductor substrate;
(B) a first gate electrode and a second gate electrode formed on an upper portion of the semiconductor substrate between the drain region and the source region, the first gate electrode positioned on the drain region side; The second gate electrode located on the source region side and adjacent to the first gate electrode via a first insulating film;
(C) a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
(D) a second gate insulating film formed between the second gate electrode and the semiconductor substrate, the second gate insulating film having a charge storage portion therein;
Are arranged in a plurality of arrays,
(E) Of the plurality of memory cells,
A first gate line connecting the first gate electrodes of the memory cells arranged in a first direction;
A second gate line that is adjacent to the first gate line via a second insulating film and connects the second gate electrode of the memory cells arranged in the first direction;
A plurality of
(F) The second gate lines respectively connected to the second gate electrodes of the memory cells adjacent to each other through the source region in the second direction intersecting the first direction are electrically connected to each other. A semiconductor device characterized in that a voltage can be applied independently.

Item 2: In the semiconductor device according to Item 1,
During a write operation to a selected memory cell of the plurality of memory cells, the second gate line connected to the second gate electrode of the selected memory cell, and the selected memory cell via the source region A semiconductor device, wherein a different voltage is supplied to the second gate line connected to the second gate electrode of an unselected memory cell adjacent in the second direction.

Item 3: (a) a first semiconductor region formed in a semiconductor substrate and functioning as one of a drain region or a source region and a second semiconductor region functioning as the other of a drain region or a source region;
(B) a first gate electrode and a second gate electrode formed on an upper portion of the semiconductor substrate between the first semiconductor region and the second semiconductor region, the first gate electrode being located on the front first semiconductor region side; One gate electrode, the second gate electrode located on the second semiconductor region side and adjacent to the first gate electrode via a first insulating film;
(C) a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
(D) a second gate insulating film formed between the second gate electrode and the semiconductor substrate, the second gate insulating film having a charge storage portion therein;
Are arranged in a plurality of arrays,
(E) Of the plurality of memory cells,
A first gate line connecting the first gate electrodes of the memory cells arranged in a first direction;
A second gate line that is adjacent to the first gate line via a second insulating film and connects the second gate electrode of the memory cells arranged in the first direction;
A plurality of
(F) an interlayer insulating film is formed on the semiconductor substrate so as to cover the first and second gate electrodes and the first and second gate lines;
(G) The first gate line includes a first portion extending in the first direction, and one end connected to the first portion and extending in a second direction intersecting the first direction. A second portion present,
(H) The second gate line includes a third portion adjacent to the first and second portions of the first gate line via the second insulating film, and the second portion of the first gate line. A fourth portion extending in a third direction that is adjacent to the portion through the second insulating film and intersects the second direction,
(I) A first contact hole is formed in the interlayer insulating film on the fourth portion of the second gate line, and the first conductor portion embedded in the first contact hole and the second gate line A semiconductor device, wherein the fourth portion is electrically connected.

Item 4: In the semiconductor device according to Item 3,
The semiconductor device is characterized in that the second direction is a direction orthogonal to the first direction.

Item 5: In the semiconductor device according to Item 3,
The semiconductor device is characterized in that the third direction is parallel to the first direction.

Item 6: In the semiconductor device according to Item 3,
The first gate line and the first gate electrode are made of the same first conductor layer, and the second gate line and the second gate electrode are made of the same second conductor layer. A semiconductor device.

Item 7: In the semiconductor device according to Item 3,
The second gate electrode is formed in a sidewall shape on the sidewall of the first gate electrode via the first insulating film,
The third portion of the second gate line is formed in a sidewall shape on the sidewalls of the first and second portions of the first gate line via the second insulating film. A semiconductor device.

Item 8: In the semiconductor device according to Item 3,
The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are made of an insulating film in the same layer as the second gate insulating film.

Item 9: In the semiconductor device according to Item 3,
The semiconductor substrate has an element isolation region made of an insulator,
The fourth portion of the second gate line extends in the third direction from the top of the second portion of the first gate line to the element isolation region. apparatus.

Item 10: In the semiconductor device according to Item 9,
The semiconductor device, wherein the first contact hole is formed in the interlayer insulating film on the fourth portion located on the element isolation region.

Item 11: In the semiconductor device according to Item 3,
A first wiring formed on the interlayer insulating film and electrically connected to the fourth portion of the second gate line through the first conductor portion embedded in the first contact hole; A semiconductor device.

Item 12: In the semiconductor device according to Item 11,
The semiconductor device, wherein the first wiring extends in a direction perpendicular to the first direction.

Item 13: In the semiconductor device according to Item 3,
The semiconductor device, wherein the first semiconductor region functions as the drain region, and the second semiconductor region functions as the source region.

Item 14: In the semiconductor device according to Item 13,
The second gate lines respectively connected to the second gate electrodes of the memory cells adjacent to each other through the second semiconductor region in a fourth direction intersecting the first direction are electrically connected. There is no semiconductor device.

Item 15: In the semiconductor device according to Item 14,
During a write operation to a selected memory cell of the plurality of memory cells, the second gate line connected to the second gate electrode of the selected memory cell, and the selected memory cell via the second semiconductor region A different voltage is supplied to the second gate line connected to the second gate electrode of the non-selected memory cell adjacent in the fourth direction.

Item 16: In the semiconductor device according to Item 13,
The second gate lines connected to the second gate electrodes of the memory cells adjacent to each other in the fourth direction via the second semiconductor region include the fourth portion, the first conductor portion, Are shifted in the first direction and are electrically connected to different wirings formed on the interlayer insulating film, respectively.

Item 17: In the semiconductor device according to Item 13,
A plurality of memory cell array formation regions each having a plurality of memory cells formed in an array;
An element isolation region made of an insulator is formed between the plurality of memory cell array formation regions,
The semiconductor device according to claim 1, wherein the first and second gate lines extend on the element isolation region between the memory cell array formation regions.

Item 18: In the semiconductor device according to Item 17,
A second contact hole is formed in the interlayer insulating film on the second semiconductor region in the outer peripheral portion of the memory cell array formation region, and a second conductor portion buried in the second contact hole, the second semiconductor region, Are electrically connected to each other.

Item 19: (a) a drain region and a source region formed in a semiconductor substrate;
(B) a first gate electrode and a second gate electrode formed on an upper portion of the semiconductor substrate between the drain region and the source region, the first gate electrode positioned on the drain region side; The second gate electrode located on the source region side and formed in a sidewall shape on the sidewall of the first gate electrode via a first insulating film;
(C) a first gate insulating film formed between the first gate electrode and the semiconductor substrate;
(D) a second gate insulating film formed between the second gate electrode and the semiconductor substrate and made of the same insulating film as the first insulating film, and having a charge storage portion therein A second gate insulating film;
Are arranged in a plurality of arrays,
(E) Of the plurality of memory cells,
A first gate line connecting the first gate electrodes of the memory cells arranged in a first direction, and comprising a first conductor layer in the same layer as the first gate electrode;
Connecting the second gate electrode of the memory cell adjacent to the first gate line via a second insulating film in the same layer as the first insulating film and arranged in the first direction; A second gate line comprising a second conductor layer in the same layer,
A plurality of
(F) an interlayer insulating film is formed on the semiconductor substrate so as to cover the first and second gate electrodes and the first and second gate lines;
(G) The first gate line includes a first portion extending in the first direction and one end connected to the first portion and extending in a second direction orthogonal to the first direction. A second portion present,
(H) the second gate line includes a third portion formed in a sidewall shape on the sidewalls of the first and second portions of the first gate line via the second insulating film; A fourth portion extending adjacent to the second portion of the first gate line through the second insulating film and extending in the first direction;
(I) A first contact hole is formed in the interlayer insulating film on the fourth portion of the second gate line, and the first conductor portion embedded in the first contact hole and the second gate line A semiconductor device, wherein the fourth portion is electrically connected.

Item 20: The semiconductor device according to Item 19,
The first conductor portion is formed on the interlayer insulating film so as to extend in the second direction and is embedded in the first contact hole in the fourth portion of the second gate line. A plurality of electrically connected first wires,
The second gate lines respectively connected to the second gate electrodes of the memory cells adjacent to each other in the second direction via the source region are not electrically connected to each other, and are different from each other. A semiconductor device which is electrically connected to one wiring.

Item 21: A semiconductor device having at least two memory cells connected to a common source line and arranged adjacent to each other so as to face the source line.
During the write operation of the memory cell, the value of the voltage applied to the word line of the selected memory cell to which writing is performed is applied to the word line of the unselected memory cell to which writing is not performed. A semiconductor device having a voltage value different from that of the semiconductor device.

Item 22: The semiconductor device according to Item 21,
A semiconductor device, wherein a value of a voltage applied to a word line of the selected memory cell is larger than a value of a voltage applied to a word line of the non-selected memory cell.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The performance of the semiconductor device can be improved.

  In addition, the manufacturing yield of the semiconductor device can be improved.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The structure of the semiconductor device of this embodiment will be described with reference to the drawings. FIG. 1 is a plan view of a principal part of a semiconductor device (nonvolatile semiconductor memory device) according to the present embodiment, and FIGS. 1 corresponds to FIG. 2, and the cross section taken along line BB in FIG. 1 corresponds to FIG. For easy understanding, FIG. 1 shows a polycrystalline silicon film 6 for forming the selection gate electrode 8 and the selection gate line 9, and a polycrystalline silicon film 12 for forming the memory gate electrode 13 and the memory gate line 14. The planar layout of the drain region 19, the source region 20, the contact hole 23, etc. is shown, and the other components are not shown. Further, in the plan view of FIG. 1, the side wall spacer 18 is not shown, and the lightly doped n-type semiconductor region 16 is included in the drain region 19 and the lightly doped n-type semiconductor region 17 is included in the source region 20. Show.

  The semiconductor device of the present embodiment shown in FIGS. 1 to 3 is a semiconductor device including a nonvolatile semiconductor memory device (nonvolatile memory, flash memory).

  For example, a memory cell of a nonvolatile memory is provided in a memory cell region (memory cell formation region, memory cell array formation region) 1A of a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. MISFETs (Metal Insulator Semiconductor Field Effect Transistors; MIS transistors, MIS field effect transistors) are formed.

  An element isolation region 2 for isolating elements is formed in the semiconductor substrate 1, and a p-type well 3 is formed in an active region isolated by the element isolation region 2. In the p-type well 3 of the memory cell region 1A, a memory cell 30 of a nonvolatile memory composed of a memory transistor and a selection transistor is formed. In each memory cell region 1A, a plurality of memory cells 30 are formed in an array, and each memory cell region 1A is electrically isolated from other regions by an element isolation region 2.

  The memory cell 30 of the flash memory (nonvolatile semiconductor memory device) formed in the memory cell region 1A is a split gate type cell using a MONOS film. As shown in FIG. 2, the memory cell 30 includes an insulating film 11 serving as a gate insulating film of a memory transistor, a memory gate electrode 13 (word line 13) made of a conductor such as n-type polycrystalline silicon, n Select gate electrode (control gate electrode) 8 made of a conductor such as type polycrystalline silicon, a gate insulating film 5 located under the select gate electrode 8, and a lightly doped n-type semiconductor region (lightly doped n-type) Impurity region) 16 and drain region (drain diffusion layer, high-concentration n-type semiconductor region) 19, and low-concentration n-type semiconductor region (low-concentration n-type impurity region) 17 and source region (source diffusion layer, high-concentration) in the source portion. n-type semiconductor region) 20. The memory gate electrode 13 of each memory cell 30 constitutes a word line of each memory cell. The select gate electrode 8 and the memory gate electrode 13 of each memory cell 30 are formed on the upper portion of the semiconductor substrate 1 between the drain region 19 and the source region 20, and the select gate electrode 8 is located on the drain region 19 side. The memory gate electrode 13 is located on the source region 20 side and is adjacent to the selection gate electrode 8 via the insulating film 11, and the gate insulating film 5 is interposed between the selection gate electrode 8 and the semiconductor substrate 1. An insulating film 11 that functions as a gate insulating film having a charge storage portion is interposed between the gate electrode 13 and the semiconductor substrate 1. The memory gate electrode 13 is formed in a sidewall shape on the sidewall of the select gate electrode 8 with the insulating film 11 interposed therebetween.

  Here, the MISFET formed of the memory gate electrode 13 is referred to as a memory transistor, and the MISFET formed of the selection gate electrode (control gate electrode) 8 is referred to as a selection transistor (control transistor).

  A plurality of memory cells 30 of the flash memory (nonvolatile semiconductor memory device) are arranged on the main surface of the semiconductor substrate 1 in an array. Of the plurality of memory cells 30 arranged in an array (matrix) in the X and Y directions of FIG. 1, in the X direction of FIG. 1 (the direction parallel to the main surface of the semiconductor substrate 1, the first direction). The select gate electrodes 8 of the memory cells 30 arranged side by side are (electrically) connected by a select gate line 9 made of the same conductive layer as the select gate electrode 8 (that is, the polycrystalline silicon film 6). The memory gate electrodes 13 of the memory cells 30 arranged in a row are connected (electrically) by a memory gate line 14 made of the same conductive layer as the memory gate electrode 13 (that is, the polycrystalline silicon film 12). The memory gate electrode 13 is adjacent to the selection gate line 9 via the insulating film 11, and the memory gate line 14 is adjacent to the selection gate line 9 via the insulating film 11. Note that the Y direction in FIG. 1 is a direction that intersects the X direction, and is preferably a direction that is orthogonal to the X direction.

  The gate insulating film 5 is made of an insulating film such as a silicon oxide film. The insulating film 11 is an insulating film (trap insulating film) having a charge storage portion therein, for example, a silicon nitride film (that is, a charge storage portion) for storing charges and a silicon oxide film positioned above and below the silicon nitride film And a laminated film (ONO (Oxide-Nitride-Oxide) film). The insulating film 11 is formed under the memory gate electrode 13, under the memory gate line 14, between the adjacent selection gate electrode 8 and the memory gate electrode 13, and between the adjacent selection gate line 9 and the memory gate line 14. Thus, the insulating film 11 under the memory gate electrode 13 becomes a gate insulating film (a gate insulating film having a charge storage portion inside) of the memory transistor.

  The low-concentration n-type semiconductor region 16, the low-concentration n-type semiconductor region 17, the drain region 19, and the source region 20 are semiconductor regions into which an n-type impurity (for example, phosphorus (P) or arsenic (As)) is introduced (silicon). And is formed in a p-type well 3 provided in the semiconductor substrate 1. The drain region 19 has a higher impurity concentration than the low concentration n-type semiconductor region 16 in the drain portion, and the source region 20 has a higher impurity concentration than the low concentration n-type semiconductor region 17 in the source portion. Among the plurality of memory cells 30, the memory cells 30 adjacent (adjacent) in the Y direction of FIG. 1 via the drain region 19 share the drain region 19, and also through the source region 20 of FIG. Memory cells 30 adjacent (adjacent) in the Y direction share the source region 20.

  Side wall spacers 18 made of an insulator such as silicon oxide are formed on the side walls of the select gate electrode 8 and the memory gate electrode 13. That is, the side wall of the memory gate electrode 13 opposite to the side adjacent to the selection gate electrode 8 via the insulating film 11 and the selection gate opposite to the side adjacent to the memory gate electrode 13 via the insulating film 11 Side wall spacers 18 are formed on the side walls of the electrode 8.

  The lightly doped n-type semiconductor region 16 in the drain portion is formed in a self-aligned manner with respect to the select gate electrode 8, and the drain region 19 is formed in a self-aligned manner with respect to the side wall spacer 18 on the side wall of the select gate electrode 8. Therefore, the low concentration n-type semiconductor region 16 is formed under the side wall spacer 18 on the side wall of the selection gate electrode 8, and the drain region 19 is formed outside the low concentration n-type semiconductor region 16. Therefore, the lightly doped n-type semiconductor region 16 is formed so as to be adjacent to the channel region of the selection transistor, the drain region 19 is in contact with the lightly doped n-type semiconductor region 16, and the lightly doped n-type semiconductor region 16 extends from the channel region of the selected transistor. It is formed so as to be separated from each other. The lightly doped n-type semiconductor region 17 in the source part is formed in a self-aligned manner with respect to the memory gate electrode 13, and the source region 20 is formed in a self-aligned manner with respect to the side wall spacer 18 on the side wall of the memory gate electrode 13. Therefore, the low concentration n-type semiconductor region 17 is formed under the sidewall spacer 18 on the sidewall of the memory gate electrode 13, and the source region 20 is formed outside the low concentration n-type semiconductor region 17. Accordingly, the lightly doped n-type semiconductor region 17 is formed adjacent to the channel region of the memory transistor, the source region 20 is in contact with the lightly doped n-type semiconductor region 17, and the lightly doped n-type semiconductor region 17 extends from the channel region of the memory transistor. It is formed so as to be separated from each other.

  The selection gate electrode 8 is formed by patterning a polycrystalline silicon film (polycrystalline silicon film doped or doped with n-type impurities) 6 formed on the semiconductor substrate 1, and this selection gate electrode 8 is formed. The patterned polycrystalline silicon film 6 extends in the X direction in FIG. 1 and connects the select gate electrodes 8 of the memory cells 30 to each other. Therefore, the patterned polycrystalline silicon film 6 forms the selection gate electrode 8 of each memory cell 30 and the selection gate line 9 connecting the selection gate electrodes 8 of the memory cells 30 arranged in the X direction in FIG. ing. That is, the selection gate electrode 8 and the selection gate line 9 are formed by the same conductive film (conductive layer) formed in the same process.

  The memory gate electrode 13 is formed by anisotropically etching a polycrystalline silicon film (polycrystalline silicon film doped or doped with n-type impurities) 12 formed on the semiconductor substrate 1 so as to cover the selection gate electrode 8. The polycrystalline silicon film 12 is left on the side wall 8 via the insulating film 11. The polycrystalline silicon film 12 forming the memory gate electrode 13 is formed on one side wall of the patterned polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selection gate line 9 via the insulating film 11. 1 extends in the X direction (lateral direction), and the memory gate electrodes 13 of the memory cells 30 are connected to each other. Accordingly, the polycrystalline silicon film 12 on the sidewalls of the patterned polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selection gate line 9 causes the memory gate electrode 13 of each memory cell 30 and the X direction in FIG. A memory gate line 14 is formed to connect the memory gate electrodes 13 of the memory cells 30 arranged side by side. The memory gate line 14 is formed in the word shunt region 1C that connects the memory cell regions 1A, and is arranged to apply a common potential to the memory cells 30 in each memory cell region 1A. Is connected. That is, the memory gate electrode 13 and the memory gate line 14 are formed by the same conductive film (conductive layer) formed in the same process. The polycrystalline silicon film 12 formed on one side wall of the select gate electrode 8 via the insulating film 11 becomes the memory gate electrode 13 and formed on the one side wall of the select gate line 9 via the insulating film 11. The polycrystalline silicon film 12 becomes the memory gate line 14.

  The selection transistor constituting the memory cell 30 and the selection gate electrode 8 of the memory transistor and the memory gate electrode 13 are adjacent to each other through the insulating film 11, and the selection gate line 9 and the memory gate line 14 are connected through the insulating film 11. Adjacent. Further, the channel region of the memory transistor is formed under the insulating film 11 under the memory gate electrode 13, and the channel region of the selection transistor is formed under the gate insulating film 5 under the selection gate electrode 8.

  In the channel formation region of the selection transistor under the gate insulating film 5 under the selection gate electrode 8, a p-type semiconductor region 4 for adjusting the threshold value of the selection transistor is formed as necessary. In the channel formation region of the memory transistor under the insulating film 11, a p-type semiconductor region 10 (or an n-type semiconductor region) for adjusting the threshold value of the memory transistor is formed as necessary.

  A metal silicide film 21 (for example, a cobalt silicide film) is formed on the upper surfaces (surfaces) of the selection gate electrode 8, the selection gate line 9, the memory gate electrode 13, the memory gate line 14, the drain region 19, and the source region 20 by a salicide process or the like. The metal silicide film 21 can reduce the diffusion resistance and the contact resistance.

  On the semiconductor substrate 1, an insulating film (interlayer insulating film) 22 is formed as an interlayer insulating film so as to cover the select gate electrode 8 and the memory gate electrode 13. The insulating film 22 is made of, for example, a laminated film of a relatively thin silicon nitride 22a and a relatively thick silicon oxide 22b thereon. The silicon nitride 22a can function as an etching stopper film when the contact hole 23 is formed. A contact hole (opening) 23 is formed in the insulating film 22, and a plug (conductor portion) 24 made of a conductive film mainly composed of a tungsten (W) film is formed in the contact hole 23, and the plug 24 is embedded. A wiring (first wiring layer) 25 is formed on the insulating film 22. The wiring 25 is, for example, an aluminum wiring made of a laminated film of a barrier conductor film 25a, an aluminum film 25b, and a barrier conductor film 25c. The barrier conductor films 25a and 25c are made of, for example, a titanium film, a titanium nitride film, or a laminated film thereof. The wiring 25 is not limited to the aluminum wiring and can be variously changed. For example, the wiring 25 can be a tungsten wiring or a copper wiring (for example, a buried copper wiring formed by a damascene method).

  Of the contact hole 23 and the plug 24 filling it, the contact hole 23a for connecting to the drain region 19 and the plug 24a filling it are formed above the drain region 19 of each memory cell 30 in the memory cell region 1A. A contact hole 23b for connecting to the source region 20 and a plug 24b filling the contact hole 23b are formed above the source region 20 of the source dummy region 1B at the end (outer periphery) of the memory cell region 1A. A contact hole 23c for connection and a plug 24c filling the contact hole 23c are formed above the selection gate line 9 in the word shunt region 1C between the memory cell regions 1A. The contact hole 23d for connecting to the memory gate line 14 and the contact hole 23d The plug 24d that fills the gap between the memory cell regions 1A It is formed over the memory gate lines of the word shunt region 1C. The element isolation region 2 is formed in the entire word shunt region 1C, and the selection gate line 9 and the memory gate line 14 are formed on the element isolation region 2 of the word shunt region 1C. The contact hole 23b for connecting to the source region 20 and the plug 24b filling the contact hole 23b are disposed in the source dummy region 1B at the end (outer peripheral portion) of the memory cell region 1A. It becomes a dummy region and becomes a countermeasure against crystal defects.

  Next, the selection gate line 9 and the memory gate line 14 will be described in more detail.

  The selection gate line 9 has a first portion 9a that extends in the X direction (first direction) in FIG. 1 and connects the selection gate electrodes 8 of the memory cells 30 arranged in the X direction, and one end of the selection gate line 9 is first. And a second portion 9b extending in the Y direction in FIG. 1 (a direction parallel to the main surface of the semiconductor substrate 1 and perpendicular to the X direction, a second direction). That is, the second portion 9b of the select gate line 9 extends in a direction intersecting with the extending direction of the first portion 9a, and more preferably orthogonal to the extending direction of the first portion 9a. It extends in the direction (perpendicular direction).

  The distance from the end of the second portion 9b extending in the Y direction to the select gate line 9 (first portion 9a) facing the source region and the memory gate line 14 is the second portion. It is shorter than the length of 9b in the Y direction. That is, the length of the second portion 9b in the Y direction is extended as much as possible in the design dimension. As a result, it is possible to easily secure a space in the Y direction of the contact portion 14a of the memory gate line formed extending from the second portion 9b in the X direction, and prevent the contact hole 23d from being missed. Can be made easier.

  Further, the second portion 9b of the selection gate line is formed so that the length in the Y direction is longer than the length in the X direction. As a result, the length of the contact portion 14a of the memory gate line extending in the X direction can be increased, thereby making it easy to prevent the contact hole 23d from being missed.

  The first portion 9a of the select gate line 9 has a relatively wide width (width in the Y direction) below the contact hole 23c, and the wide portion of the first portion 9a of the select gate line 9 is wide. (Third portion) Contact hole 23c is formed on 9c, and plug 24c is connected to wide portion 9c of first portion 9a of select gate line 9 at the bottom of contact hole 23c. The contact hole 23c is formed on the relatively wide portion 9c, and the plug 24c embedded in the contact hole 23c is connected to the wide portion 9c, thereby preventing the contact hole 23c from being disconnected. The selection gate line 9 can be reliably exposed at the bottom of the hole 24c, and the plug 24c can be reliably connected (electrically connected) to the selection gate line 9. Further, it is possible to prevent the memory gate line 14 from being exposed at the bottom of the contact hole 23c, and it is possible to prevent the selection gate line 9 and the memory gate line 14 from being short-circuited. As described above, the first portion 9a, the second portion 9b, and the wide portion 9c of the select gate line 9 are made of the patterned polycrystalline silicon film 6.

  A memory gate line 14 is formed on one side wall of the select gate line 9 via an insulating film 11. Therefore, the memory gate line 14 is formed on the side walls of the first portion 9 a, the second portion 9 b, and the wide portion 9 c of the selection gate line 9 via the insulating film 11. The memory gate line 14 is formed in a sidewall shape on one side wall of the select gate line 9 via an insulating film 11, and further, the second portion 9 b of the select gate line 9 is interposed via the insulating film 11. And a contact portion 14a extending in the X direction in FIG. The contact portion 14 a of the memory gate line 14 is also made of the polycrystalline silicon film 12 in the same manner as the sidewall portion of the memory gate line 14. Thus, the contact portion 14a of the memory gate line 14 extends in a direction intersecting the extending direction (Y direction) of the second portion 9b of the select gate line 9, and more preferably X in FIG. It extends in a direction parallel to the direction (a direction orthogonal to the extending direction (Y direction) of the second portion 9a). As described above, the element isolation region 2 is formed in the entire word shunt region 1C, and the selection gate line 9 and the memory gate line 14 are formed on the element isolation region 2, so that the contact portion 14a of the memory gate line 14a is selected. 1 extends from the second portion 9b of the gate line 9 to the element isolation region 2 in the X direction of FIG. An insulating film 11 is interposed between the contact portion 14 a of the memory gate line 14 and the second portion 9 b of the selection gate line 9.

  As described above, the polycrystalline silicon film 12 formed on the semiconductor substrate 1 so as to cover the patterned polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selection gate line 9 is anisotropically etched and patterned. By leaving the polycrystalline silicon film 12 on one side wall of the polycrystalline silicon film 6 via the insulating film 11, the memory gate electrode 13 and the memory gate line 14 made of the polycrystalline silicon film 12 can be formed. it can. In the anisotropic etching process of the polycrystalline silicon film 12, an etching mask layer (photoresist layer, not shown) is formed on the contact portion 14a, and the polycrystalline silicon film 12 under the etching mask layer remains. As a result, the contact portion 14a of the select gate line 9 is formed. Accordingly, the planar pattern shape of the etching mask layer (photoresist layer) used at this time corresponds to the planar pattern shape of the contact portion 14a. Therefore, the memory gate electrode 13, the memory gate line 14, and the contact portion 14a of the memory gate line 14 are formed in the same process and are made of the same conductor layer (here, the polycrystalline silicon film 12).

  A contact hole 23d is formed on the contact portion 14a of the memory gate line 14, and the plug 24d is electrically connected to the contact portion 14a of the memory gate line 14 at the bottom of the contact hole 23d. The planar pattern shape of the contact portion 14a is formed to have a predetermined size so as not to be missed in consideration of a shift when the contact hole 23d is opened. As a result, the contact hole 23d is prevented from being disconnected, the contact portion 14a of the memory gate line 14 is reliably exposed at the bottom of the contact hole 24d, and the plug 24d is securely connected (electrically connected) to the memory gate line 14. can do. Further, the contact portion 14 a of the memory gate line 14 extends from the second portion 9 b of the selection gate line 9 to the element isolation region 2, and a contact hole is formed on the contact portion 14 a located on the element isolation region 2. 23d is formed. For this reason, even if the contact hole 23d is missed, the contact portion 14a of the memory gate line 14 and the element isolation region 2 are exposed at the bottom of the contact hole 23d. It is possible to prevent the embedded plug 24d from being short-circuited with another conductive member. Even if overetching occurs in the contact hole 23d formation step, the element isolation region 2 is exposed at the bottom of the contact hole 23d, so that the plug 24d embedded in the contact hole 23d is short-circuited with another conductive member. Furthermore, the lower side surface of the plug 24d is in contact with the contact portion 14a of the memory gate line 14, thereby ensuring electrical connection between the plug 24d and the contact portion 14a of the memory gate line 14. Can do.

  Further, in this embodiment, each memory gate line 14 is provided with an independent contact portion 14a, and is adjacent (adjacent) via the source region 20 in the Y direction in FIG. The (two) memory gate lines 14 connected to the memory gate electrode 13 of the memory cell 30 facing each other are not electrically connected to each other.

  For example, in FIG. 2, the memory cell 30 a and the memory cell 30 b are adjacent to each other in the Y direction (adjacent or opposed) via the source region 20. In the present embodiment, (two lines) connected to the memory gate electrodes 13 of the memory cells 30 (for example, the memory cell 30a and the memory cell 30b in FIG. 2) adjacent to each other in the Y direction in FIG. The memory gate lines 14 are referred to as (two) memory gate lines 14 that are adjacent to each other in the Y direction in FIG.

  In the present embodiment, the (two) memory gate lines 14 adjacent in the Y direction in FIG. 1 via the source region 20 have the connection position of the contact portion 14a and the plug 24d in the word shunt region 1C as shown in FIG. They are displaced in the X direction and are electrically connected to different wirings 25 (25d) formed on the insulating film 22 and extending in the Y direction. That is, the memory gate line 14 is electrically connected to another memory gate line 14 other than the memory gate line 14 adjacent in the Y direction via the source region 20 via the plug 24d and the wiring 25 (25d). . In the example of FIG. 1, every other memory gate line 14 is electrically connected via a plug 24d and a wiring 25 (wiring 25d). Therefore, (two) memory gate lines 14 respectively connected to the memory gate electrodes 13 of the memory cells 30 adjacent in the Y direction in FIG. 1 via the source region 20, that is, in the Y direction via the source region 20. A desired voltage (different voltage) can be independently applied to the adjacent (two) memory gate lines 14 via the wiring 25 (25d), the plug 24d, and the contact portion 14a. For this reason, in the present embodiment, different voltages (potentials) may be independently applied to the memory gate electrodes 13 of the memory cells 30 (for example, the memory 30a and the memory cell 30b) adjacent in the Y direction via the source region 20. it can.

  Further, in the present embodiment, as will be described later, it is easy to secure a process margin, so that a metal silicide film 21 can be formed on the upper surfaces of the selection gate line 9 and the memory gate line 14, and disconnection of the metal silicide film 21 can be prevented. The resistance of the select gate line 9 and the memory gate line 14 can be reduced. For this reason, in the word shunt region 1C between the memory cell regions 1A, the number of plugs 24 connected to each select gate line 9 and each memory gate line 14 can be reduced to one, and the planar layout area of the semiconductor device is reduced. It becomes possible.

  FIG. 4 is a principal cross-sectional view showing a schematic cross-sectional structure of the memory cell 30 in the semiconductor device of the present embodiment. FIG. 5 is a table showing an example of voltage application conditions to each part of the selected memory cell at the time of “write”, “erase”, and “read” in the present embodiment. In the table of FIG. 5, the voltage Vd applied to the drain region 19 of the memory cell (selected memory cell) as shown in FIG. 4 and the selection gate at the time of “write”, “erase”, and “read” are shown. The voltage Vcg applied to the electrode 8 (selection gate line 9), the voltage Vmg applied to the memory gate electrode 13 (memory gate line 14), the voltage Vs applied to the source region 20, and the base voltage applied to the p-type well 3 Vb is described. In addition, what was shown in the table | surface of FIG. 5 is an example of the application conditions of a voltage, and is not limited to this, It can change variously as needed. In this embodiment, the injection of electrons into the silicon nitride film, which is a charge storage portion in the insulating film 11 of the memory transistor, is defined as “write”, and the injection of holes is defined as “erase”. . As shown in FIG. 4, the insulating film 11 is composed of a laminated film (ONO film) of a silicon oxide film 11a, a silicon nitride film 11b, and a silicon oxide film 11c, and the silicon nitride film 11b is used for accumulating charges. It functions as a charge storage unit.

  As the writing method, hot electron writing called a so-called source side injection method can be used. For example, a voltage as shown in the “write” column of FIG. 5 is applied to each part of the selected memory cell to be written, and electrons (electrons) are contained in the silicon nitride film 11b in the insulating film 11 of the selected memory cell. Inject. Hot electrons are generated in the channel region (between the source and drain) between the two gate electrodes (memory gate electrode 13 and select gate electrode 8), and the charge storage portion in the insulating film 11 below the memory gate electrode 13 Hot electrons are locally injected into the region on the select transistor side of the silicon nitride film 11b. The injected hot electrons (electrons) are captured by traps in the silicon nitride film 11b in the insulating film 11, and as a result, the threshold voltage of the memory transistor rises.

  As an erasing method, a BTBT (Band-To-Band Tunneling) hot hole injection erasing method can be used. That is, erasing is performed by injecting holes generated by BTBT (band-to-band tunneling phenomenon) into the charge storage portion (the silicon nitride film 11b in the insulating film 11). For example, a voltage as shown in the “erase” column of FIG. 5 is applied to each part of a selected memory cell to be erased, and a hole (hole) is generated by a BTBT (Band-To-Band Tunneling) phenomenon to generate an electric field. By accelerating, holes are injected into the silicon nitride film 11b in the insulating film 11 of the selected memory cell, thereby lowering the threshold voltage of the memory transistor.

  At the time of reading, for example, a voltage as shown in the “read” column in FIG. 5 is applied to each part of the selected memory cell to be read. The voltage Vmg applied to the memory gate electrode 13 at the time of reading is set to a value between the threshold voltage of the memory transistor in the written state and the threshold voltage in the erased state, so that the written state and the erased state are discriminated. can do.

  FIG. 6 is a principal part circuit diagram (equivalent circuit diagram) of the semiconductor device of the present embodiment. As shown in the circuit diagram of FIG. 6, a plurality of memory cells 30 are formed in the memory cell region 1A and arranged in an array, and the drain region 19 of each memory cell 30 extends in the Y direction. Connected to bit lines BL1 to BL6 (consisting of wiring 25), the source region (20) of each memory cell 30 is connected to source lines MSL1 and MSL2 (consisting of wiring 25) extending in the Y direction via a source dummy region 1B. Has been. The selection gate electrodes (8) of the memory cells 30 arranged in the X direction are electrically connected by selection gate lines CGL1 to CGL4 (corresponding to the selection gate line 9), and the memory gate electrodes (13) of the memory cells 30 arranged in the X direction. Are electrically connected by memory gate lines MGL1 to MGL4 (corresponding to the memory gate line 14). Memory gate lines MGL1 to MGL4 are connected to memory gate wirings MMG1 and MMG2 (consisting of wiring 25) extending in the Y direction through word shunt region 1C. Further, as shown in the circuit diagram of FIG. 6, the memory gate lines respectively connected to the memory gate electrodes (13) of the memory cells 30 adjacent to each other in the Y direction via the source region. In the example of FIG. The line MGL2 and the memory gate line MGL3 are not electrically connected to each other, one memory gate line MGL2 is connected to the memory gate wiring MMG1 in the word shunt region 1C, and the other memory gate line MGL3 is connected to the word shunt region 1C is connected to another memory gate wiring MMG2. Therefore, a predetermined (desired) voltage is independently applied to the memory gate lines adjacent to each other in the Y direction via the source region 20, in this case, the memory gate line MGL 2 and the memory gate line MGL 3 via the memory gate lines MMG 1 and MMG 2. Can be applied. Therefore, different voltages (potentials) can be applied to the memory gate lines (here, the memory gate lines MGL2 and MGL3) adjacent to each other in the Y direction via the source region 20 via the memory gate wirings MMG1 and MMG2. Therefore, a voltage can be independently applied to the memory gate electrode of the adjacent memory cell 30 through the source region 20, and different voltages can be applied to each memory cell.

  FIG. 7 is a plan view of an essential part of the semiconductor device according to the present embodiment. Of the wiring 25, the wiring 25d connected to the memory gate line 14 (that is, the wiring 25d corresponding to the memory gate wirings MMG1 and MMG2 in FIG. 6). ) Corresponds to what is further described in FIG. The wiring 25d is electrically connected to the contact portion 14a of the memory gate line 14 through the plug 24d filling the contact hole 23d in the word shunt region 1C. As shown in FIG. 7, the (two) memory gate lines 14 connected to the memory gate electrodes 13 of the memory cells 30 adjacent to each other via the source region 20 in the Y direction, that is, the source region 20 in the Y direction. The two (two) memory gate lines 14 that are adjacent to each other are not electrically connected to each other, one memory gate line 14 is connected to the wiring 25d in the word shunt region 1C, and the other memory gate line Reference numeral 14 denotes a word shunt region 1C connected to another wiring 25d. For this reason, a predetermined (desired) voltage can be independently applied to the (two) memory gate lines 14 adjacent via the source region 20 via the wiring 25d, and adjacent (two lines) via the source region 20. It is possible to apply different voltages (potentials) to the memory gate line 14 via the wiring 25d.

  FIG. 8 is a main part plan view of a semiconductor device (nonvolatile semiconductor memory device) of a first comparative example examined by the present inventors, and FIG. 9 is a main part sectional view thereof. A sectional view taken along line CC in FIG. 8 corresponds to FIG. FIG. 8 is a plan view corresponding to FIG.

  The semiconductor device of the first comparative example shown in FIGS. 8 and 9 is connected to the pattern shape of the selection gate line 9 and the memory gate line 14 and the memory gate line 14 with respect to the semiconductor device of the present embodiment. The position of the contact hole 23e and the plug 24e filling the contact hole 23e and the connection relationship between the wiring 25 connected to the plug 24e and the memory gate line 14 are different. In addition, since the cross-sectional structure of the memory cell of the semiconductor device of the first comparative example has the same structure as that of FIG. 2 of the first embodiment, description thereof is omitted here.

  In the semiconductor device of the first comparative example shown in FIGS. 8 and 9, the select gate line 9 is formed of the patterned polycrystalline silicon film 6 as in the present embodiment, and is in the X direction (FIG. 8). 1 corresponding to the X direction of 1) and connecting the select gate electrodes 8 of the memory cells 30 aligned in the X direction, and the first portion 9a are relatively wide. Unlike the present embodiment, the select gate line 9 does not have the second portion 9b.

  In the semiconductor device of the first comparative example shown in FIGS. 8 and 9, a memory gate line 14 made of a polycrystalline silicon film 12 is formed on one side wall of the select gate line 9 with an insulating film 11 interposed therebetween. The memory gate lines 14 adjacent to each other in the Y direction via the source region 20 are electrically connected to each other by a contact portion 14 b made of a part of the polycrystalline silicon film 12 constituting the memory gate line 14. The contact portion 14b extends from the selection gate line 9 to another selection gate line 9 in the Y direction in FIG. 8 (corresponding to the Y direction in FIG. 1), and the memory on the sidewall of the selection gate line 9 The gate line 14 is electrically connected to another memory gate line 14 on the side wall of the other selection gate line 9.

  The polycrystalline silicon film 12 formed on the semiconductor substrate 1 so as to cover the patterned polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selective gate line 9 is anisotropically etched to form the patterned polycrystalline silicon film. 6, the memory gate electrode 13 and the memory gate line 14 made of the polycrystalline silicon film 12 can be formed by leaving the polycrystalline silicon film 12 through the insulating film 11 on one side wall. In the anisotropic etching process of the crystalline silicon film 12, an etching mask layer (photoresist layer, not shown) is formed on the contact portion 14b, and the polycrystalline silicon film 12 under the etching mask layer is left. Thus, the contact portion 14b of the memory gate line 14 is formed. Therefore, the planar pattern shape of the etching mask layer (photoresist layer) used at this time corresponds to the planar pattern shape of the contact portion 14b.

  A contact hole 23e is formed on the contact portion 14b of the memory gate line 14, and a plug 24e is connected to the contact portion 14b of the memory gate line 14 at the bottom of the contact hole 23e. The plug 24 e is connected to the wiring 25, and the plurality of memory gate lines 14 are electrically connected via the plug 24 e and the wiring 25. As described above, in the first comparative example, two memory gate lines 14 (memory gate electrodes 13) adjacent in the Y direction via the source region 20 are taken out by the common contact portion 14b and the plug 24e connected thereto. (Draws).

  FIG. 10 is an explanatory diagram showing problems during the write operation in the semiconductor device of the first comparative example.

  In the semiconductor device of the first comparative example shown in FIG. 8 and FIG. 9, the selected memory cell that performs writing in the memory cell 30 with the voltage shown in the “write” column of FIG. Apply to each part. In the selected memory cell, 1 V is applied as Vd to the drain region 19, 1.5 V (Vdd) is applied as Vcg to the select gate electrode 8 (select gate line 9), and the memory gate electrode 13 (memory gate line 14) is applied. 12 V is applied as Vmg, and 6 V is applied to the source region 20 as Vs. Here, the source region 20 is common to the selected memory cell and the non-selected memory cell (memory cell in which writing is not performed) that is adjacent to (is adjacent to) the selected memory cell in the Y direction via the source region 20. The memory gate line 14 is electrically connected by a contact portion 14b. For this reason, since the source region 20 is common in the selected memory cell and the non-selected memory cell adjacent to the selected memory cell in the Y direction via the source region 20, the potential Vs of the source region 20 becomes the same potential. Since the memory gate line 14 is connected by the contact portion 14b, the potential Vmg of the memory gate electrode 13 (memory gate line 14) becomes the same potential. Therefore, when the write voltage is applied to the selected memory cell, the same voltage (Vs = 6V, Vmg) as the selected memory cell is applied to the source region 20 and the memory gate electrode 13 (memory gate line 14) of the unselected memory cell. = 12V) is applied.

  Therefore, in the non-selected memory cell adjacent to the selected memory cell to be written via the source region 20 in the Y direction, the channel current is applied by the potential Vcg of the selection gate electrode 8 (selection gate line 9) of the non-selected memory cell. Cut off and prevent disturb of unselected memory cells. However, in practice, as shown in FIG. 10 and above, in the non-selected memory cell adjacent to the selected memory cell to be written through the source region 20 in the Y direction, the source region 20 and the memory gate electrode 13 are selected. Since the same high voltage as that applied to the memory cell is applied, a junction leakage current is generated between the source and the substrate, and the hot electrons generated thereby are generated in the insulating film 11 (the silicon nitride film 11b in the non-selected memory cell). There is a possibility that the threshold voltage of the memory transistor of the non-selected memory cell will rise. As described above, the write disturb applied to the non-selected memory cells adjacent in the Y direction via the source region 20 becomes a problem for the write selected memory cell, which may reduce the performance of the semiconductor device.

  On the other hand, in the present embodiment, as described above, each memory cell is connected to the memory gate electrode 13 of the memory cell 30 adjacent (opposite, adjacent) in the Y direction via the source region 20 (between). The memory gate lines 14 that are connected to each other, that is, the memory gate lines 14 that are adjacent to each other in the Y direction via the source region 20, are not electrically connected to each other, and voltages (different voltages) are independently supplied via different wirings 25d and plugs 24d. ) Can be applied. Thus, in the present embodiment, the two memory gate lines 14 (memory gate electrodes 13) adjacent in the Y direction via the source region 20 are connected to the contact portions 14a of the memory gate lines 14 and the plugs 24d connected thereto. Are taken out independently (withdrawn). For this reason, the selected memory cell to be written in the memory cell 30 and a non-selected memory cell adjacent to the selected memory cell in the Y direction via the source region 20 are independently set to the memory gate electrode 13 ( A desired voltage can be applied (supplied). Therefore, different potentials are applied (supplied) to the memory gate electrode 13 of the selected memory cell to be written and the memory gate electrode 13 of the non-selected memory cell adjacent to the selected memory cell in the Y direction via the source region 20. )can do.

  For this reason, in this embodiment, even when a voltage as shown in the “write” column in FIG. 5 is applied to each part of the selected memory cell to be written in the write operation, In a non-selected memory cell adjacent in the Y direction via 20, the voltage value of the memory gate electrode 13 can be different from the voltage value of the memory gate electrode 13 of the selected memory. For example, the memory gate of the non-selected memory cell adjacent to the write selected memory cell in the Y direction via the source region 20 with respect to the voltage Vmg (12 V in the example of FIG. 5) of the memory gate electrode 13 of the write selected memory cell. The voltage Vmg of the electrode 13 can be lowered (for example, 0 V or 1.5 V as Vdd). That is, in the present embodiment, in at least two memory cells (for example, corresponding to the memory cells 30a and 30b) that are connected to a common source line and arranged adjacently to face the source line, the memory Of the two memory cells during the cell write operation, the value of the voltage applied to the word line (memory gate electrode 13) of the selected memory cell where writing is performed is the word of the unselected memory cell where writing is not performed. The voltage applied to the line (memory gate electrode 13) is different from the voltage applied to the word line (memory gate electrode 13). More preferably, the voltage applied to the word line (memory gate electrode 13) of the selected memory cell The voltage applied to the word line (memory gate electrode 13) is set larger than the value. As a result, a high voltage is applied to the memory gate electrode 13 of the write selected memory cell, and a high voltage is applied to the memory gate electrode 13 of the unselected memory cell adjacent to the write selected memory cell in the Y direction via the source region 20. It is possible to prevent voltage from being applied.

  Therefore, in this embodiment, unlike the first comparative example, even if a high voltage is applied to the memory gate electrode 13 of the selected memory cell to be written, the source region 20 is provided in the selected memory cell to be written. Since no high voltage is applied to the memory gate electrode 13 of the non-selected memory cell adjacent in the Y direction, electrons are taken into the insulating film 11 (the silicon nitride film 11b in the non-selected memory cell). This can prevent the threshold voltage of the memory transistor of the non-selected memory cell from increasing. As described above, in the present embodiment, it is possible to prevent the write disturb applied to the non-selected memory cell adjacent to the write selected memory cell in the Y direction via the source region 20.

  FIG. 11 is a graph showing the write disturb of unselected memory cells during the write operation to the selected memory cell. The horizontal axis in FIG. 11 corresponds to the time (arbitrary unit: arbitrary unit) after the voltage for writing is applied, and the vertical axis in FIG. 11 represents Y through the source region 20 with respect to the selected memory cell to be written. This corresponds to a threshold voltage (arbitrary unit) in unselected memory cells adjacent in the direction. In the graph of FIG. 11, in the case of the semiconductor device of the present embodiment as shown in FIGS. 1 to 3 (shown by a solid line as “this embodiment” in the graph of FIG. 11), FIG. The case of the first comparative example as shown in FIG. 9 (shown by the dotted line as “first comparative example” in the graph of FIG. 11) is shown.

  As shown in the graph of FIG. 11, in the first comparative example, in a non-selected memory cell adjacent to the selected memory cell to which writing is performed via the source region 20 in the Y direction, Since a high voltage is applied to the memory gate electrode 13, electrons (hot electrons) are taken into the insulating film 11 (the silicon nitride film 11b therein) of the non-selected memory cell, and the memory transistor of the non-selected memory cell is activated. The threshold voltage increases. On the other hand, in the present embodiment, a high voltage is not applied to the memory gate electrode 13 in a non-selected memory cell adjacent to the selected memory cell to be written through the source region 20 in the Y direction during the write operation. Electrons (hot electrons) are not taken into the insulating film 11 (the silicon nitride film 11b therein) of the non-selected memory cell, and the threshold voltage of the memory transistor of the non-selected memory cell hardly changes.

  Thus, in the present embodiment, the memory gate lines 14 (memory gate electrodes 13) adjacent in the Y direction are not electrically connected to each other via the source region 20 and are adjacent to each other via the source region 20. Since a desired potential (different potential) can be independently supplied to each of the two memory gate lines 14 (memory gate electrode 13), the source region 20 is supplied to the selected memory cell to be written during the write operation. In a non-selected memory cell adjacent to each other through the memory cell, a high voltage is prevented from being applied to the memory gate electrode 13, and a threshold voltage of the memory transistor of the non-selected memory cell is prevented from changing (raising). be able to. Thereby, the performance of the semiconductor device can be improved.

  FIG. 12 is a fragmentary plan view of a semiconductor device (nonvolatile semiconductor memory device) of a second comparative example examined by the present inventors, and FIG. 13 is a fragmentary sectional view thereof. A cross-sectional view taken along a line DD in FIG. 12 corresponds to FIG. FIG. 12 is a plan view corresponding to FIG. 1 and FIG.

  The semiconductor device of the second comparative example shown in FIGS. 12 and 13 is connected to the pattern shape of the select gate line 9 and the memory gate line 14 and the memory gate line 14 with respect to the semiconductor device of the present embodiment. The positions of the contact hole 23f and the plug 24f filling the contact hole 23f are different. Further, since the cross-sectional structure of the memory cell of the semiconductor device of the second comparative example has the same structure as that of FIG. 2 of the first embodiment, the description thereof is omitted here.

  In the semiconductor device of the second comparative example shown in FIGS. 12 and 13, the pattern shape of the polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selection gate line 9 is substantially the same as that of the first comparative example. is there. That is, the pattern shape of the select gate line 9 is substantially the same as that of the first comparative example, and the memory cells 30 extending in the X direction in FIG. 12 (corresponding to the X direction in FIG. 1) and arranged in the X direction. The first portion 9a for connecting the selection gate electrode 8 and the wide portion 9c having a relatively wide width in the first portion 9a are different from the present embodiment. The gate line 9 does not have the second portion 9b. In the semiconductor device of the second comparative example, the memory gate line 14 made of the polycrystalline silicon film 12 is formed on one side wall of the select gate line 9 with the insulating film 11 interposed therebetween. Unlike the first comparative example, the contact portion 14b as in the first comparative example is not provided, and the memory gate lines 14 adjacent in the Y direction are electrically connected via the source region 20. Absent.

  In the semiconductor device of the second comparative example shown in FIGS. 12 and 13, the memory gate line 14 extends from the selection gate line 9 adjacent to the memory gate line 14 via the insulating film 11 to the element isolation region 2. The contact portion 14c extends in the Y direction in FIG. 12 (corresponding to the Y direction in FIG. 1). The contact portion 14 c of the memory gate line 14 is not connected to the other memory gate line 14 adjacent to the memory gate line 14 in the Y direction via the source region 20. Therefore, each memory gate line 14 is provided with an independent contact portion 14c.

  Also in the semiconductor device of the second comparative example, the polycrystalline silicon film 12 formed so as to cover the patterned polycrystalline silicon film 6 constituting the selection gate electrode 8 and the selection gate line 9 on the semiconductor substrate 1 is anisotropic. The polycrystalline silicon film 12 is left on the one side wall of the patterned polycrystalline silicon film 6 through the insulating film 11, and the memory gate electrode 13 and the memory gate line made of the polycrystalline silicon film 12 are left. 14 can be formed, but in the anisotropic etching process of the polycrystalline silicon film 12, an etching mask layer (photoresist layer, not shown) is formed on the contact portion 14c, and the etching mask layer By leaving the lower polycrystalline silicon film 12, the contact portion 14 c of the select gate line 9 is formed. Therefore, the planar pattern shape of the etching mask layer (photoresist layer) used at this time corresponds to the planar pattern shape of the contact portion 14c.

  A contact hole 23f is formed on the contact portion 14c of the memory gate line 14 of the semiconductor device of the second comparative example, and the plug 24f is connected to the contact portion 14c of the memory gate line 14 at the bottom of the contact hole 23f. The plug 24f is connected to the wiring 25.

  In the semiconductor device of the second comparative example shown in FIGS. 12 and 13, the memory gate lines 14 adjacent in the Y direction via the source region 20 are electrically connected to each other as in the semiconductor device of the present embodiment. A desired voltage (different voltage) can be applied independently through different wiring 25 and plug 24f without being connected. Therefore, as in the present embodiment, even in the semiconductor device of the second comparative example, in a non-selected memory cell adjacent to the selected memory cell to be written in the Y direction via the source region 20 in the write operation, It is possible to prevent a high voltage from being applied to the memory gate electrode 13 and to prevent the threshold voltage of the memory transistor of the unselected memory cell from changing (raising).

  However, in the semiconductor device of the second comparative example shown in FIGS. 12 and 13, unlike the semiconductor device of the present embodiment, the selection gate line 9 does not have the second portion 9b, and the memory gate The contact portion 14c of the line 14 extends in the Y direction in FIG. Therefore, in the planar layout of the semiconductor device of the second comparative example shown in FIGS. 12 and 13, the alignment margin and the dimensional variation margin in the photolithography process are concentrated only in the Y direction in FIG. Therefore, it is difficult to secure a sufficient process margin, which may reduce the manufacturing yield of the semiconductor device. In addition, if a sufficient process margin is ensured to prevent a decrease in the manufacturing yield of the semiconductor device, the semiconductor device is increased in size (planar layout is increased in area). For example, in the semiconductor device of the second comparative example, a photolithography process for patterning the polycrystalline silicon film 6 to form the selection gate electrode 8 and the selection gate line 9, and anisotropically etching the polycrystalline silicon film 12 When the memory gate electrode 13 and the memory gate line 14 are formed, margins such as a photolithography process for forming the contact portion 14c and a photolithography process for forming the contact hole 23f are stacked only in the Y direction in FIG. End up.

  On the other hand, in the semiconductor device of the present embodiment shown in FIGS. 1 to 3, the select gate line 9 has a second portion 9b extending in the Y direction of FIG. The contact portion 14a extends from the second portion 9b of the select gate line 9 to the element isolation region 2 in the X direction in FIG.

  That is, in the present embodiment, the selection gate line 9 includes a first portion 9a that connects the selection gate electrodes 8 of the memory cells 30 that extend in the X direction and are arranged in the X direction in FIG. 1 portion 9a is connected to the first portion 9a extending in the X direction of FIG. 1 as well as the wide portion 9c in which the contact hole 23c is formed on the contact portion 23c. And a second portion 9b extending in the Y direction (direction perpendicular to the X direction) in FIG. Accordingly, the second portion 9b of the select gate line 9 has one end connected to the first portion 9a and in a direction (Y direction) substantially perpendicular to the extending direction (X direction) of the first portion 9a. It is extended. On the side walls of the first portion 9a, the second portion 9b, and the wide portion 9c of the selection gate line 9, a memory gate line 14 made of the polycrystalline silicon film 12 is formed. A contact portion 14a extending from the second portion 9b of the select gate line 9 to the element isolation region 2 in the X direction in FIG.

  In the present embodiment, the selection gate line 9 has a second portion 9b extending in the Y direction in FIG. 1, and the contact portion 14a of the memory gate line 14 is the second portion 9b of the selection gate line 9. Since it is formed so as to extend in the X direction in FIG. 1 from the top to the element isolation region 2, the alignment margin and the dimensional variation margin in the photolithography process are in the X direction and the Y direction in FIG. It is distributed and it is easy to secure a sufficient process margin. For this reason, the manufacturing yield of the semiconductor device can be improved. In addition, the reliability and performance of the semiconductor device can be improved. When the alignment margin and the dimensional variation margin in the photolithography process are concentrated only in the Y direction in FIG. 1 as in the second comparative example, the interval between the memory gate lines 13 adjacent to each other in the Y direction is increased. Although it is necessary to make it relatively large, in this embodiment, a margin for alignment and a margin for dimensional variation in the photolithography process can be distributed in the X direction and the Y direction in FIG. The distance between the lines 13 can be made relatively small, which is advantageous for reducing the area of the planar layout, and the semiconductor device can be downsized. In addition, the manufacturing yield of the semiconductor device can be improved. In the nonvolatile semiconductor memory device, there is a space in the X direction that is the word line direction, and there is no space in the Y direction that is the bit line direction. For this reason, rather than extending the contact portion 14c of the memory gate line 14 in the Y direction where there is no space as in the second comparative example, the X direction where there is a relatively large space as in the present embodiment. Further, by extending the contact portion 14a of the memory gate line 14, the manufacturing yield of the semiconductor device can be improved, and the layout area of the entire nonvolatile semiconductor memory device can be reduced.

  Next, a manufacturing process of the semiconductor device (nonvolatile semiconductor memory device) of the present embodiment will be described with reference to the drawings. 14 to 25 are fragmentary cross-sectional views of the semiconductor device (nonvolatile semiconductor memory device) of the present embodiment during the manufacturing process. 14 to 25, FIGS. 14, 16, 18, 20, 22, and 24 are sectional views of the region corresponding to FIG. 2, and FIGS. 15, 17, 19, and 21. 23 and 25 are sectional views of the region corresponding to FIG. 14 and 15 are cross-sectional views during the same manufacturing process, FIGS. 16 and 17 are cross-sectional views during the same manufacturing process, and FIGS. 18 and 19 are cross-sectional views during the same manufacturing process. 20 and FIG. 21 are cross-sectional views during the same manufacturing process, FIGS. 22 and 23 are cross-sectional views during the same manufacturing process, and FIGS. 24 and 25 are cross-sectional views during the same manufacturing process. FIG.

  First, as shown in FIGS. 14 and 15, a semiconductor substrate (semiconductor wafer) 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example, is prepared. Then, an element isolation region 2 made of an insulator is formed on the main surface of the semiconductor substrate 1 by, for example, an STI (Shallow Trench Isolation) method.

  Next, the p-type well 3 is formed by ion implantation of p-type impurities. The p-type well 3 is mainly formed in the memory cell region 1A, and the memory cell region 1A is electrically isolated from other regions by the element isolation region 2. Then, a p-type semiconductor region (p-type impurity region, channel region) 4 for adjusting the threshold value of the selection transistor is formed on the surface portion (surface layer portion) of the p-type well 3 by ion implantation or the like.

  Next, after cleaning the surface of the semiconductor substrate 1, an insulating film 5a for the gate insulating film of the selection transistor is formed on the surface of the p-type well 3 by using a thermal oxidation method or the like. Then, on the semiconductor substrate 1 including the insulating film 5a, a polycrystalline silicon film 6 serving as a selection gate electrode and a silicon oxide film 7 for protecting the selection gate electrode are sequentially deposited. The polycrystalline silicon film 6 is a polycrystalline silicon film into which an n-type impurity (for example, phosphorus (P) or the like) is introduced or doped, that is, an n-type polycrystalline silicon film.

  Next, using the photolithography technique and the dry etching technique, the silicon oxide film 7 and the polycrystalline silicon film 6 are patterned to form the selection gate electrode 8 and the selection gate line 9 of the selection transistor. The selection gate electrode 8 and the selection gate line 9 are made of a patterned polycrystalline silicon film 6, and the insulating film 5a under the selection gate electrode 8 becomes the gate insulating film 5 of the selection transistor. Therefore, the selection gate electrode 8 and the selection gate line 14 (first, second and third portions 14a, 14b, 14c) are formed in the same process, and are formed from the same conductor layer (polycrystalline silicon film 6). Become. When forming the pattern of the selection gate electrode 8 and the selection gate line 9, dry etching is stopped when the surface of the insulating film 5a is exposed so that unnecessary damage does not occur on the surface of the semiconductor substrate 1. .

  Next, as shown in FIGS. 16 and 17, a p-type semiconductor region for adjusting the threshold value is formed in the channel region of the memory transistor of the semiconductor substrate 1 (the p-type well 3) using an ion implantation method or the like. (P-type impurity region) 10 is formed.

  Next, the insulating film 5a left for protecting the semiconductor substrate 1 is removed using, for example, hydrofluoric acid, and then an insulating film 11 to be a gate insulating film of the memory transistor is formed. The insulating film 11 is made of, for example, a laminated film of a silicon oxide film (corresponding to the silicon oxide film 11a), a silicon nitride film (corresponding to the silicon nitride film 11b), and a silicon oxide film (corresponding to the silicon oxide film 11c). . The insulating film 11 is formed on the surface of the p-type well 3 and on the exposed surface (side wall) of the select gate electrode 8. Of the insulating film 11, a silicon oxide film can be formed by, for example, an oxidation process (thermal oxidation process), and a silicon nitride film can be formed by, for example, a CVD (Chemical Vapor Deposition) method. For example, after the lower silicon oxide film of the insulating film 11 is formed by thermal oxidation, the silicon nitride film of the insulating film 11 is deposited by the CVD method, and the upper silicon oxide film of the insulating film 11 is further CVD. It can be formed by the method and thermal oxidation. When removing the insulating film 5a, the silicon oxide film 7 on the select gate electrode 8 can be removed.

  Next, a polycrystalline silicon film 12 to be a memory gate electrode is deposited on the semiconductor substrate 1 including the insulating film 11. The polycrystalline silicon film 12 is a polycrystalline silicon film into which an n-type impurity (for example, phosphorus (P) or the like) is introduced or doped, that is, an n-type polycrystalline silicon film.

  Next, the polycrystalline silicon film 12 is removed by anisotropic etching until the upper surface of the insulating film 11 is exposed, and the polycrystalline silicon film is formed on the sidewalls of the selection gate electrode 8 and the selection gate line 9 via the insulating film 11. Thus, the memory gate electrode 13 and the memory gate line 14 made of the polycrystalline silicon film 12 are formed. The insulating film 11 under the memory gate electrode 13 becomes a gate insulating film of the memory transistor. In the anisotropic etching process of the polycrystalline silicon film 12, an etching mask layer (photoresist layer, not shown) is formed on the contact portion 14a, and the polycrystalline silicon film 12 under the etching mask layer remains. As a result, the contact portion 14a of the select gate line 9 is formed. Therefore, the memory gate electrode 13, the memory gate line 14, and the contact portion 14a of the memory gate line 14 are formed in the same process and are formed of the same conductive layer (polycrystalline silicon film 12). A sidewall spacer 15 made of the polycrystalline silicon film 12 is also formed on the sidewall of the selection gate electrode 8 on the side opposite to the memory gate electrode 13.

  Next, as shown in FIGS. 18 and 19, the sidewall spacer 15 is removed by using a photolithography technique and a dry etching technique. Then, the upper silicon oxide film and the lower silicon nitride film exposed in the insulating film 11 are removed using, for example, hydrofluoric acid and hot phosphoric acid.

  Next, as shown in FIGS. 20 and 21, ion implantation of low-concentration n-type impurities is performed to form a low-concentration n-type semiconductor region 16 in the drain portion and a low-concentration n-type semiconductor region 17 in the source portion. Form. The low-concentration n-type semiconductor region 16 in the drain part and the low-concentration n-type semiconductor region 17 in the source part are formed by the same ion implantation process. However, as another form, the photolithography technique and a resist film are used separately. It can also be formed by an ion implantation process.

  Next, after the exposed portion of the silicon oxide film under the insulating film 11 is removed with, for example, hydrofluoric acid, a silicon oxide film is deposited on the semiconductor substrate 1 and this silicon oxide film is anisotropically etched. Side wall spacers 18 made of an insulator such as silicon oxide are formed on the side walls of selection gate electrode 8, selection gate line 9, memory gate electrode 13 and memory gate line.

  Next, the drain region (n-type semiconductor region, n-type impurity region) 19 of the selection transistor and the source region (n-type semiconductor region, n-type impurity region) 20 of the memory transistor are formed by ion implantation of n-type impurities. To do. The drain region 19 has a higher impurity concentration than the low concentration n-type semiconductor region 16 in the drain portion, and the source region 20 has a higher impurity concentration than the low concentration n-type semiconductor region 17 in the source portion. In this manner, the memory cell 30 of the flash memory (nonvolatile semiconductor memory device) is formed.

Next, as shown in FIGS. 22 and 23, the surfaces of the selection gate electrode 8, the selection gate line 9, the memory gate electrode 13, the memory gate line 14, the drain region 19 and the source region 20 are exposed, for example, cobalt ( Co) film is deposited and heat-treated to form a metal silicide film on the top (surface) of the selection gate electrode 8, selection gate line 9, memory gate electrode 13, memory gate line 14, drain region 19 and source region 20, respectively. (Cobalt silicide film, eg, CoSi ₂ film) 21 is formed. Thereby, diffusion resistance and contact resistance can be reduced. Thereafter, the unreacted cobalt film is removed.

  Next, as shown in FIGS. 24 and 25, an insulating film (interlayer insulating film) 22 is formed on the semiconductor substrate 1. That is, the insulating film 22 is formed on the semiconductor substrate 1 including the metal silicide film 21 so as to cover the select gate electrode 8 and the memory gate electrode 13. The insulating film 22 is made of, for example, a laminated film of a relatively thin silicon nitride 22a and a relatively thick silicon oxide 22b thereon. The insulating film 22 can function as an interlayer insulating film. If necessary, the upper surface of the insulating film 22 can be planarized by a CMP (Chemical Mechanical Polishing) method or the like.

  Next, the contact hole 23 is formed in the insulating film 22 by dry etching the insulating film 22 using a photolithography technique and a dry etching technique.

  Next, plugs 24 (including plugs 24) made of tungsten (W) or the like are formed in the contact holes 23. The plug 24 is formed, for example, by forming a barrier film (for example, titanium nitride film) on the insulating film 22 including the inside of the contact hole 23 and then filling the contact hole 23 on the barrier film by a CVD method or the like. Then, an unnecessary tungsten film and barrier film on the insulating film 22 can be removed by CMP or an etch back method.

  Next, a wiring (first wiring layer) 25 is formed on the insulating film 22 in which the plug 24 is embedded. For example, a barrier conductor film 25a (for example, a titanium film or a titanium nitride film or a laminated film thereof), an aluminum film 25b and a barrier conductor film 25c (for example, a titanium film or a titanium nitride film or the like) are formed on the insulating film 22 in which the plug 24 is embedded. In this case, the wiring 25 can be formed by patterning using a photolithography technique and a dry etching technique. The wiring 25 is not limited to the aluminum wiring as described above and can be variously changed. For example, a tungsten wiring or a copper wiring (for example, a buried copper wiring formed by a damascene method) can be used. Thereafter, an interlayer insulating film, an upper wiring layer, and the like are further formed, but the description thereof is omitted here. The buried copper wiring formed by the damascene method can be used after the second layer wiring.

(Embodiment 2)
FIG. 26 is a fragmentary plan view of a semiconductor device (nonvolatile semiconductor memory device) according to another embodiment of the present invention. FIG. 26 is a plan view substantially corresponding to FIG. 1 of the first embodiment. Further, since the cross-sectional structure of the memory cell has the same structure as that of the first embodiment, description thereof is omitted here.

  In the semiconductor device according to the first embodiment, every other memory gate line 14 (polycrystalline silicon film 12) is electrically connected via the wiring 25 and the plug 23d, but this embodiment shown in FIG. In the semiconductor device of this form, every seven memory gate lines 14 (polycrystalline silicon film 12) are electrically connected via wiring 25 and plug 23d. That is, the other seven memory gate lines 14 exist between the memory gate lines 14 that are electrically connected to each other.

  In the semiconductor device shown in FIG. 26, the position of the second portion 9b of each select gate line 9 and the position of the contact portion 14a of the memory gate line 14 on the side wall of the select gate line 9 are shifted to each memory The position in the X direction of the contact hole 23d opened on the contact portion 14a of the gate line 14 is shifted. As a result, the connection position between the contact portion 14a of the memory gate line 14 adjacent to the Y direction and the plug 24d is shifted in the X direction, and the position in the X direction of the connection portion between the contact portion 14a of the memory gate line 14 and the plug 24d is determined. , N + 8th to n + 8mth (n, m: integer) memory gate lines 14, and the nth, n + 8th to n + 8mth (n, m: integer) memory gate lines 14 are connected in the Y direction. Are electrically connected by the same wiring 25 extending to the bottom. The position of the second portion 9b of each select gate line 9 and the position of the contact portion 14a of the memory gate line 14 on the side wall of the select gate line 9 are shifted so as to be on the contact portion 14a of each memory gate line 14. By shifting the position of the opening contact hole 23d in the X direction, each memory gate line 14 can be electrically connected to a desired wiring 25 extending in the Y direction.

  Note that the memory gate lines 14 are connected to the wiring 25 every other line in the first embodiment and every seven lines in the present embodiment, but the memory gate lines 14 are connected to the wiring 25 every other line as necessary. Can be connected to.

  Also in the present embodiment, substantially the same effect as in the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, although a split gate type memory cell using MONOS has been described in this embodiment, it can be applied to a one-transistor type NOR flash memory or the like.

  The present invention is suitable for application to a semiconductor device including a nonvolatile semiconductor memory device.

1 is a plan view of a principal part of a semiconductor device according to a first embodiment of the present invention. It is principal part sectional drawing of the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing which shows the typical cross-section of a memory cell. 6 is a table showing an example of voltage application conditions to each part of a selected memory cell during “write”, “erase”, and “read”. 1 is a main part circuit diagram (equivalent circuit diagram) of a semiconductor device according to a first embodiment of the present invention; 1 is a plan view of a principal part of a semiconductor device according to a first embodiment of the present invention. It is a principal part top view of the semiconductor device of the 1st comparative example. It is principal part sectional drawing of the semiconductor device of a 1st comparative example. It is explanatory drawing which shows the problem at the time of write-in operation | movement in the semiconductor device of a 1st comparative example. It is a graph which shows the write disturb of the non-selected memory cell at the time of the write operation to the selected memory cell. It is a principal part top view of the semiconductor device of the 2nd comparative example. It is principal part sectional drawing of the semiconductor device of the 2nd comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device of Embodiment 1 of this invention. FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 17; FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; FIG. 20 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 19; FIG. 21 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 20; FIG. 22 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 21; FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; It is a principal part top view of the semiconductor device of Embodiment 2 of this invention.

Explanation of symbols

1 semiconductor substrate 1A memory cell region 1B source dummy region 1C word shunt region 2 element isolation region 3 p-type well 4 p-type semiconductor region 5 gate insulating film 5a insulating film 6 polycrystalline silicon film 7 silicon oxide film 8 selection gate electrode 9 selection Gate line 9a First portion 9b Second portion 9c Wide portion 10 P-type semiconductor region 11 Insulating film 12 Polycrystalline silicon film 13 Memory gate electrode 14 Memory gate line 14a Contact portion 14b Contact portion 14c Contact portion 15 Side wall spacer 16 Low Concentration n-type semiconductor region 17 Low-concentration n-type semiconductor region 18 Side wall spacer 19 Drain region 20 Source region 21 Metal silicide film 22 Insulating film 22a Silicon nitride 22b Silicon oxide 23 Contact hole 23a Contact hole 23b Contact hole 23c Contact hole 23e contact hole 23e contact hole 23f contact hole 24 plug 24d plug 24e plug 24f plug 25 wiring 25d wiring 30 memory cells BL1 to BL6 bit lines CGL1 to CGL4 selection gate lines MGL1 to MGL4 memory gate lines MMG1, MMG2 memory gate wiring MSL1, MSL2 source line

Claims (12)

A semiconductor device having a memory array including a plurality of nonvolatile memory cells formed on a semiconductor substrate,
The plurality of first nonvolatile memory cells are:
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first charge storage layer formed on a side surface of the first gate electrode and the semiconductor substrate;
A second gate electrode formed on the side surface of the first gate electrode on the first charge storage layer via the first charge storage layer;
The plurality of second nonvolatile memory cells are disposed adjacent to the first nonvolatile memory cell in the first direction,
A second gate insulating film formed on the semiconductor substrate;
A third gate electrode formed on the second gate insulating film;
A side surface of the second gate electrode and a second charge storage layer formed on the semiconductor substrate;
A fourth gate electrode formed on the side surface of the third gate electrode on the second charge storage layer via the second charge storage layer;
The plurality of first nonvolatile memory cells and the plurality of second nonvolatile memory cells are formed such that the second gate electrode and the fourth gate electrode are adjacent to each other.
Since the first gate electrode and the second gate electrode extend in a second direction intersecting the first direction, the plurality of first nonvolatile memory cells are electrically connected to each other in the second state. Line up in the direction,
When the third gate electrode and the fourth gate electrode extend in the second direction, the plurality of second nonvolatile memory cells are arranged in the second direction in an electrically connected state,
The second gate electrode includes a first contact portion extending and terminating in the first direction toward the fourth gate electrode,
The fourth gate electrode includes a second contact portion that extends and terminates toward the second gate electrode in the first direction,
The first and second contact portions are formed to be shifted in the second direction,
The semiconductor device, wherein the second gate electrode and the fourth gate electrode are not connected by a conductive film in the same layer as the second gate electrode and the fourth gate electrode. A semiconductor device having a memory array including a plurality of nonvolatile memory cells formed on a semiconductor substrate,
The plurality of first nonvolatile memory cells are:
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first charge storage layer formed on a side surface of the first gate electrode and the semiconductor substrate;
A second gate electrode formed on the side surface of the first gate electrode on the first charge storage layer via the first charge storage layer;
The plurality of second nonvolatile memory cells are disposed adjacent to the first nonvolatile memory cell in the first direction,
A second gate insulating film formed on the semiconductor substrate;
A third gate electrode formed on the second gate insulating film;
A side surface of the second gate electrode and a second charge storage layer formed on the semiconductor substrate;
A fourth gate electrode formed on the side surface of the third gate electrode on the second charge storage layer via the second charge storage layer;
The plurality of first nonvolatile memory cells and the plurality of second nonvolatile memory cells are formed such that the second gate electrode and the fourth gate electrode are adjacent to each other.
Since the first gate electrode and the second gate electrode extend in a second direction intersecting the first direction, the plurality of first nonvolatile memory cells are electrically connected to each other in the second state. Line up in the direction,
When the third gate electrode and the fourth gate electrode extend in the second direction, the plurality of second nonvolatile memory cells are arranged in the second direction in an electrically connected state,
The second gate electrode includes a first contact portion extending and terminating in the first direction toward the fourth gate electrode,
The fourth gate electrode includes a second contact portion that extends and terminates toward the second gate electrode in the first direction,
The first and second contact portions are formed to be shifted in the second direction,
A first insulating film is formed on the memory array,
A first plug connected to the first contact portion and a second plug connected to the second contact portion are formed in the first insulating film,
A first wiring capable of applying a first voltage to the second gate electrode through the first plug is formed on the first plug,
A second wiring capable of applying a second voltage different from the first voltage to the fourth gate electrode through the second plug is formed on the second plug,
The semiconductor device according to claim 1, wherein the first and second wirings are formed to be shifted in the second direction and extend in the first direction . The semiconductor device according to claim 1 ,
further,
A first insulating film formed on the memory array;
A first plug connected to the first contact portion formed in the first insulating film and a second plug connected to the second contact portion ;
Semiconductor device characterized that you have a second wiring connected to the first wiring and the second plug connected to the first plug. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the first and second wirings are formed to be shifted in the second direction and extend in the first direction. The semiconductor device according to any one of claims 1 to 4,
Furthermore, it has an element isolation region formed in the semiconductor substrate,
The semiconductor device according to claim 1, wherein the first and second contact portions are disposed on the element isolation region. The semiconductor device according to claim 5,
The device isolation region is constituted by a second insulating film embedded in a groove formed in the semiconductor substrate. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device, wherein the second and fourth gate electrodes are formed in a sidewall shape. In the semiconductor device according to claim 1,
A silicide film is formed on the first gate electrode, the second gate electrode, the third gate electrode, the fourth gate electrode, the first contact portion, and the second contact portion. A semiconductor device characterized by the above. The semiconductor device according to claim 8,
The semiconductor device, wherein the silicide film is a cobalt silicide film. The semiconductor device according to any one of claims 1 to 9,
The semiconductor device, wherein the first and second charge storage layers include a silicon nitride film. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the second direction is a direction orthogonal to the first direction. The semiconductor device according to claim 4,
The first and second nonvolatile memory cells share the source region by being adjacent via a source region formed in the semiconductor substrate,
The source region extends in the second direction;
The first nonvolatile memory cell has a first drain region formed in the semiconductor substrate,
The first drain region is formed on the opposite side of the source region via the first gate electrode and the second gate electrode in the first direction,
The second nonvolatile memory cell has a second drain region formed in the semiconductor substrate,
The second drain region is formed on the opposite side of the source region via the third gate electrode and the fourth gate electrode in the first direction,
The first drain region is connected to a third plug formed in the first insulating film,
The second drain region is connected to a fourth plug formed in the first insulating film,
The first drain region and the second drain region are formed on the first insulating film via the third plug and the fourth plug, and are formed by a third wiring extending in the first direction. A semiconductor device which is electrically connected.

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