CN109616514A - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN109616514A CN109616514A CN201811532604.5A CN201811532604A CN109616514A CN 109616514 A CN109616514 A CN 109616514A CN 201811532604 A CN201811532604 A CN 201811532604A CN 109616514 A CN109616514 A CN 109616514A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 48
- 238000002955 isolation Methods 0.000 claims description 26
- 239000000377 silicon dioxide Substances 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 abstract description 20
- 230000015556 catabolic process Effects 0.000 abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 238000000059 patterning Methods 0.000 abstract description 4
- 101100398801 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) LDS2 gene Proteins 0.000 description 23
- 150000002500 ions Chemical class 0.000 description 18
- 235000012239 silicon dioxide Nutrition 0.000 description 17
- 101000658644 Homo sapiens Tetratricopeptide repeat protein 21A Proteins 0.000 description 13
- 102100034913 Tetratricopeptide repeat protein 21A Human genes 0.000 description 13
- 238000000034 method Methods 0.000 description 9
- 102100025292 Stress-induced-phosphoprotein 1 Human genes 0.000 description 7
- 101710140918 Stress-induced-phosphoprotein 1 Proteins 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses a kind of semiconductor devices and preparation method thereof, in technical solution of the present invention, gate dielectric layer and gate surface are covered with first medium layer, can the first medium layer based on grid and its surface, formed in the substrate and lightly doped drain and source region be lightly doped, avoided that source region is lightly doped and lightly doped drain is diffused into below grid, it can increase and the distance between source region and lightly doped drain is lightly doped, breakdown problem is prevented punch-through, parasitic capacitance is reduced, improves operating frequency.It can first medium layer and second dielectric layer based on the grid and its side wall; source region and drain region are formed in the substrate; when forming patterned second dielectric layer, due to the protection of first medium layer, caused over etching problem when can be to avoid patterning second dielectric layer.And technical solution of the present invention only needs two layers of dielectric layer, and manufacture craft is simple, low manufacture cost.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology fields, more specifically, being related to a kind of semiconductor devices and its system
Make method.
Background technique
With the continuous development of science and technology, more and more electronic equipments are widely used in daily life
And in work, huge convenience is brought for daily life and work, it is indispensable to become current people
Important tool.
Semiconductor devices is the main element that electronic equipment realizes various functional integrated circuits.With integrated circuit integrated level
Continuous improvement, the size of semiconductor devices is smaller and smaller, in this way, source region and lightly doped drain is lightly doped in semiconductor devices
Distance becomes closer to, so that semiconductor devices is easy to happen punch-through breakdown (punch-through) problem, causes to leak electricity.And
And due to being lightly doped source region and lightly doped drain can be diffused into below grid, increase the parasitic capacitance between grid and source region with
And the parasitic capacitance between drain region, reduce the operating frequency of semiconductor devices.
To solve the above-mentioned problems, the prior art is general first forms the first spacer structure in the side wall of grid, as formation
The exposure mask of source region and lightly doped drain is lightly doped, this way it is possible to avoid source region is lightly doped and is lightly doped by ion implanting formation
When drain region, source region is lightly doped and lightly doped drain is diffused into below grid, meanwhile, it can increase and source region is lightly doped and is lightly doped
The distance between drain region prevents punch-through breakdown problem, reduces parasitic capacitance, improves operating frequency；Then again in the first interval knot
Structure surface forms the second spacer structure, as the exposure mask for forming source region and drain region, forms source region and drain region.
Although the above-mentioned prior art can prevent punch-through breakdown problem, operating frequency is improved, over etching can occur and ask
Topic, and cost of manufacture is higher.
Summary of the invention
In view of this, technical solution of the present invention provides a kind of semiconductor devices and preparation method thereof, avoid wearing in realization
While punchthrough breakdown problem and raising operating frequency, over etching problem, and low manufacture cost are avoided.
To achieve the goals above, the invention provides the following technical scheme:
A kind of production method of semiconductor devices, the production method include:
A substrate is provided, the substrate has first surface, and the first surface has gate dielectric layer, the gate dielectric layer
There is grid away from a side surface of the substrate；
First medium layer is formed, the first medium layer covers the gate dielectric layer and the grid；
First medium layer based on the grid and its side wall carries out first time ion implanting towards the first surface,
It is formed in the substrate and source region and lightly doped drain is lightly doped；
Form patterned second dielectric layer, the patterned second dielectric layer covering is located at the of the gate lateral wall
One dielectric layer exposes the first medium layer of other parts；
First medium layer and second dielectric layer based on the grid and its side wall carry out second towards the first surface
Secondary ion injection, forms source region and drain region in the substrate.
Preferably, in above-mentioned production method, one substrate of the offer includes:
Gate dielectric layer is formed in the first surface of substrate；
Shallow trench is formed on the gate dielectric layer, the shallow trench extends in the substrate；
The filled media material in the shallow trench forms fleet plough groove isolation structure；
Grid is formed away from a side surface of the substrate in the gate dielectric layer；
Wherein, the first medium layer covers the surface of the fleet plough groove isolation structure.
Preferably, in above-mentioned production method, the patterned second dielectric layer of formation includes:
Non-patterned second dielectric layer is formed, the second dielectric layer covers the first medium layer；
The second dielectric layer is patterned, retains the part that the second dielectric layer is located at the gate lateral wall, removes it
The second dielectric layer of his part.
Preferably, in above-mentioned production method, the first medium layer is silica.
Preferably, in above-mentioned production method, the second dielectric layer is silicon nitride.
Preferably, in above-mentioned production method, on the direction for being parallel to the first surface, the grid is located at described
It lightly doped drain and described is lightly doped between source region；
On the direction perpendicular to the first surface, source region is lightly doped with described with the lightly doped drain in the grid
It does not overlap.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes:
Substrate, the substrate have first surface；
Cover the gate dielectric layer of the first surface；
The grid that the gate dielectric layer deviates from the one side of substrate surface is set；
Cover the first medium layer of the grid and the gate dielectric layer；
First medium layer based on the grid and its side wall is formed in source region is lightly doped and gently mixes in the substrate
Miscellaneous drain region；
Covering is located at the second dielectric layer of the first medium layer of the gate lateral wall, and the second dielectric layer exposes other portions
The first medium layer divided；
First medium layer and second dielectric layer based on the grid and its side wall, be formed in the source region in the substrate with
And drain region.
Preferably, in above-mentioned semiconductor device, the first medium layer is silica.
Preferably, in above-mentioned semiconductor device, the second dielectric layer is silicon nitride.
Preferably, in above-mentioned semiconductor device, on the direction for being parallel to the first surface, the grid is located at institute
It states lightly doped drain and described is lightly doped between source region；
On the direction perpendicular to the first surface, source region is lightly doped with described with the lightly doped drain in the grid
It does not overlap.
As can be seen from the above description, in semiconductor devices that technical solution of the present invention provides and preparation method thereof, gate medium
Layer and gate surface be covered with first medium layer, can the first medium layer based on grid and its surface, in the substrate
It forms lightly doped drain and source region is lightly doped, avoid that source region is lightly doped and lightly doped drain is diffused into below grid, Ke Yizeng
The distance between source region and lightly doped drain is lightly doped greatly, prevents punch-through breakdown problem, reduces parasitic capacitance, improves operation frequency
Rate.Can first medium layer and second dielectric layer based on the grid and its side wall, source region and leakage are formed in the substrate
Area, when forming patterned second dielectric layer, due to the protection of first medium layer, when can be to avoid patterning second dielectric layer
Caused over etching problem.And technical solution of the present invention only needs two layers of dielectric layer, and manufacture craft is simple, low manufacture cost.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1-Fig. 7 is a kind of process flow chart of the production method of semiconductor devices；
Fig. 8-Figure 13 is a kind of process flow chart of the production method of semiconductor devices provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
With reference to Fig. 1-Fig. 7, Fig. 1-Fig. 7 is a kind of process flow chart of the production method of semiconductor devices, the production method
Include:
Firstly, providing a substrate 11 as shown in Figure 1, silicon nitride layer 14 is formed on substrate 11.The substrate 11 has first
Surface, first surface are covered with gate dielectric layer 12, and 12 surface of gate dielectric layer has grid G 1, and 1 surface of grid G has silica
Layer 13.General grid G 1 is silicon materials, therefore can form silicon dioxide layer by 1 surface of thermal oxidation technology direct oxidation grid G
13.Wherein, silicon nitride layer 14 covers gate dielectric layer 12 and silicon dioxide layer 13.Gate dielectric layer is formed with shallow trench in 12 surface
Isolation structure STI1, fleet plough groove isolation structure STI1 run through gate dielectric layer 12, and extend in substrate 11.Gate dielectric layer 12 exposes
Fleet plough groove isolation structure STI1.Silicon nitride layer 14 covers fleet plough groove isolation structure STI1.
Then, as shown in Fig. 2, etch nitride silicon layer 14, removes 12 surface of gate dielectric layer, fleet plough groove isolation structure STI1 table
The silicon nitride layer 14 of 1 top surface of face and grid G, while removing the silicon dioxide layer 13 of 1 top surface of grid G.The table of silicon nitride material
Face stress is larger, and adhesive force is poor, is easy to fall off, it is not easy to directly grow on 1 surface of the grid G of silicon materials, pass through titanium dioxide
Silicon layer 13 can guarantee the attachment stability of silicon nitride layer 14.
Again as shown in figure 3, source region LDS1 and lightly doped drain LDD1 is lightly doped by the formation of first time ion implanting, by
There is silicon dioxide layer 13 and silicon nitride layer 14 in 1 side wall of grid G, it can be to avoid lightly-doped source area LDS1 and lightly doped drain
Area LDD1 is diffused into 1 lower section of grid G, can increase and spacing between source region LDS1 and lightly doped drain LDD1 is lightly doped, avoid
Punch-through breakdown problem reduces parasitic capacitance, improves operating frequency.It is predictable, due to thermal diffusion, infused by the first secondary ion
After entering, source region LDS1 and lightly doped drain LDD1 is lightly doped can spread to the direction close to grid G 1, so that being lightly doped
Source region LDS1 is flushed close to the boundary of grid G 1 with the boundary of grid G 1, boundary and grid of the lightly doped drain LDD1 close to grid G 1
The boundary of pole G1 flushes.
Again as shown in figure 4, formed silicon dioxide layer 15, silicon dioxide layer 15 cover the top surface grid G1, silicon dioxide layer 13,
Silicon nitride layer 14, fleet plough groove isolation structure STI1 and gate dielectric layer 12.
Again as shown in figure 5, forming silicon nitride layer 16, silicon nitride layer 16 covers silicon dioxide layer 15.
Again as shown in fig. 6, etch nitride silicon layer 16 and silicon dioxide layer 15, remove the silicon nitride layer 16 of 1 top surface of grid G
And silicon dioxide layer 15, and remove 16 He of silicon nitride layer on 12 surface of gate dielectric layer and the surface fleet plough groove isolation structure STI1
Silicon dioxide layer 15 retains silicon nitride layer 16 and silicon dioxide layer 15 on 1 side wall of grid G.
Finally, as shown in fig. 7, forming source region S and drain region D by second of ion implanting.
As can be seen from the above description, production method shown in Fig. 1-Fig. 7 needs the first spacer structure (silicon dioxide layer 13 and nitrogen
SiClx layer 14) exposure mask as first time ion implanting, need the second spacer structure (silicon nitride layer 16 and silicon dioxide layer
15) exposure mask as second of ion implanting, but also silicon dioxide layer 13 is needed to guarantee 14 adhesive force of silicon nitride layer, Gong Jixu
Form four-level membrane structure (silicon dioxide layer 13, silicon nitride layer 14, silicon dioxide layer 15 and silicon nitride layer 16), Er Qiexu
It wants twice etching technique (as shown in Figure 2 and Figure 6), production process is complicated, and cost of manufacture is high.And during twice etching,
It needs to expose grid G 1 by etching and fleet plough groove isolation structure STI, twice etching process inevitably will appear quarter
Erosion problem causes grid G 1 and fleet plough groove isolation structure STI to cause to damage.
To solve the above-mentioned problems, the embodiment of the invention provides a kind of semiconductor devices and preparation method thereof, the present invention
In embodiment technical solution, gate dielectric layer and gate surface are covered with first medium layer, can be based on grid and its surface
First medium layer forms lightly doped drain in the substrate and source region is lightly doped, avoids that source region and lightly doped drain is lightly doped
Area is diffused into below grid, can increase and the distance between source region and lightly doped drain is lightly doped, prevent punch-through breakdown problem, is dropped
Low parasitic capacitance improves operating frequency.Can first medium layer and second dielectric layer based on the grid and its side wall, in institute
State formation source region and drain region in substrate, due to the protection of first medium layer, can keep away when forming patterned second dielectric layer
Exempt to pattern caused over etching problem when second dielectric layer.And technical solution of the present invention only needs two layers of dielectric layer and primary
Etching technics, manufacture craft is simple, low manufacture cost.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
With reference to Fig. 8-Figure 13, Fig. 8-Figure 13 is a kind of work of the production method of semiconductor devices provided in an embodiment of the present invention
Skill flow chart, the production method include:
Step S11: as shown in figure 8, providing a substrate 21.
The substrate 21 has first surface, and the first surface has gate dielectric layer 22, and the gate dielectric layer 22 deviates from
One side surface of the substrate 21 has grid G 2.
In the step, the substrate that provides includes: firstly, the first surface in substrate 21 forms gate dielectric layer 22；So
Afterwards, shallow trench is formed on the gate dielectric layer 22, the shallow trench extends in the substrate 21；Again in the shallow trench
Filled media material forms fleet plough groove isolation structure STI2；Finally, deviating from the side table of the substrate in the gate dielectric layer 22
Face forms grid G 2.Shown grid G 2 can be prepared for silicon materials, such as polysilicon.Wherein, subsequent first Jie for crossing step and being formed
Matter layer 23 covers the surface of the fleet plough groove isolation structure STI2.
Step S12: as shown in figure 9, forming first medium layer 23, the first medium layer 23 covers the gate dielectric layer 22
And the grid G 2.The first medium layer 23 covers the fleet plough groove isolation structure STI2.
Wherein, the first medium layer 23 is silica.The first medium layer 23 can be formed by depositing operation.
The first medium layer 23 positioned at 2 side wall of grid G can be to avoid forming lightly doped drain LDD2 and light in subsequent step
Doping source region LDS2 is diffused into 2 lower section of grid G, increases lightly doped drain LDD2 and source region LDS2 distance is lightly doped, prevent punch-through
Breakdown problem reduces parasitic capacitance, improves operating frequency.The thickness of the first medium layer 23 can be less than the gate dielectric layer
22 thickness, so that, using relatively small implantation dosage, can be formed and be set when subsequent step carries out first time ion implanting
The lightly doped drain LDD2 of depthkeeping degree and source region LDS2 is lightly doped.Optionally, the thickness range of the first medium layer 23 is
5nm-20nm, it is preferred that can be 10nm.Thickness using above-mentioned first medium layer 23 is moderate, on the one hand, can to avoid due to
23 thickness of first medium layer is excessive to cause thickness process to need biggish Implantation Energy, on the other hand, can also avoid due to the
One dielectric layer, 23 thickness is too small, can not effectively prevent over etching problem.First medium layer 23 can be set according to demand and grid are situated between
The thickness relationship of matter layer 22, the thickness that first medium layer 23 also can be set in other modes are not less than the thickness of gate dielectric layer 22
Degree, using different-thickness first medium layer 23 and gate dielectric layer 22 when, it is only necessary to adjust the first secondary ion according to the actual situation
Implantation dosage.Therefore in the embodiment of the present invention specific limit is not done to the specific thickness of the two and first time ion implantation dosage
It is fixed.
Step S13: as shown in Figure 10, the first medium layer 23 based on the grid G 1 and its side wall, towards described first
Surface carries out first time ion implanting, is formed in the substrate 21 and source region LDS2 and lightly doped drain LDD2 is lightly doped.
On the direction perpendicular to substrate 21, the thinner thickness of first medium layer 23, it is only necessary to it is appropriate increase for the first time from
The dosage of son injection can form the lightly doped drain of set depth so that in ion implanting to the setting regions of substrate 21
LDD2 and source region LDS2 is lightly doped.Since the embodiment of the present invention is covered with one layer of first medium layer 23 on gate dielectric layer 22,
Compared with existing production method shown in Fig. 1-Fig. 7, first time ion implantation dosage needs appropriate increase, optionally, based on upper
The first medium layer 23 of setting thickness is stated, if the dosage of first time ion implanting is 1E12 quantity for making high tension apparatus
Grade, if dosage is the 1E15 order of magnitude for making low-voltage device.
In manufacturing process shown in the embodiment of the present invention, it is initially formed fleet plough groove isolation structure STI2, it is rear to carry out first time ion
Injection.In other modes, providing substrate includes: to form gate dielectric layer 22 on substrate 21 then to be formed on gate dielectric layer 22
Grid G 2.Hereafter, the first medium layer 23 for forming covering grid G2 and gate dielectric layer 22, forms by first time ion implanting
Lightly doped drain LDD2 and after source region LDS2 is lightly doped, re-forms the shallow ridges through first medium layer 23 and gate dielectric layer 22
Slot, the filled media material in shallow trench form fleet plough groove isolation structure STI2.At this point, fleet plough groove isolation structure STI2 and
One dielectric layer 23 flushes, and first medium layer 23 exposes fleet plough groove isolation structure STI2.
Step S14: as is illustrated by figs. 11 and 12, patterned second dielectric layer 24 is formed, described patterned second is situated between
The covering of matter layer 24 is located at the first medium layer 23 of 2 side wall of grid G, exposes the first medium layer 23 of other parts.
In the step, the patterned second dielectric layer 24 of formation includes: firstly, as shown in figure 11, forming non-pattern
The second dielectric layer 24 of change, the second dielectric layer 24 cover the first medium layer 23；Then, as shown in figure 12, pattern
The second dielectric layer 24 retains the part that the second dielectric layer 24 is located at the gate lateral wall, removes the institute of other parts
State second dielectric layer 24.The second dielectric layer 24 can be patterned by etching technics.
Wherein, the second dielectric layer 24 is silicon nitride.Optionally, the thickness range of second dielectric layer 24 is 20nm-
150nm, it is preferred that the thickness of second dielectric layer 24 can be 50nm, so that retaining after by subsequent second of ion implanting
The lightly doped drain LDD2 that is sized and source region LDS2 is lightly doped, and drain region D is contacted with lightly doped drain LDD2, so that
Source region S is contacted with source region LDS2 is lightly doped.
Step S15: as shown in figure 13, first medium layer 23 and second dielectric layer based on the grid G 2 and its side wall
24, second of ion implanting is carried out towards the first surface, forms source region S and drain region D in the substrate 21.
Drain region D is located between the adjacent fleet plough groove isolation structure STI2 of lightly doped drain LDD2 and one, and the drain region two sides D point
It is not contacted with lightly doped drain LDD2 and fleet plough groove isolation structure STI2.Source region S is adjacent with one positioned at source region LDS2 is lightly doped
Fleet plough groove isolation structure STI2 between, and the two sides source region S respectively with source region LDS2 and the fleet plough groove isolation structure is lightly doped
STI2 contact.
Optionally, on the direction for being parallel to the first surface, the grid G 2 is located at the lightly doped drain LDD2
It is lightly doped between source region LDS2 with described；On the direction perpendicular to the first surface, the grid G 2 is lightly doped with described
Drain region LDD2 and the source region LDS2 that is lightly doped are not overlapped.That is, in the production method described in the embodiment of the present invention,
Perpendicular to the direction of first surface, lightly doped drain LDD2 and the adjacent boundary of grid G 2 can be made to be overlapped, and lightly doped drain
Area LDD2 is not overlapped with grid G 2, lightly-doped source area LDS2 and the adjacent boundary of grid G 2 can be made to be overlapped, and lightly doped drain
Area LDD2 is not overlapped with grid G 2, and lightly doped drain LDD2 and the minimum spacing being lightly doped between source region LDS2 are equal to grid at this time
The width of G2.
In the embodiment of the present invention, using the first medium layer 23 of setting thickness, breakdown problem, reduction are prevented punch-through in realization
While parasitic capacitance and raising operating frequency purpose, so that the dosage of following first time ion implantings is smaller.And the
One dielectric layer 23 can also increase the adhesive force of 2 side wall second dielectric layer 24 of grid G.Meanwhile first medium layer 23 can also be made
For the etching barrier layer for etching second dielectric layer 24, when avoiding etching second dielectric layer 24, grid G 2 caused by over etching and shallow
The damage of groove isolation construction STI2.
As can be seen from the above description, production method described in the embodiment of the present invention can to avoid lightly-doped source area LDS2 with gently mix
Miscellaneous drain region LDD2 is diffused into 2 lower section of grid G, can increase and the distance between source region LDS2 and lightly doped drain LDD2 is lightly doped,
Breakdown problem is prevented punch-through, parasitic capacitance is reduced, improves operating frequency.But also it is led when to avoid patterning second dielectric layer 24
Cause the over etching problem of grid G 2 and fleet plough groove isolation structure STI2.Particularly, production method of the present invention only needs two layers of medium
Layer (first medium layer 23 and second dielectric layer 24), an etching process, production method is simple, low manufacture cost.
In the embodiment of the present invention, the semiconductor devices can be MOS, including PMOS or NMOS.Finally formed half
In conductor device, the lightly doped drain LDD2 that is formed by first time ion implantation technology and be lightly doped source region LDS2 have it is identical
The first doping concentration and the first injection depth, there is phase by the drain region D2 and source region S2 of second of ion implantation technology new city
The second same doping concentration and the second injection depth.First injection depth is less than less than the second injection depth, the first doping concentration
Second doping concentration, can be to avoid loss driving current.
Based on the above embodiment, another embodiment of the present invention additionally provides a kind of semiconductor devices, and the semiconductor devices is such as
Shown in Figure 13, which includes: substrate 21, and the substrate 21 has first surface；Cover the grid of the first surface
Dielectric layer 22；The grid G 2 that the gate dielectric layer 22 deviates from the one side of substrate surface is set；Cover the grid G 2 and
The first medium layer 23 of the gate dielectric layer 22；First medium layer 23 based on the grid G 2 and its side wall is formed in described
Source region LDS2 and lightly doped drain LDD2 is lightly doped in substrate 21；Covering is located at the 2 side wall first medium layer 23 of grid G
Second dielectric layer 24, the second dielectric layer 24 exposes the first medium layer 23 of other parts；Based on the grid G 2
And its first medium layer 23 and second dielectric layer 24 of side wall, the source region S2 and drain region D2 being formed in the substrate 21.
Semiconductor devices described in the embodiment of the present invention can be MOS.The first medium layer 23 is silica.Described
Second medium layer 24 is silicon nitride.On the direction for being parallel to the first surface, the grid G 2 is located at the lightly doped drain
It LDD2 and described is lightly doped between source region LDS2；On the direction perpendicular to the first surface, the grid G 2 with it is described light
Doped drain LDD2 is lightly doped source region LDS2 and does not overlap with described.
In semiconductor devices described in the embodiment of the present invention, the first medium layer 23 based on grid G 2 and its surface, described
Lightly doped drain LDD2 is formed in substrate 21 and source region LDS2 is lightly doped, and avoids that source region LDS2 and lightly doped drain is lightly doped
LDD2 is diffused into 2 lower section of grid G, can increase and the distance between source region LDS2 and lightly doped drain LDD2 is lightly doped, avoid wearing
Punchthrough breakdown problem reduces parasitic capacitance, improves operating frequency.First medium layer 23 based on the grid G and its side wall and
Second medium layer 24 forms source region S2 and drain region D2 in the substrate 21, when forming patterned second dielectric layer 23, due to
The protection of first medium layer 23, can be to avoid caused over etching problem when patterning second dielectric layer 24.And skill of the present invention
Art scheme only needs two layers of dielectric layer, and an etching technics, manufacture craft is simple, low manufacture cost.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.For partly being led disclosed in embodiment
For body device, since it is corresponding with production method disclosed in embodiment, so be described relatively simple, related place referring to
Production method relevant portion explanation.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that article or equipment including a series of elements not only include those elements, but also
It including other elements that are not explicitly listed, or further include for this article or the intrinsic element of equipment.Do not having
In the case where more limitations, the element that is limited by sentence "including a ...", it is not excluded that in the article including above-mentioned element
Or there is also other identical elements in equipment.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of production method of semiconductor devices, which is characterized in that the production method includes:
A substrate is provided, the substrate has first surface, and the first surface has gate dielectric layer, and the gate dielectric layer deviates from
One side surface of the substrate has grid；
First medium layer is formed, the first medium layer covers the gate dielectric layer and the grid；
First medium layer based on the grid and its side wall carries out first time ion implanting towards the first surface, in institute
It states to be formed in substrate and source region and lightly doped drain is lightly doped；
Patterned second dielectric layer is formed, the patterned second dielectric layer covering is located at the first of the gate lateral wall and is situated between
Matter layer exposes the first medium layer of other parts；
First medium layer and second dielectric layer based on the grid and its side wall, towards the first surface carry out second from
Son injection, forms source region and drain region in the substrate.
2. manufacturing method according to claim 1, which is characterized in that one substrate of the offer includes:
Gate dielectric layer is formed in the first surface of substrate；
Shallow trench is formed on the gate dielectric layer, the shallow trench extends in the substrate；
The filled media material in the shallow trench forms fleet plough groove isolation structure；
Grid is formed away from a side surface of the substrate in the gate dielectric layer；
Wherein, the first medium layer covers the surface of the fleet plough groove isolation structure.
3. manufacturing method according to claim 1, which is characterized in that described to form patterned second dielectric layer and include:
Non-patterned second dielectric layer is formed, the second dielectric layer covers the first medium layer；
The second dielectric layer is patterned, retains the part that the second dielectric layer is located at the gate lateral wall, removes other portions
The second dielectric layer divided.
4. manufacturing method according to claim 1, which is characterized in that the first medium layer is silica.
5. manufacturing method according to claim 1, which is characterized in that the second dielectric layer is silicon nitride.
6. manufacturing method according to claim 1, which is characterized in that on the direction for being parallel to the first surface, institute
Grid is stated to be located at the lightly doped drain and described be lightly doped between source region；
On the direction perpendicular to the first surface, the grid and the lightly doped drain and described source region is lightly doped not
It is overlapping.
7. a kind of semiconductor devices, which is characterized in that the semiconductor devices includes:
Substrate, the substrate have first surface；
Cover the gate dielectric layer of the first surface；
The grid that the gate dielectric layer deviates from the one side of substrate surface is set；
Cover the first medium layer of the grid and the gate dielectric layer；
First medium layer based on the grid and its side wall, is formed in the substrate and source region and lightly doped drain is lightly doped
Area；
Covering is located at the second dielectric layer of the first medium layer of the gate lateral wall, and the second dielectric layer exposes other parts
The first medium layer；
First medium layer and second dielectric layer based on the grid and its side wall, the source region and leakage being formed in the substrate
Area.
8. semiconductor devices according to claim 7, which is characterized in that the first medium layer is silica.
9. semiconductor devices according to claim 7, which is characterized in that the second dielectric layer is silicon nitride.
10. semiconductor devices according to claim 7, which is characterized in that on the direction for being parallel to the first surface,
The grid is located at the lightly doped drain and described is lightly doped between source region；
On the direction perpendicular to the first surface, source region is lightly doped not with described with the lightly doped drain in the grid
It is overlapping.
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