CN113451276A - Test structure, test system and test method - Google Patents
Test structure, test system and test method Download PDFInfo
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- CN113451276A CN113451276A CN202110723120.4A CN202110723120A CN113451276A CN 113451276 A CN113451276 A CN 113451276A CN 202110723120 A CN202110723120 A CN 202110723120A CN 113451276 A CN113451276 A CN 113451276A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The application provides a test structure, a test system and a test method, comprising: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad; the metal interconnection line comprises a test metal structure, and the test metal structure is used for testing a part of structures in the metal structure of the metal interlayer dielectric layer; the semiconductor device to be tested and the test pad are connected through a metal interconnection line; the test pad is used for providing a test voltage; the electrical property of the semiconductor device to be tested is used for reflecting the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested. The test structure in the embodiment of the application comprises a part of structure in the metal structure which can be used for testing the metal interlayer dielectric layer, namely, only a part of the metal structure of the existing metal interlayer dielectric layer is needed to be used for carrying out the plasma induced damage test.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a test structure, a test system and a test method.
Background
Currently, when manufacturing a chip including a plurality of semiconductor devices, in order to test the manufactured chip or a process of manufacturing the semiconductor devices included in the chip, a test structure is generally manufactured on a wafer together with the chip. The test structure is placed in a cutting channel among the chips, and after the test is finished, the chips manufactured on the wafer are separated through the cutting channel. Specifically, when the test structure is used for testing a chip, the test structure can be communicated through a PAD (PAD) electrically connected with the surface of the cutting path so as to test various performance parameters of the semiconductor device included in the chip and obtain a test result of the semiconductor device included in the chip.
When testing various performance parameters of a semiconductor device included in a chip by using a test structure, a Plasma process performance of the semiconductor device included in the chip in a manufacturing process can be tested by using the test structure, that is, a Plasma Induced Damage (PID) to which the semiconductor device is subjected in a Plasma process is tested, but now, due to the limited area of a cutting path, various test requirements of the Plasma Induced Damage test cannot be met, so that a new test structure and a new test method are urgently needed to realize the various test requirements of the Plasma Induced Damage test.
Disclosure of Invention
In view of the above, an object of the present application is to provide a test structure, a test system and a test method, which can meet various test requirements of a plasma induced damage test.
The embodiment of the application provides a test structure, includes: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad;
the metal interconnection line and the semiconductor device to be tested are positioned on the same wafer, the metal interconnection line comprises a test metal structure, and the test metal structure is used for a part of structures in a metal structure for testing the metal interlayer dielectric layer;
the semiconductor device to be tested and the test pad are connected through the metal interconnection line;
the test pad is used for providing a test voltage;
and the electrical property of the semiconductor device to be tested is used for showing the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Optionally, the test metal structure is a comb-shaped structure or a zigzag structure.
Optionally, the test metal structure is a multilayer structure, and two adjacent layers of structures are arranged in parallel or in a staggered manner.
Optionally, the two adjacent layers of structures are connected to each other by a via.
Optionally, the semiconductor device to be tested is a MOS transistor.
Optionally, the metal interconnection line is connected to a gate or a source of the MOS transistor.
An embodiment of the present application provides a test system, including: the testing device comprises a first metal interconnection line, a second metal interconnection line, a first semiconductor device to be tested, a second semiconductor device to be tested, a first testing pad and a second testing pad;
the first semiconductor device to be tested and the first test pad are connected through the first metal interconnection line, and the second semiconductor device to be tested and the second test pad are connected through the second metal interconnection line;
the first metal interconnection line comprises a first testing metal structure, the second metal interconnection line comprises a second testing metal structure, and the first testing metal structure and the second testing metal structure belong to the same group of metal structures used for testing the metal interlayer dielectric layer and are used for connecting different metal interlayer dielectric layer testing voltages.
Optionally, the first test metal structure and the second test metal structure are comb-shaped structures, and the first test metal structure and the second test metal structure are embedded into each other or two layers of the first test metal structure and the second test metal structure are arranged in parallel and opposite to each other.
Optionally, the first semiconductor device to be tested is an N-type MOS transistor, and the second semiconductor device to be tested is a P-type MOS transistor.
The embodiment of the application provides a test method, which comprises the following steps:
providing a test voltage for the test pad;
the test voltage reaches the semiconductor device to be tested through the test pad and the metal interconnection line; the metal interconnection line comprises a test metal structure, and the test metal structure is a partial structure in the metal structure for testing the metal interlayer dielectric layer;
and testing the electrical performance of the semiconductor device to be tested to obtain the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Optionally, the metal interconnection line is connected to a gate of the semiconductor device to be tested;
the testing the electrical performance of the semiconductor device to be tested comprises the following steps:
and testing the leakage current of the grid oxide layer of the semiconductor device to be tested.
The test structure that this application embodiment provided includes: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad; the metal interconnection line and the semiconductor device to be tested are positioned on the same wafer, the metal interconnection line comprises a test metal structure, and the test metal structure is used for a part of structures in a metal structure for testing the metal interlayer dielectric layer; the semiconductor device to be tested and the test pad are connected through the metal interconnection line; the test pad is used for providing a test voltage; and the electrical property of the semiconductor device to be tested is used for showing the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Therefore, the test structure in the embodiment of the application comprises partial structures in a metal structure which can be used for testing the metal interlayer dielectric layer, namely the test structure provided by the application does not need to be designed independently, only needs to utilize one part in the existing metal interlayer dielectric layer metal structure to carry out the plasma induced damage test, namely, one metal interlayer dielectric layer metal structure can be used for testing the metal interlayer dielectric layer and also can be used for testing the plasma induced damage, and the metal interlayer dielectric layer metal structures with various structure types can also meet the diversified PID test requirements, meanwhile, because the same test bonding pad is used for connecting the test structure, the same test bonding pad can be utilized to carry out the test of different semiconductor performances with the same test structure, namely, the number of the test bonding pads is saved, and more test structures can be arranged in the limited cutting track area, various tests of semiconductor properties were performed.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 shows a schematic diagram of a test structure in the prior art;
FIG. 2 shows a schematic diagram of a test structure according to an embodiment of the present application;
fig. 3-4 show schematic diagrams of another test structure according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, currently when manufacturing a chip including a plurality of semiconductor devices, in order to test the manufactured chip or a process of manufacturing the semiconductor devices included in the chip, a test structure is generally manufactured on a wafer together with the chip. The test structure is placed in a cutting channel among the chips, and after the test is finished, the chips manufactured on the wafer are separated through the cutting channel. Specifically, when the test structure is used for testing a chip, the test structure can be communicated through a PAD (PAD) electrically connected with the surface of the cutting path so as to test various performance parameters of the semiconductor device included in the chip and obtain a test result of the semiconductor device included in the chip.
Referring to fig. 1, 4 chips are manufactured on a wafer, a plurality of bonding pads are formed on a surface of a scribe line between the chips, a plurality of test structures are manufactured in the scribe line under the bonding pads, each test structure includes a semiconductor device for testing, the bonding pads are electrically connected to test the semiconductor device included in the test structure, and a test result of the semiconductor device is obtained, wherein the test result can reflect whether a plurality of processes for manufacturing the chips including the semiconductor device are normal or healthy and reasonable.
When the test structure is used for testing various performance parameters of the semiconductor device included in the chip, the test structure can be used for testing a plasma process of the semiconductor device included in the chip in a manufacturing process, namely testing plasma induced damage of the semiconductor device when the plasma process is carried out. In a metal interconnection process or a via formation process performed at a later stage of manufacturing of a semiconductor device, various plasma related processes, such as dry etching, plasma enhanced chemical vapor deposition, etc., are generally used. These plasma processes may affect the gate oxide layer in the semiconductor device, resulting in damage to the gate oxide layer, and thus, when the gate oxide layer is tested, a large leakage current is generated, so that the performance of the finally manufactured chip is reduced.
An existing Plasma Induced Damage (PID) test structure includes a plurality of layers of metal lines and semiconductor devices, and the PID test structure is integrally disposed in a scribe line of a wafer. In the process of forming the metal line and the through hole, due to the fact that a plasma related process is used, the metal line and the through hole in the test structure are influenced by the plasma related process to generate a charging effect, a potential is applied to the semiconductor device, a grid oxide layer on the semiconductor device is damaged, and the larger the area of the metal line is, the larger the damage to the grid oxide layer is. The charging effect refers to that charges in a plasma process are attached to a gate oxide layer, so that the gate oxide layer has a potential difference, and the gate oxide layer is damaged due to the potential difference. The gate oxide layer may be affected when each metal line or via is formed using a plasma process.
Because the area of the cutting channel is limited, the number of PADs for electrically leading out the test structure is also limited, so that the influence of the PID commonly generated after the metal wires are stacked on the grid oxide layer is usually tested at present, if the influence of the PID generated by each layer of metal wires on the grid oxide layer is tested, the test structure combining a single-layer metal wire and a semiconductor device needs to be independently arranged, each test structure electrically leads out a PAD, the occupied area of the cutting channel is obviously increased, more other test structures cannot be arranged in the cutting channel with the limited area, and various test requirements of a chip are met.
Referring to fig. 1, the PID test structure includes 4 layers of metal lines and a semiconductor device, which may be a metal oxide semiconductor field Effect (MOS) transistor, and if the PID influence of each layer of metal lines on the gate oxide layer of the MOS transistor is to be tested, each layer is required to correspond to an electrically led PAD, and in addition, the PID influence commonly generated after the multiple layers of metal lines are stacked, a total of 5 electrically led PADs are required. With the increase of the number of the metal wire layers, the number of PADs is more and more, and the various testing requirements of PID testing are more and more.
The existing PAD quantity and cutting path area can not meet various test requirements, and a new test structure and a new test method are urgently needed to meet various test requirements of a plasma induced damage test.
The inventor researches and discovers that the test structure for testing the Inter Metal Dielectric (IMD) layer can also be applied to PID test, and can meet various PID test requirements under the condition of limited cutting channel area, such as PID influence of a single-layer Metal wire on a grid oxide layer.
Based on this, the embodiment of the application provides a test structure, a test system and a test method, including: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad; the metal interconnection line and the semiconductor device to be tested are positioned on the same wafer, the metal interconnection line comprises a test metal structure, and the test metal structure is used for a part of structures in a metal structure for IMD (in-mold decoration) test of the metal interlayer dielectric layer; the semiconductor device to be tested and the test pad are connected through the metal interconnection line; the test pad is used for providing a test voltage; and the electrical property of the semiconductor device to be tested is used for reflecting the PID influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Therefore, the test structure in the embodiment of the application comprises a part of structure in a metal structure which can be used for performing IMD test, namely the test structure provided by the application does not need to be designed independently, and only needs to utilize one part of the existing IMD metal structure to perform PID test, namely, one IMD metal structure can be used for both IMD test and PID test, and IMD metal structures of various structure types can also meet diversified PID test requirements.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a schematic diagram of a test structure that can be used for performing PID testing according to an embodiment of the present application is provided, where the test structure 201 includes: metal interconnect lines 211, semiconductor devices to be tested 221, and test pads 231.
In this embodiment of the present application, the Semiconductor device to be tested may be an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor field Effect Transistor (MOSFET, hereinafter referred to as MOS Transistor), a SiC MOSFET (Silicon Carbide field Effect Transistor), and other Semiconductor devices, and the embodiment of the present application does not specifically limit the type of the Semiconductor device to be tested. In the embodiment of the present application, a MOS transistor may be employed as the semiconductor device to be tested.
In the embodiment of the present application, the metal interconnection line 211 may affect the semiconductor device to be tested by using a plasma process in the manufacturing process, and particularly may damage the gate oxide layer of the semiconductor device to be tested, so that the performance of the subsequent semiconductor device may be reduced in the testing or application process, for example, leakage current is generated to increase the power consumption of the device itself, and the switching function of the MOS transistor may be disabled due to the leakage current.
The metal interconnection line 211 may include a plurality of layers, and an area of metal in each layer of the metal interconnection line 211 may be the same as an area of a certain layer of the metal interconnection line in the semiconductor device 221 to be tested or may be larger than an area of a certain layer of the metal interconnection line in the semiconductor device 221 to be tested, so as to simulate an influence on the semiconductor device 221 to be tested after the metal interconnection line having the largest area is formed in the semiconductor device 221 to be tested.
In practical applications, the larger the area of the metal interconnection line, the greater the influence on the semiconductor device 221 to be tested. Therefore, in the PID test, the influence of each layer of metal interconnection 211 on the semiconductor device 221 to be tested can be tested, and the influence of all the layers of metal interconnection lines on the semiconductor device 221 to be tested can also be tested.
In the embodiment of the present application, the metal interconnection line 211 and the semiconductor device 221 to be tested are located on the same wafer, the semiconductor device 221 to be tested and the test pad 231 are connected through the metal interconnection line 211, when the semiconductor device 221 to be tested is a MOS transistor, the metal interconnection line 211 may be connected to a gate or a source of the MOS transistor, and in some cases, the metal interconnection line 211 may also be connected to a drain or a hydrazine of the MOS transistor. The test pad 231 is used to supply a test voltage. The electrical properties of the semiconductor device to be tested are used to reflect the PID influence of the metal interconnection line 211 on the plasma-induced damage generated by the semiconductor device 221 to be tested. The electrical properties of the semiconductor device 221 to be tested may include the properties of the gate oxide layer, such as whether the gate oxide layer has a leakage current, the magnitude of the leakage current, and the like.
In the embodiment of the present application, the metal interconnection line 211 includes a test metal structure 2111, and the test metal structure 2111 is used as a part of a metal structure for an inter-metal dielectric IMD test. The test metal structure 2111 may be a comb-like structure, i.e. resembling a comb, a meander-line structure, or a serpentine structure.
Referring to fig. 2, the test metal structures 2111 of two comb structures embedded in each other on the same plane may form a complete metal structure for IMD test. When IMD test is carried out, high voltage is applied to one end of two ends of the two comb-shaped structures by using the two test pads, and low voltage is applied to the other end of the two comb-shaped structures, so that the interlayer dielectric layer between the metal interconnection lines can be tested. When performing the PID test, one of the test pads 231 is applied with a high test voltage and electrically connected to the gate of the semiconductor device 221 to be tested through the metal interconnection line 211, the drain of the semiconductor device 221 to be tested can be connected with a low voltage or grounded to perform the related test of the electrical performance of the semiconductor device 221 to be tested, while the other test pad does not perform any voltage treatment.
In summary, a complete IMD metal structure can be used for IMD testing, and a part of the IMD metal structure can also be used for PID testing, and the IMD test and the PID test can be distinguished by applying test voltages to different test pads during testing.
Referring to fig. 3, another test structure provided in the embodiments of the present application is shown. The test metal structure 2111 may be a single-layer structure or a multi-layer structure. When the test metal structure 2111 is a multilayer structure, two adjacent layers may be disposed in parallel or staggered. Fig. 3 shows that the structures of two adjacent layers are arranged in a staggered manner, i.e. the metal lines of the test metal structure 2111 of the next layer are perpendicular to the metal lines of the test metal structure 2111 of the previous layer.
In practical application, when the test metal structure 2111 is a multilayer structure, two adjacent layers of structures can be connected through a through hole, and after the through hole connection, for an IMD test, the performance of an interlayer dielectric layer between two adjacent layers and the performance of an interlayer dielectric layer between different through holes can be tested; for the PID test, the influence of the metal interconnection layers of two adjacent layers on the electrical performance of the semiconductor device to be tested can be tested.
The test metal structures of 2 comb structures in the same layer shown in fig. 3 are embedded into each other, the test metal structures of two adjacent layers are arranged in a staggered manner, and the test metal structures of two adjacent layers are connected through holes. When IMD test is carried out, high voltage is applied to one end of two ends of the two comb-shaped structures by the two test bonding pads, and low voltage is applied to the other end of the two comb-shaped structures, so that the interlayer dielectric layer between two layers of metal interconnection lines and the interlayer dielectric layer between different through holes can be tested. When the PID test is performed, one of the test pads 231 is applied with a high test voltage, the gate of the semiconductor device 221 to be tested is electrically connected through the two layers of metal interconnection lines 211, the drain of the semiconductor device 221 to be tested can be connected with a low voltage or grounded, so as to perform the related test of the electrical performance of the semiconductor device 221 to be tested, obtain the PID influence of the two layers of metal interconnection lines and the through hole array on the semiconductor device 221 to be tested, and the other test pad does not perform any voltage treatment.
Referring to fig. 4, the two test metal structures of the comb-like structure may also be disposed in parallel and opposite to each other, and the test metal structures of the two comb-like structures are aligned with each other in the longitudinal direction, or in the direction perpendicular to the placement direction of the test metal structures, the test metal structures of the two comb-like structures are aligned. When IMD test is carried out, high voltage is applied to one end of two ends of the two comb-shaped structures by the two test bonding pads, and low voltage is applied to the other end of the two comb-shaped structures, so that the interlayer dielectric layer between the two layers of metal interconnection lines can be tested. When the PID test is performed, one of the test pads 231 is applied with a high test voltage, the gate of the semiconductor device 221 to be tested is electrically connected through one layer of the metal interconnection line 211, the drain of the semiconductor device 221 to be tested can be connected with a low voltage or grounded, so as to perform the related test of the electrical performance of the semiconductor device 221 to be tested, obtain the PID influence of the single layer of the metal interconnection line and the through hole array on the semiconductor device 221 to be tested, and the other test pad does not perform any voltage treatment.
The embodiment of the application provides a test structure, includes: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad; the metal interconnection line and the semiconductor device to be tested are positioned on the same wafer, the metal interconnection line comprises a test metal structure, and the test metal structure is used for a part of structures in a metal structure for IMD (in-mold decoration) test of the metal interlayer dielectric layer; the semiconductor device to be tested and the test pad are connected through the metal interconnection line; the test pad is used for providing a test voltage; and the electrical property of the semiconductor device to be tested is used for reflecting the PID influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Therefore, the test structure in the embodiment of the application comprises a part of structure in a metal structure which can be used for performing IMD test, namely the test structure provided by the application does not need to be designed independently, and only needs to utilize one part of the existing IMD metal structure to perform PID test, namely, one IMD metal structure can be used for both IMD test and PID test, and IMD metal structures of various structure types can also meet diversified PID test requirements.
Based on the test structure provided by the above embodiment, an embodiment of the present application further provides a test system, including: a first metal interconnection line 211, a second metal interconnection line 212, a first semiconductor device to be tested 221, a second semiconductor device to be tested 222, a first test pad 231, and a second test pad 232.
Referring to fig. 2, 3 or 4, the first semiconductor device to be tested 221 and the first test pad 231 are connected through the first metal interconnection line 211, and the second semiconductor device to be tested 222 and the second test pad 232 are connected through the second metal interconnection line 212.
The first metal interconnection line 211 comprises a first test metal structure 2111, the second metal interconnection line 212 comprises a second test metal structure 2121, and the first test metal structure 2111 and the second test metal structure 2121 belong to the same group of metal structures used for inter-metal dielectric layer IMD test and are used for connecting different IMD test voltages.
In the embodiment of the present application, the first test metal structure 2111 and the second test metal structure 2121 may both be comb-shaped structures, and the first test metal structure 2111 and the second test metal structure 2121 may be embedded into each other or two layers of the two test metal structures are disposed in parallel and opposite to each other.
Referring to fig. 2 or fig. 3, the first test metal structure 2111 and the second test metal structure 2121 are embedded in the same plane; referring to fig. 4, the first test metal structure 2111 and the second test metal structure 2121 are disposed in parallel and opposite to each other on different planes.
In the embodiment of the present application, the first semiconductor device under test 221 may be an N-type MOS transistor, and the second semiconductor device under test 222 is a P-type MOS transistor. The arrangement can reflect the difference of the bearing capacity of MOS transistors with different channel types for PID test.
Referring to fig. 2, when performing the PID test, a high test voltage is applied to the first test pad 231, the first metal interconnection line 211 is electrically connected to the gate of the first semiconductor device 221 to be tested, the drain of the first semiconductor device 221 to be tested can be connected to a low voltage or ground, so as to perform the electrical performance related test on the first semiconductor device 221 to be tested, and the second test pad 232 does not perform any voltage treatment; the second test pad 232 is applied with a high test voltage and electrically connected to the gate of the second semiconductor device under test 222 through the second metal interconnection line 212, the drain of the second semiconductor device under test 222 can be connected with a low voltage or grounded to perform a related test of electrical properties on the second semiconductor device under test 222, and the first test pad 231 does not perform any voltage treatment. The metal structure shown in fig. 2 can test the PID influence of a single-layer metal interconnection line on the semiconductor devices to be tested, and when a specific test is performed, there is no voltage between the test metal structures of the two comb structures, i.e., one is connected to the voltage by using the test pad, and the other is completely connected to the voltage, so that the PID tests of the two semiconductor devices to be tested can be performed by using the IMD metal structure.
The specific test process of the test structure shown in fig. 3 and fig. 4 may refer to the specific description of the above embodiment, and is not repeated here.
Based on the test structure and the test system provided by the embodiment, the embodiment of the application further provides a test method, and the test method applies the test structure provided by the embodiment.
The test method provided by the embodiment of the application comprises the following steps:
providing a test voltage for the test pad;
the test voltage reaches the semiconductor device to be tested through the test pad and the metal interconnection line; the metal interconnection line comprises a test metal structure, and the test metal structure is a partial structure in a metal structure for IMD (in-mold decoration) test of the metal interlayer dielectric layer;
and testing the electrical performance of the semiconductor device to be tested to obtain the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
Optionally, the metal interconnection line is connected to a gate of the semiconductor device to be tested;
the testing the electrical performance of the semiconductor device to be tested comprises the following steps:
and testing the leakage current of the grid oxide layer of the semiconductor device to be tested.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (11)
1. A test structure, comprising: the device comprises a metal interconnection line, a semiconductor device to be tested and a test bonding pad;
the metal interconnection line and the semiconductor device to be tested are positioned on the same wafer, the metal interconnection line comprises a test metal structure, and the test metal structure is used for partial structure in the metal structure for testing the metal interlayer dielectric layer;
the semiconductor device to be tested and the test pad are connected through the metal interconnection line;
the test pad is used for providing a test voltage;
and the electrical property of the semiconductor device to be tested is used for showing the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
2. The test structure of claim 1, wherein the test metal structure is a comb-like structure or a meander-line structure.
3. The test structure of claim 1, wherein the test metal structure is a multi-layer structure, and adjacent two layers of the structure are arranged in parallel or staggered.
4. The test structure of claim 3, wherein the adjacent two-layer structures are interconnected by vias.
5. The test structure of claim 1, wherein the semiconductor device under test is a MOS transistor.
6. The test structure of claim 5, wherein the metal interconnect line connects a gate or a source of the MOS transistor.
7. A test system, comprising: the testing device comprises a first metal interconnection line, a second metal interconnection line, a first semiconductor device to be tested, a second semiconductor device to be tested, a first testing pad and a second testing pad;
the first semiconductor device to be tested and the first test pad are connected through the first metal interconnection line, and the second semiconductor device to be tested and the second test pad are connected through the second metal interconnection line;
the first metal interconnection line comprises a first testing metal structure, the second metal interconnection line comprises a second testing metal structure, and the first testing metal structure and the second testing metal structure belong to the same group of metal structures used for testing the metal interlayer dielectric layer and are used for connecting different metal interlayer dielectric layer testing voltages.
8. The test system of claim 7, wherein the first test metal structure and the second test metal structure are comb-shaped structures, and the first test metal structure and the second test metal structure are embedded into each other or two layers are arranged in parallel and opposite to each other.
9. The test system of claim 7, wherein the first semiconductor device under test is an N-type MOS transistor and the second semiconductor device under test is a P-type MOS transistor.
10. A method of testing, comprising: providing a test voltage for the test pad;
the test voltage reaches the semiconductor device to be tested through the test pad and the metal interconnection line; the metal interconnection line comprises a test metal structure, and the test metal structure is a partial structure in the metal structure for testing the metal interlayer dielectric layer;
and testing the electrical performance of the semiconductor device to be tested to obtain the influence of the metal interconnection line on the plasma induced damage generated by the semiconductor device to be tested.
11. The test method of claim 10, wherein the metal interconnection line is connected to a gate of the semiconductor device to be tested;
the testing the electrical performance of the semiconductor device to be tested comprises the following steps:
and testing the leakage current of the grid oxide layer of the semiconductor device to be tested.
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Application publication date: 20210928 |