CN103872023A - Structure and method for testing performances of inter-layer dielectric layer - Google Patents
Structure and method for testing performances of inter-layer dielectric layer Download PDFInfo
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- CN103872023A CN103872023A CN201410110743.4A CN201410110743A CN103872023A CN 103872023 A CN103872023 A CN 103872023A CN 201410110743 A CN201410110743 A CN 201410110743A CN 103872023 A CN103872023 A CN 103872023A
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Abstract
The invention provides a structure and method for testing the performances of an inter-layer dielectric layer. The space over a grid electrode is used for collecting charges which are brought by plasma and it is ensured that the grid electrode and an antenna are isolated by the inter-layer dielectric layer. When the charges received by the antenna are accumulated to an amount that an inter-layer insulating layer can not bear, the charges will penetrate through the inter-layer insulating layer and damage a semiconductor device. When detection is carried out, leaked currents and threshold voltages of the semiconductor device are detected so that whether the semiconductor device is damaged or not can be judged. Thus, whether the inter-layer dielectric layer is broken through or not can be judged. The plasma-damage-resisting capacity of the inter-layer dielectric layer can be detected.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of test structure and method of testing of interlayer dielectric layer performance.
Background technology
Semiconductor front end technique, after prepared by device, can form interlayer dielectric layer (Interlayer dielectric, ILD) at device surface, and then prepares the metal interconnecting wires layer of last part technology.Therefore, interlayer dielectric layer is except providing good insulating properties, prevents between different layers conductor beyond short circuit, also plays protection device and avoid being subject to the effect of plasma damage.
Because metal interconnecting wires layer is multilayer; ground floor can adopt through hole line to be connected with grid, source electrode, drain electrode and the base stage etc. of described device conventionally; but other parts of ground floor may not be connected with device and are connected with rear layer metal connecting line etc.; therefore interlayer dielectric layer just need to keep good insulating properties, is short-circuited with the metal connecting line and the device that prevent from not being connected with device.
Owing to making when metal connecting line, conventionally can produce a large amount of electric charges, electric charge constantly accumulation meeting causes plasma damage to interlayer dielectric layer, if plasma damage is serious, can causes the leakage current etc. of whole device to become large, thereby reduce the performance of device.
But, can not detect at present the test structure of interlayer dielectric layer anti-plasma damage ability, the test structure of common resistance to plasma damage can only detect the plasma damage problem that the metal interconnected Wiring technology of back segment produces, and the ability of interlayer dielectric layer anti-plasma can not be detected.Therefore, those skilled in the art are badly in need of proposing a kind of test structure that can detect interlayer dielectric layer anti-plasma damage ability.
Summary of the invention
The object of the present invention is to provide a kind of test structure and method of testing of interlayer dielectric layer performance, can detect the ability of interlayer dielectric layer anti-plasma damage.
To achieve these goals, the present invention proposes a kind of test structure of interlayer dielectric layer performance, for the detection to interlayer dielectric layer anti-plasma damage ability, described structure comprises: semiconductor device, interlayer dielectric layer, through hole line, metal connecting line and antenna; Wherein, described semiconductor device is provided with grid, source electrode, drain electrode and base stage; Described interlayer dielectric layer is formed at described semiconductor device surface; Described metal connecting line is formed at the surface of described interlayer dielectric layer, comprises gate metal line, source electrode through hole line, drain electrode through hole line and base stage through hole line; Described grid, source electrode, drain electrode and base stage are connected respectively described gate metal line, source electrode through hole line, drain electrode through hole line and base stage through hole line by through hole line; The surface that described dwi hastasana is formed in described interlayer dielectric layer be positioned at described grid directly over, and isolated with described semiconductor device and metal connecting line.
Further, in the test structure of described interlayer dielectric layer performance, described antenna parallels with described grid.
Further, in the test structure of described interlayer dielectric layer performance, the area of described antenna is described gate area 2000～6000 times.
Further, in the test structure of described interlayer dielectric layer performance, described antenna is one deck or multilayer.
Further, in the test structure of described interlayer dielectric layer performance, between stacked antenna, adopt through hole line to be connected.
Further, the invention allows for a kind of method of testing of interlayer dielectric layer performance, the test structure of any one interlayer dielectric layer performance is as described above tested, described method comprises step:
In the given time, described grid is applied the test voltage of pre-sizing;
Measure test leakage current and the testing valve threshold voltage of semiconductor device;
Judge that by the test leakage current measuring and testing valve threshold voltage interlayer dielectric layer is subject to the degree of plasma damage.
Further, in the method for testing of described interlayer dielectric layer performance, before described grid is applied to the voltage of pre-sizing, measure initial leakage current and the Initial Hurdle voltage of semiconductor device.
Further, in the method for testing of described interlayer dielectric layer performance, the variable quantity of compare test leakage current and testing valve threshold voltage and described initial leakage current and Initial Hurdle voltage judges that interlayer dielectric layer is subject to the degree of plasma damage.
Further, in the method for testing of described interlayer dielectric layer performance, the predetermined magnitude range of described test voltage is 1.2～1.4 times of described semiconductor device operating voltage.
Further, in the method for testing of described interlayer dielectric layer performance, described scheduled time scope is 3s～6s.
Compared with prior art, beneficial effect of the present invention is mainly reflected in: directly over grid, be formed for collecting the electric charge being brought by plasma, and guarantee that grid and antenna isolated by interlayer dielectric layer, when the charge accumulated of antenna reception is during to the unaffordable amount of interlayer insulating film, electric charge will pass interlayer insulating film, semiconductor device is caused damage, in the time detecting, just can judge by the leakage current and the threshold voltage that detect semiconductor device whether semiconductor device is compromised, and then judge that whether interlayer dielectric layer is breakdown, realize the detection to interlayer dielectric layer anti-plasma damage ability.
Accompanying drawing explanation
Fig. 1 is the vertical view of the test structure of interlayer dielectric layer performance in one embodiment of the invention;
Fig. 2 is that the test structure of interlayer dielectric layer performance in one embodiment of the invention is along the generalized section of Fig. 1 dotted line AA.
Embodiment
Test structure and method of testing below in conjunction with schematic diagram to interlayer dielectric layer performance of the present invention are described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 1 and Fig. 2, in the present embodiment, proposed a kind of test structure of interlayer dielectric layer performance, for the detection to interlayer dielectric layer anti-plasma damage ability, described structure comprises: semiconductor device, interlayer dielectric layer, through hole line, metal connecting line and antenna;
Wherein, described semiconductor device is formed in Semiconductor substrate 10, and described semiconductor device is provided with grid 20, source electrode, drain electrode and base stage (scheming not shown); Described interlayer dielectric layer (in order to simplify accompanying drawing, all not shown in Fig. 1 and Fig. 2) is formed at the surface of described semiconductor device; Described metal connecting line is formed at the surface of described interlayer dielectric layer, and described metal connecting line comprises gate metal line 34, source electrode through hole line 31, drain electrode through hole line 32 and base stage through hole line 33; Described grid 20, source electrode, drain electrode and base stage are connected respectively described gate metal line 34, source electrode through hole line 31, drain electrode through hole line 32 and base stage through hole line 33 by through hole line 21; The surface that described antenna 40 is formed at described interlayer dielectric layer be positioned at described grid 200 directly over, and isolated with described semiconductor device and metal connecting line.
In the present embodiment, described antenna 40 parallels with described grid 20, and described antenna 40 can be square or circular, and its gross area is 2000～6000 times of described grid 20, for example, be 5000 times.Described antenna 40 is one deck or multilayer, adopts through hole line 21 to be connected between stacked antenna 40, and stacked antenna 40 is also in order to collect more plasma charge.Described antenna 40 areas are larger, and the plasma charge of its collection is just more, thereby can carry out good test to the performance of described interlayer dielectric layer.
When the plasma charge receiving when antenna 40 runs up to the unaffordable amount of interlayer insulating film, plasma charge will pass interlayer insulating film, and semiconductor device is caused damage.Because the grid 20 in semiconductor device is polysilicons, it is projection for Semiconductor substrate 10, therefore, described grid 20 is smaller with the spacing of its top antenna 40, interlayer insulating film thinner thickness herein, more easily punctured by plasma charge, the last major effect of plasma charge that antenna 40 receives is to the performance of grating of semiconductor element 20, so can reflect by measuring grid oxygen electrical parameter relevant or that semiconductor device is degenerated the anti-plasma damage ability of interlayer insulating film.
In the present embodiment, also proposed a kind of method of testing of interlayer dielectric layer performance, the test structure of interlayer dielectric layer performance is as described above tested, described method comprises step:
S1: in the given time, to described grid: 2 apply the test voltage of pre-sizing;
S2: test leakage current and the testing valve threshold voltage of measuring semiconductor device;
S3: judge that by the test leakage current measuring and testing valve threshold voltage interlayer dielectric layer is subject to the degree of plasma damage.
In the present embodiment, before described grid 20 is applied to the voltage of pre-sizing, first measure initial leakage current and the Initial Hurdle voltage of semiconductor device, then the variable quantity of compare test leakage current and testing valve threshold voltage and described initial leakage current and Initial Hurdle voltage judges that interlayer dielectric layer is subject to the degree of plasma damage.
In the present embodiment, the predetermined magnitude range of described test voltage is described semiconductor device operating voltage V
op1.2～1.4 times, be for example 1.3 times; Described scheduled time scope is 3s～6s, for example, be 5s; As stress condition, measure afterwards test leakage current and testing valve threshold voltage according to this.If there is obvious variation in test leakage current and testing valve threshold voltage, illustrate that interlayer dielectric layer is breakdown, if test leakage current and testing valve threshold voltage are in tolerance interval, the functional of interlayer dielectric layer is described.
To sum up, in the test structure and method of testing of the interlayer dielectric layer performance providing in the embodiment of the present invention, directly over grid, be formed for collecting the electric charge being brought by plasma, and guarantee that grid and antenna isolated by interlayer dielectric layer, when the charge accumulated of antenna reception is during to the unaffordable amount of interlayer insulating film, electric charge will pass interlayer insulating film, semiconductor device is caused damage, in the time detecting, just can judge by the leakage current and the threshold voltage that detect semiconductor device whether semiconductor device is compromised, and then judge that whether interlayer dielectric layer is breakdown, realize the detection to interlayer dielectric layer anti-plasma damage ability.
Above are only the preferred embodiments of the present invention, the present invention is not played to any restriction.Any person of ordinary skill in the field; not departing from the scope of technical scheme of the present invention; the technical scheme that the present invention is disclosed and technology contents make any type of variations such as replacement or modification that are equal to; all belong to the content that does not depart from technical scheme of the present invention, within still belonging to protection scope of the present invention.
Claims (10)
1. a test structure for interlayer dielectric layer performance, for the detection to interlayer dielectric layer anti-plasma damage ability, described structure comprises: semiconductor device, interlayer dielectric layer, through hole line, metal connecting line and antenna; Wherein, described semiconductor device is provided with grid, source electrode, drain electrode and base stage; Described interlayer dielectric layer is formed at described semiconductor device surface; Described metal connecting line is formed at the surface of described interlayer dielectric layer, comprises gate metal line, source electrode through hole line, drain electrode through hole line and base stage through hole line; Described grid, source electrode, drain electrode and base stage are connected respectively described gate metal line, source electrode through hole line, drain electrode through hole line and base stage through hole line by through hole line; The surface that described dwi hastasana is formed in described interlayer dielectric layer be positioned at described grid directly over, and isolated with described semiconductor device and metal connecting line.
2. the test structure of interlayer dielectric layer performance as claimed in claim 1, is characterized in that, described antenna parallels with described grid.
3. the test structure of interlayer dielectric layer performance as claimed in claim 2, is characterized in that, the area of described antenna is described gate area 2000～6000 times.
4. the test structure of interlayer dielectric layer performance as claimed in claim 3, is characterized in that, described antenna is one deck or multilayer.
5. the test structure of interlayer dielectric layer performance as claimed in claim 4, is characterized in that, adopts through hole line to be connected between stacked antenna.
6. a method of testing for interlayer dielectric layer performance, tests the test structure of any one interlayer dielectric layer performance as described in claim 1 to 5, and described method comprises step:
In the given time, described grid is applied the test voltage of pre-sizing;
Measure test leakage current and the testing valve threshold voltage of semiconductor device;
Judge that by the test leakage current measuring and testing valve threshold voltage interlayer dielectric layer is subject to the degree of plasma damage.
7. the method for testing of interlayer dielectric layer performance as claimed in claim 6, is characterized in that, before described grid is applied to the voltage of pre-sizing, first measures initial leakage current and the Initial Hurdle voltage of semiconductor device.
8. the method for testing of interlayer dielectric layer performance as claimed in claim 7, it is characterized in that, the variable quantity of compare test leakage current and testing valve threshold voltage and described initial leakage current and Initial Hurdle voltage judges that interlayer dielectric layer is subject to the degree of plasma damage.
9. the method for testing of interlayer dielectric layer performance as claimed in claim 6, is characterized in that, the predetermined magnitude range of described test voltage is 1.2～1.4 times of described semiconductor device operating voltage.
10. the method for testing of interlayer dielectric layer performance as claimed in claim 6, is characterized in that, described scheduled time scope is 3s～6s.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105388407A (en) * | 2014-09-09 | 2016-03-09 | 中芯国际集成电路制造(上海)有限公司 | Integrity detection method for gate dielectric layer |
| CN113451276A (en) * | 2021-06-28 | 2021-09-28 | 长江存储科技有限责任公司 | Test structure, test system and test method |
| CN113497002A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6353235B1 (en) * | 1998-11-09 | 2002-03-05 | Mitsubishi Denki Kabushiki Kaisha | Plasma damage detector and plasma damage evaluation method |
| US20020098604A1 (en) * | 1999-12-20 | 2002-07-25 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
-
2014
- 2014-03-24 CN CN201410110743.4A patent/CN103872023B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6353235B1 (en) * | 1998-11-09 | 2002-03-05 | Mitsubishi Denki Kabushiki Kaisha | Plasma damage detector and plasma damage evaluation method |
| US20020098604A1 (en) * | 1999-12-20 | 2002-07-25 | Taiwan Semiconductor Manufacturing Company | Wafer-level antenna effect detection pattern for VLSI |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105388407A (en) * | 2014-09-09 | 2016-03-09 | 中芯国际集成电路制造(上海)有限公司 | Integrity detection method for gate dielectric layer |
| CN105388407B (en) * | 2014-09-09 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | The integrality detection method of gate dielectric layer |
| CN113497002A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| CN113497002B (en) * | 2020-04-07 | 2024-02-06 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| CN113451276A (en) * | 2021-06-28 | 2021-09-28 | 长江存储科技有限责任公司 | Test structure, test system and test method |
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| CN103872023B (en) | 2016-10-26 |
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