CN105355577A - Plasma damage test structure and manufacturing method thereof - Google Patents
Plasma damage test structure and manufacturing method thereof Download PDFInfo
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- CN105355577A CN105355577A CN201410414962.1A CN201410414962A CN105355577A CN 105355577 A CN105355577 A CN 105355577A CN 201410414962 A CN201410414962 A CN 201410414962A CN 105355577 A CN105355577 A CN 105355577A
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Abstract
The invention discloses a plasma damage test structure. The plasma damage test structure comprises a transistor, an interconnecting layer, a test interconnecting layer, a bonding pad structure and a metal connecting layer, wherein the transistor is arranged in a substrate; the interconnecting layer comprises a first top layer metal layer and a first bottom layer metal layer, and the first bottom layer metal layer and a grid in the transistor are electrically connected; the test interconnecting layer comprises a second top layer metal layer and a second bottom layer metal layer, and is arranged on the substrate; the bonding pad structure comprises a dielectric layer with a through hole and a metal bonding pad arranged in the through hole, and is arranged on the second top layer metal layer; the first end of the metal connecting layer is arranged on the surface of the first top layer metal layer, and the metal connecting layer and the test interconnecting layer are electrically connected. Plasma damage generated in the process of manufacturing the plasma damage test structure is reduced, and thus the plasma damage in the plasma damage test structure is reduced.
Description
Technical field
The application relates to the technical field of semiconductor integrated circuit, in particular to a kind of plasma damage test structure and preparation method thereof.
Background technology
In the manufacturing process of semiconductor chip, usually need to use plasma process to form required device, such as using plasma strengthens chemical vapour deposition (CVD) (PECVD) process deposits dielectric layer or metal level etc., and such as using plasma etching technics etches substrate or dielectric layer etc. again.But, can plasma electric charge be produced in the process of plasma process.If the conductor that have accumulated plasma electric charge is directly connected on the grid of device, the gate oxide between grid and substrate will form grid leakage current.When the electric charge accumulated exceedes some, this electric leakage of the grid fails to be convened for lack of a quorum damage gate oxide, thus the reliability of the even whole chip of device and life-span are seriously reduced.Usually this situation is called plasma damage (PID), is also called antenna effect (PAE).
In order to detect the plasma damage in semiconductor chip fabrication process, usually the wafer comprising plasma damage test structure is placed in the manufacture craft process of semiconductor chip, to detect the plasma damage that semiconductor chip is subject to.Fig. 1 is the schematic diagram of existing plasma damage test structure.As shown in Figure 1, existing plasma damage test structure comprises: be arranged at the transistor 20 ' in substrate 10 ', be arranged at the interconnection layer 30 ' on transistor 20 ', be arranged at the test interconnection layer 40 ' on the surface of substrate 10, and be arranged at the pad structure 50 ' on test interconnection layer 40 '.Wherein, interconnection layer 30 ' is connected by top layer metallic layer with test interconnection layer 40 '; Pad structure 50 ' comprises the dielectric layer 51 ' with through hole and the metal pad 53 ' be arranged in through hole.
In above-mentioned plasma damage test structure, pad structure is formed after formation top layer metallic layer, and the making of pad structure needs using plasma to strengthen chemical vapour deposition (CVD) (PECVD) and plasma etch process, such as using plasma strengthens chemical vapor deposition method and forms dielectric layer, and such as using plasma strengthens chemical vapor deposition method and forms through hole in the dielectric layer again.The plasma electric charge produced in above-mentioned plasma enhanced chemical vapor deposition and plasma etch process can be delivered on the grid of device by top layer metallic layer, thus gate oxide between grid and substrate forms grid leakage current, and then damage gate oxide, the reliability of the even whole chip of plasma damage test structure and life-span are seriously reduced, and makes to adopt accuracy during above-mentioned plasma damage test structure detection plasma damage to reduce.At present, effective solution is not also had for the problems referred to above.
Summary of the invention
The application aims to provide a kind of plasma damage test structure and preparation method thereof, to reduce the plasma damage making and produce in the process of plasma damage test structure, and improves the accuracy adopting plasma damage test structure to detect plasma damage.
To achieve these goals, this application provides a kind of plasma damage test structure, this plasma damage measure structure comprises: transistor, is arranged in substrate; Interconnection layer, comprises the first top layer metallic layer and the first bottom metal layer, is formed and be electrically connected between the first bottom metal layer and the grid in transistor; Test interconnection layer, comprises the second top layer metallic layer and the second bottom metal layer, and test interconnection layer is arranged on substrate; Pad structure, comprise the dielectric layer with through hole and the metal pad be arranged in through hole, pad structure is arranged on the second top layer metallic layer, this plasma damage measure structure also comprises: metal connecting layer, the first end of metal connecting layer is arranged on the surface of the first top layer metallic layer, is formed and be electrically connected between metal connecting layer with test interconnection layer.
Further, in above-mentioned plasma damage test structure, the second end of metal connecting layer is arranged on the surface of the second top layer metallic layer, and the second end of metal connecting layer is connected with dielectric layer.
Further, in above-mentioned plasma damage test structure, plasma damage test structure also comprises: intermediate interconnect layers, comprise the 3rd top layer metallic layer and the 3rd bottom metal layer, intermediate interconnect layers is arranged between interconnection layer and test interconnection layer, and the 3rd bottom metal layer is connected with the second bottom metal layer; Second end of metal connecting layer is arranged on the surface of the 3rd top layer metallic layer, and the second end of metal connecting layer is connected with dielectric layer.
Further, in above-mentioned plasma damage test structure, the material of metal connecting layer is identical with the material of metal pad.
Further, in above-mentioned plasma damage test structure, the material of metal connecting layer and metal pad is aluminium.
Further, above-mentioned plasma damage test structure also comprises: antenna structure, is electrically connected arranges with interconnection layer; And diode, be arranged in substrate, formed between diode with the second bottom metal layer and be electrically connected.
Present invention also provides a kind of manufacture method of plasma damage test structure, this manufacture method comprises the following steps: form transistor in the substrate; Transistor is formed the interconnection layer comprising the first top layer metallic layer and the first bottom metal layer, and on substrate, form the test interconnection layer comprising the second top layer metallic layer and the second bottom metal layer, formed between the first bottom metal layer and the grid in transistor and be electrically connected; Second top layer metallic layer is formed the dielectric layer with through hole; Form metal pad in through-holes, and form first end and be positioned at metal connecting layer on the surface of the first top layer metallic layer, formed between metal connecting layer with test interconnection layer and be electrically connected.
Further, in above-mentioned manufacture method, the step forming metal pad and metal connecting layer comprises: the metal preparation layers forming covering first top layer metallic layer, surface between the first top layer metallic layer and the second top layer metallic layer and dielectric layer and through hole; Etching removes the part metals preparation layers on the surface of dielectric layer, and formation metal pad and the second end are positioned at the metal connecting layer on the surface of the second top layer metallic layer.
Further, in above-mentioned manufacture method, in the step forming interconnection layer and test interconnection layer, between interconnection layer and test interconnection layer, form the intermediate interconnect layers comprising the 3rd top layer metallic layer and the 3rd bottom metal layer, the 3rd bottom metal layer is connected with the second bottom metal layer; Formed in the step of metal pad and metal connecting layer, form the metal preparation layers of covering first top layer metallic layer, the 3rd top layer metallic layer, the surface between the first top layer metallic layer and the 3rd top layer metallic layer, the surface between the 3rd top layer metallic layer and the second top layer metallic layer and dielectric layer and through hole, then etching removes the part metals preparation layers be positioned on the surface of dielectric layer, and formation metal pad and the second end are positioned at the metal connecting layer on the surface of the 3rd top layer metallic layer.
Further, in above-mentioned manufacture method, form the step with the dielectric layer of through hole and comprise: the surface forming covering first top layer metallic layer and the second top layer metallic layer, and the medium preparation layers on surface between the first top layer metallic layer and the second top layer metallic layer; Etch media preparation layers is to form through hole and dielectric layer.
Further, in above-mentioned manufacture method, before the step forming test interconnection layer, form diode in the substrate; In the step forming test interconnection layer, form the second bottom metal layer be connected with diode electrically.
Further, in above-mentioned manufacture method, in the step forming interconnection layer, form the antenna structure be electrically connected with interconnection layer.
The technical scheme of application the application, by first arranging dielectric layer and be arranged in the through hole of dielectric layer on test interconnection layer, the metal connecting layer making interconnection layer and the electrical connection of test interconnection layer is set again, thus the plasma electric charge that the plasma process making the through hole arranging dielectric layer and be arranged in dielectric layer adopt produces can not be delivered on the grid of test structure by interconnection layer, and then decrease the plasma damage making and produce in the process of plasma damage test structure, plasma damage in this plasma damage measure structure is reduced, and improve the accuracy adopting this plasma damage test structure to detect plasma damage.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows the cross-sectional view of existing plasma damage test structure;
Fig. 2 shows the plasma damage test structure cross-sectional view that a kind of preferred implementation of the application provides;
Fig. 3 shows the plasma damage test structure cross-sectional view that the another kind of preferred implementation of the application provides;
Fig. 4 shows the schematic flow sheet of the manufacture method of the plasma damage test structure that the application's execution mode provides;
Fig. 5 shows in the manufacture method of the plasma damage test structure that a kind of preferred implementation of the application provides, and forms the cross-sectional view of the matrix after transistor in the substrate;
Fig. 6 shows the interconnection layer being formed on the transistor shown in Fig. 5 and comprise the first top layer metallic layer and the first bottom metal layer, and on substrate, form the test interconnection layer comprising the second top layer metallic layer and the second bottom metal layer, form the cross-sectional view of the matrix after being electrically connected between the first bottom metal layer with grid in transistor;
Fig. 7 shows the cross-sectional view forming the matrix after having the dielectric layer of through hole on the second top layer metallic layer shown in Fig. 6;
Fig. 7-1 shows the cross-sectional view of the matrix after the medium preparation layers forming the first top layer metallic layer shown in coverage diagram 6, the second top layer metallic layer and the surface between the first top layer metallic layer and the second top layer metallic layer;
Fig. 8 shows and form metal pad in the through hole shown in Fig. 7, and forms first end and be positioned on the surface of the first top layer metallic layer, and the second end is positioned at the cross-sectional view of the matrix after the metal connecting layer on the surface of the second top layer metallic layer;
Fig. 8-1 shows the cross-sectional view of the matrix after the metal preparation layers forming the first top layer metallic layer shown in coverage diagram 7, surface between the first top layer metallic layer and dielectric layer and dielectric layer and through hole;
Fig. 9 shows in the manufacture method of the plasma damage test structure that a kind of preferred implementation of the application provides, and forms the cross-sectional view of the matrix after transistor in the substrate;
Figure 10 shows the interconnection layer being formed on the transistor shown in Fig. 9 and comprise the first top layer metallic layer and the first bottom metal layer, and forms the cross-sectional view of the matrix after comprising the intermediate interconnect layers of the 3rd top layer metallic layer and the 3rd bottom metal layer between interconnection layer and test interconnection layer;
Figure 11 shows the cross-sectional view forming the matrix after having the dielectric layer of through hole on the second top layer metallic layer shown in Figure 10;
Figure 11-1 shows the cross-sectional view of the matrix after forming the medium preparation layers covering the first top layer metallic layer shown in Figure 10, the second top layer metallic layer and the surface between the first top layer metallic layer and the second top layer metallic layer;
Figure 12 shows and form metal pad in the through hole shown in Figure 11, and forms first end and be positioned on the surface of the first top layer metallic layer, and the second end is positioned at the cross-sectional view of the matrix after the metal connecting layer on the surface of the 3rd top layer metallic layer; And
Figure 12-1 shows the cross-sectional view of the matrix after forming the metal preparation layers covering the first top layer metallic layer shown in Figure 11, the 3rd top layer metallic layer, the surface between the first top layer metallic layer and the 3rd top layer metallic layer, the surface between the 3rd top layer metallic layer and the second top layer metallic layer and dielectric layer and through hole.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, make in the process of plasma damage test structure and can produce plasma damage.Present inventor studies for the problems referred to above, proposes a kind of plasma damage test structure.As shown in Figures 2 and 3, this plasma damage measure structure comprises: transistor 20, is arranged in substrate 10; Interconnection layer 30, comprises the first top layer metallic layer 31 and is formed between the first bottom metal layer 33, first bottom metal layer 33 and the grid 21 in transistor 20 and be electrically connected; Test interconnection layer 40, comprises the second top layer metallic layer 41 and the second bottom metal layer 43, and test interconnection layer 40 is arranged on substrate 10; Pad structure 50, comprise the dielectric layer 51 with through hole and the metal pad 53 be arranged in through hole, pad structure 50 is arranged on the second top layer metallic layer 41, this plasma damage measure structure also comprises: metal connecting layer 60, the first end of metal connecting layer 60 is arranged on the surface of the first top layer metallic layer 31, is formed and be electrically connected between metal connecting layer 60 with test interconnection layer 40.
In above-mentioned plasma damage test structure, by first arranging the dielectric layer 51 with through hole on test interconnection layer 40, the metal connecting layer 60 that interconnection layer 30 and test interconnection layer 40 are electrically connected is set again, thus the plasma electric charge that the plasma process making the through hole arranging dielectric layer 51 and be arranged in dielectric layer 51 adopt produces can not be delivered on the grid 21 of test structure by interconnection layer 40, and then decrease the plasma damage making and produce in the process of plasma damage test structure, , plasma damage in this plasma damage measure structure is reduced, and improve the accuracy adopting plasma damage test structure to detect plasma damage.
In above-mentioned plasma damage test structure, forming the mode be electrically connected between metal connecting layer 60 with test interconnection layer 40 has a variety of.In a preferred embodiment, to make to be formed between metal connecting layer 60 with test interconnection layer 40 to be electrically connected on the surface that second end of metal connecting layer 60 is arranged at the second top layer metallic layer 41, and the second end of metal connecting layer 60 is connected with dielectric layer 51, its structure as shown in Figure 2.In another preferred embodiment, above-mentioned plasma damage test structure also comprises: be arranged at the intermediate interconnect layers 70 between interconnection layer 30 and test interconnection layer 40, this intermediate interconnect layers 70 comprises the 3rd top layer metallic layer 71 and the 3rd bottom metal layer 73, and the 3rd bottom metal layer 73 is connected with the second bottom metal layer 43, now the second end of metal connecting layer 60 be arranged at the 3rd top layer metallic layer 71 surface on to make to be formed between metal connecting layer 60 with test interconnection layer 40 to be electrically connected, and the second end of metal connecting layer 60 is connected with dielectric layer 51, its structure as shown in Figure 3.
Above-mentioned interconnection layer 30 also comprises N layer intermediate metal layer (marking two-layer in figure), and test interconnection layer 40 also comprises N layer intermediate metal layer (marking two-layer in figure), and forms isolation by interlayer dielectric layer between each metal level.The material of above-mentioned metal connecting layer 60 and metal pad 53 can be the common metal material in this area.Preferably, the material of metal connecting layer 60 is identical with the material of metal pad 53.More preferably, the material of metal connecting layer 60 and metal pad 53 is aluminium.
Above-mentioned plasma damage test structure can also comprise: be electrically connected the antenna structure 80 arranged with interconnection layer 30, and is arranged at the diode 90 in substrate 10, and is formed between this diode 90 with the second bottom metal layer 43 and be electrically connected.The plasma damage that above-mentioned antenna structure 80 is subject in manufacturing process for detecting semiconductor chip.The plasma produced in above-mentioned plasma damage test structure manufacturing process can be guided away by diode 90.
Present invention also provides a kind of manufacture method of plasma damage test structure.As shown in Figure 4, this manufacture method comprises the following steps: form transistor in the substrate; Transistor is formed the interconnection layer comprising the first top layer metallic layer and the first bottom metal layer, and on substrate, forms the test interconnection layer of the second top layer metallic layer and the second bottom metal layer, formed between the first bottom metal layer with grid in transistor and be electrically connected; Second top layer metallic layer is formed the dielectric layer with through hole; Form metal pad in through-holes, and form first end and be positioned at metal connecting layer on the surface of the first top layer metallic layer, formed between metal connecting layer with test interconnection layer and be electrically connected.
In above-mentioned manufacture method, by first forming dielectric layer and be arranged in the through hole of dielectric layer on test interconnection layer, form the metal connecting layer making interconnection layer and the electrical connection of test interconnection layer again, thus the plasma electric charge that the plasma process making the through hole forming dielectric layer and be arranged in dielectric layer adopt produces can not be delivered on the grid of test structure by interconnection layer, and then decrease the plasma damage making and produce in the process of plasma damage test structure, and improve the accuracy adopting plasma damage test structure to detect plasma damage.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Fig. 5 to Fig. 8 shows in the manufacture method of the plasma damage test structure that a kind of preferred implementation of the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 5 to Fig. 8, further illustrate the manufacture method of the plasma damage test structure that the application's preferred implementation provides.
First, in substrate 10, form transistor 20, and then form basal body structure as shown in Figure 5.Above-mentioned transistor comprises the grid 21 be arranged on substrate 10 surface, is arranged at the side wall layer (not marking in figure) of grid 21 both sides, and is arranged at the source-drain electrode (not marking in figure) in the substrate 10 of grid 21 both sides.The technique forming above-mentioned transistor 20 is state of the art, does not repeat them here.
In the step forming above-mentioned transistor 20, diode 90 can also be formed in substrate 10, form electrical connection with the test interconnection layer 40 with follow-up formation.Above-mentioned diode 90 comprises p type island region and N-type region, and the technique forming above-mentioned diode 90 can set according to prior art.Meanwhile, in the step forming above-mentioned transistor 20, contact hole structure can also be formed to connect with the interconnection layer 30 of follow-up formation on grid 21, and on diode 90, form contact hole structure connect with the test interconnection layer 40 with follow-up formation.
After completing the step forming transistor 20 in substrate 10, transistor 20 shown in Fig. 5 is formed the interconnection layer 30 comprising the first top layer metallic layer 31 and the first bottom metal layer 33, and form the test interconnection layer 40 comprising the second top layer metallic layer 41 and the second bottom metal layer 43 over the substrate 10, formed between first bottom metal layer 33 with grid 21 in transistor 20 and be electrically connected, and then form basal body structure as shown in Figure 6.Above-mentioned interconnection layer 30 also comprises N layer intermediate metal layer (marking two-layer in figure), and test interconnection layer 40 also comprises N layer intermediate metal layer (marking two-layer in figure), and forms isolation by interlayer dielectric layer between each metal level.The method forming above-mentioned interconnection layer 30 and test interconnection layer 40 see prior art, can not repeat them here.Preferably, in the step forming above-mentioned interconnection layer 30, the antenna structure 80 be electrically connected with interconnection layer 30 can also be formed.
Complete the interconnection layer 30 being formed on transistor 20 and comprise the first top layer metallic layer 31 and the first bottom metal layer 33, and after forming the step of the test interconnection layer 40 of the second top layer metallic layer 41 and the second bottom metal layer 43 over the substrate 10, the second top layer metallic layer 41 shown in Fig. 6 is formed the dielectric layer 51 with through hole, and then forms basal body structure as shown in Figure 7.In a preferred embodiment, the step forming above-mentioned through hole and dielectric layer 51 comprises: the surface forming covering first top layer metallic layer 31 and the second top layer metallic layer 41, and the first medium preparation layers 51 ' on surface between top layer metallic layer 31 and the second top layer metallic layer 41, and then form the basal body structure as shown in Fig. 7-1; Etch media preparation layers 51 ' to form through hole and dielectric layer 51, and then forms basal body structure as shown in Figure 7.
The material of above-mentioned medium preparation layers 51 ' can be dielectric material common in this area, such as silicon dioxide or silicon nitride etc.The technique forming above-mentioned medium preparation layers 51 ' can be chemical vapour deposition (CVD) or sputtering etc.The technique etching above-mentioned medium preparation layers 51 ' can be dry etching, is preferably plasma etching.Above-mentioned technique is state of the art, does not repeat them here.It should be noted that, when being formed with the antenna structure 80 be electrically connected with grid 21 on transistor 21, forming the medium preparation layers 51 ' on covering first top layer metallic layer 31, second top layer metallic layer 41 and the surface between the first top layer metallic layer 31 and the second top layer metallic layer 41 in the step forming medium preparation layers 51 ', medium preparation layers 51 ' cover antenna structure 80 (not marking in figure) can also be made.
Complete on the second top layer metallic layer 41 formed there is the step of dielectric layer 51 of through hole after, form metal pad 53 in through-holes, and form that first end is positioned on the surface of the first top layer metallic layer 31, the second end is positioned at metal connecting layer 60 on the surface of the second top layer metallic layer 41, and then forms basal body structure as shown in Figure 8.In a preferred embodiment, the step forming above-mentioned metal pad 53 and metal connecting layer 60 comprises: the surface between formation covering first top layer metallic layer 31, first top layer metallic layer 31 and dielectric layer 51 and the metal preparation layers 60 ' of dielectric layer 51 and through hole, and then forms the basal body structure as shown in Fig. 8-1; Etching removes the part metals preparation layers 60 ' on the surface of dielectric layer 51, to form metal pad 53 and metal connecting layer 60, and then forms basal body structure as shown in Figure 8.
The material of above-mentioned metal preparation layers 60 ' can be metal material common in this area, such as aluminium or copper etc.The technique forming above-mentioned metal preparation layers 60 ' can be chemical vapour deposition (CVD) or sputtering etc.The technique etching above-mentioned metal preparation layers 60 ' can be dry etching, is more preferably plasma etching.Above-mentioned technique is state of the art, does not repeat them here.
Fig. 9 to Figure 12 shows in the manufacture method of the plasma damage test structure that a kind of preferred implementation of the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 9 to Figure 12, further illustrate the manufacture method of the plasma damage test structure that the application's preferred implementation provides.
First, in substrate 10, form transistor 20, and then form basal body structure as shown in Figure 9.Above-mentioned transistor 20 comprises the grid 21 be arranged on substrate 10 surface, is arranged at the side wall layer (not marking in figure) of grid 21 both sides, and is arranged at the source-drain electrode (not marking in figure) in the substrate 10 of grid 21 both sides.The technique forming above-mentioned transistor 20 is state of the art, does not repeat them here.
In the step forming above-mentioned transistor 20, diode 90 can also be formed in substrate 10, form electrical connection with the test interconnection layer 40 with follow-up formation.Above-mentioned diode 90 comprises p type island region and N-type region, and the technique forming above-mentioned diode 90 can set according to prior art.Meanwhile, in the step forming above-mentioned transistor 20, contact hole structure can also be formed to connect with the interconnection layer 30 of follow-up formation on grid 21, and on diode 90, form contact hole structure connect with the test interconnection layer 40 with follow-up formation.
After completing the step forming transistor 20 in substrate 10, transistor 20 shown in Fig. 9 is formed the interconnection layer 30 comprising the first top layer metallic layer 31 and the first underlying metal 33 layers, form the test interconnection layer 40 comprising the second top layer metallic layer 41 and the second underlying metal 43 layers over the substrate 10, and form the intermediate interconnect layers 70 comprising the 3rd top layer metallic layer 71 and the 3rd bottom metal layer 73 between interconnection layer 30 and test interconnection layer 40, and then form basal body structure as shown in Figure 10.Above-mentioned interconnection layer 30 also comprises N layer intermediate metal layer (marking two-layer in figure), test interconnection layer 40 also comprises N layer intermediate metal layer (marking two-layer in figure), intermediate interconnect layers 70 also comprises N layer intermediate metal layer (marking two-layer in figure), and forms isolation by interlayer dielectric layer between each metal level.The method forming above-mentioned interconnection layer 30, test interconnection layer 40 and intermediate interconnect layers 70 see prior art, can not repeat them here.Preferably, in the step forming above-mentioned interconnection layer 30, the antenna structure 80 be electrically connected with interconnection layer 30 can also be formed.
Complete the interconnection layer 30 being formed on transistor 20 and comprise the first top layer metallic layer 31 and the first underlying metal 33 layers, form the test interconnection layer 40 comprising the second top layer metallic layer 41 and the second underlying metal 43 layers over the substrate 10, and after between interconnection layer 30 and test interconnection layer 40, formation comprises the step of the intermediate interconnect layers 70 of the 3rd top layer metallic layer 71 and the 3rd bottom metal layer 73, second top layer metallic layer 41 is formed the dielectric layer 51 with through hole, and then forms basal body structure as shown in figure 11.In a preferred embodiment, the step forming above-mentioned through hole and dielectric layer 51 comprises: the medium preparation layers 51 ' forming covering first top layer metallic layer 31, second top layer metallic layer 41 and the surface between the first top layer metallic layer 31 and the second top layer metallic layer 41, and then forms the basal body structure as shown in Figure 11-1; Etch media preparation layers 51 ' to form through hole and dielectric layer 51, and then forms basal body structure as shown in figure 11.
The material of above-mentioned medium preparation layers 51 ' can be dielectric material common in this area, such as silicon dioxide or silicon nitride etc.The technique forming above-mentioned medium preparation layers 51 ' can be chemical vapour deposition (CVD) or sputtering etc.The technique etching above-mentioned medium preparation layers 51 ' can be dry etching, is preferably plasma etching.Above-mentioned technique is state of the art, does not repeat them here.It should be noted that, when being formed with the antenna structure 80 be electrically connected with grid 21 on transistor 21, forming the medium preparation layers 51 ' on covering first top layer metallic layer 31, second top layer metallic layer 41 and the surface between the first top layer metallic layer 31 and the second top layer metallic layer 41 in the step forming medium preparation layers 51 ', medium preparation layers 51 ' cover antenna structure 80 (not marking in figure) can also be made.
Complete on the second top layer metallic layer 41 formed there is the step of dielectric layer 51 of through hole after, form metal pad 53 in through-holes, and form first end and be positioned on the surface of the first top layer metallic layer 31, second end is positioned at the metal connecting layer 60 on the surface of the 3rd top layer metallic layer 71, and then forms basal body structure as shown in figure 12.In a preferred embodiment, the step forming above-mentioned metal pad 53 and metal connecting layer 60 comprises: the metal preparation layers 60 ' forming the surface between covering first top layer metallic layer the 31, the 3rd top layer metallic layer 71, first top layer metallic layer 31 and the 3rd top layer metallic layer 71, surface between the 3rd top layer metallic layer 71 and the second top layer metallic layer 41 and dielectric layer 51 and through hole, and then forms the basal body structure as shown in Figure 12-1; Etching removes the part metals preparation layers 60 ' be positioned on the surface of dielectric layer 51, forms metal pad 53 and metal connecting layer 60, and then forms basal body structure as shown in figure 12.
The material of above-mentioned metal preparation layers 60 ' can be metal material common in this area, such as aluminium or copper etc.The technique forming above-mentioned metal preparation layers 60 ' can be chemical vapour deposition (CVD) or sputtering etc.The technique etching above-mentioned metal preparation layers 60 ' can be dry etching, is more preferably plasma etching.Above-mentioned technique is state of the art, does not repeat them here.
From above description, can find out, the application's the above embodiments achieve following technique effect: by first arranging dielectric layer and be arranged in the through hole of dielectric layer on test interconnection layer, the metal connecting layer making interconnection layer and the electrical connection of test interconnection layer is set again, thus the plasma electric charge that the plasma process making the through hole arranging dielectric layer and be arranged in dielectric layer adopt produces can not be delivered on the grid of test structure by interconnection layer, and then decrease the plasma damage making and produce in the process of plasma damage test structure, plasma damage in this plasma damage measure structure is reduced, and improve the accuracy adopting this plasma damage test structure to detect plasma damage.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (12)
1. a plasma damage test structure, comprising:
Transistor, is arranged in substrate;
Interconnection layer, comprises the first top layer metallic layer and the first bottom metal layer, and described first bottom metal layer is electrically connected with being formed between the grid in described transistor;
Test interconnection layer, comprise the second top layer metallic layer and the second bottom metal layer, described test interconnection layer is arranged on described substrate;
Pad structure, comprise the dielectric layer with through hole and the metal pad be arranged in described through hole, described pad structure is arranged on described second top layer metallic layer,
It is characterized in that, described plasma damage test structure also comprises:
Metal connecting layer, the first end of described metal connecting layer is arranged on the surface of described first top layer metallic layer, is formed and be electrically connected between described metal connecting layer with described test interconnection layer.
2. plasma damage test structure according to claim 1, is characterized in that, the second end of described metal connecting layer is arranged on the surface of described second top layer metallic layer, and the second end of described metal connecting layer is connected with described dielectric layer.
3. plasma damage test structure according to claim 1, is characterized in that, described plasma damage test structure also comprises:
Intermediate interconnect layers, comprise the 3rd top layer metallic layer and the 3rd bottom metal layer, described intermediate interconnect layers is arranged between described interconnection layer and described test interconnection layer, and described 3rd bottom metal layer is connected with described second bottom metal layer;
Second end of described metal connecting layer is arranged on the surface of described 3rd top layer metallic layer, and the second end of described metal connecting layer is connected with described dielectric layer.
4. plasma damage test structure according to any one of claim 1 to 3, is characterized in that, the material of described metal connecting layer is identical with the material of described metal pad.
5. plasma damage test structure according to claim 4, is characterized in that, the material of described metal connecting layer and described metal pad is aluminium.
6. plasma damage test structure according to claim 1, is characterized in that, described plasma damage test structure also comprises:
Antenna structure, is electrically connected with described interconnection layer and arranges; And
Diode, is arranged in described substrate, is formed and be electrically connected between described diode with described second bottom metal layer.
7. a manufacture method for plasma damage test structure, is characterized in that, described manufacture method comprises the following steps:
Form transistor in the substrate;
Described transistor is formed the interconnection layer comprising the first top layer metallic layer and the first bottom metal layer, and formed over the substrate and comprise the test interconnection layer of the second top layer metallic layer and the second bottom metal layer, described first bottom metal layer is electrically connected with being formed between the grid in described transistor;
Described second top layer metallic layer is formed the dielectric layer with through hole;
In described through hole, form metal pad, and form first end and be positioned at metal connecting layer on the surface of described first top layer metallic layer, formed between described metal connecting layer with described test interconnection layer and be electrically connected.
8. manufacture method according to claim 7, is characterized in that, the step forming described metal pad and described metal connecting layer comprises:
Form the metal preparation layers covering described first top layer metallic layer, surface between described first top layer metallic layer and described second top layer metallic layer and described dielectric layer and described through hole;
Etching removes the described metal preparation layers of part on the surface of described dielectric layer, forms described metal pad and the second end and is positioned at described metal connecting layer on the surface of described second top layer metallic layer.
9. manufacture method according to claim 7, is characterized in that,
In the step forming described interconnection layer and described test interconnection layer, between described interconnection layer and described test interconnection layer, form the intermediate interconnect layers comprising the 3rd top layer metallic layer and the 3rd bottom metal layer, described 3rd bottom metal layer is connected with described second bottom metal layer;
Formed in the step of described metal pad and described metal connecting layer, formed and cover described first top layer metallic layer, described 3rd top layer metallic layer, surface between described first top layer metallic layer and described 3rd top layer metallic layer, surface between described 3rd top layer metallic layer and described second top layer metallic layer and the metal preparation layers of described dielectric layer and described through hole, then etching removes the described metal preparation layers of part be positioned on the surface of described dielectric layer, form described metal pad and the second end and be positioned at described metal connecting layer on the surface of described 3rd top layer metallic layer.
10. the manufacture method according to any one of claim 7 to 9, is characterized in that, forms the step with the described dielectric layer of described through hole and comprises:
Form the surface covering described first top layer metallic layer and described second top layer metallic layer, and the medium preparation layers on surface between described first top layer metallic layer and described second top layer metallic layer;
Etch described medium preparation layers to form described through hole and dielectric layer.
11. manufacture methods according to any one of claim 7 to 9, is characterized in that,
Before the step forming described test interconnection layer, in described substrate, form diode;
In the step forming described test interconnection layer, form described second bottom metal layer be connected with described diode electrically.
12. manufacture methods according to any one of claim 7 to 9, is characterized in that, in the step forming described interconnection layer, form the antenna structure be electrically connected with described interconnection layer.
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