JP2013157540A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of a TSV structure having a desired electrical characteristics.SOLUTION: A semiconductor device includes: a semiconductor substrate 10 having a through hole 15; a first insulating layer 11 formed on a first surface of the semiconductor substrate and having a first opening 18; a first conductive layer 12 formed on the first insulating layer; a second insulating layer 14 formed on a second surface of the semiconductor substrate and having a second opening 23 on the second surface of the through hole; a third insulating layer 16 placed onto and formed by side surfaces of the semiconductor substrate and side surfaces of the second insulating layer connecting to each other, and having a third opening 17; and a second conductive layer 20 placed onto and formed by side surfaces of the second insulating layer, a top surface and side surfaces of the third insulating layer, and side surfaces of the first insulating layer connecting to each other, and being in contact with the first conductive layer. The film thickness of the second insulating layer formed on the second surface of the semiconductor substrate is equal to or thicker than the film thickness of the third insulating layer formed on the side surfaces of the semiconductor substrate.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  In a memory device using a semiconductor integrated circuit, for example, it has been proposed to stack memory chips (semiconductor chips) in multiple stages in order to increase the memory capacity.

  A through-hole penetrating the front and back surfaces of the semiconductor substrate is formed in the semiconductor chip, and a conductive layer is formed in the through-hole. Metal bumps that are electrically connected to the conductive layer are provided on the back surface of the chip, and are electrically connected to the integrated circuit on the chip surface. Metal bumps formed on the back surface of the upper semiconductor chip are bonded to metal pads formed on the surface of the lower semiconductor chip. Thus, the integrated circuit portion of the upper memory chip and the integrated circuit portion of the lower memory chip are electrically connected.

  Such a through connection formed in the semiconductor substrate is called TSV (Through Silicon Via). The TSV is formed by forming a through hole from the back surface of the semiconductor substrate by etching, forming an insulating spacer on the inner surface of the through hole, and then embedding a conductive layer in the through hole.

US Pat. No. 5,229,647 Patent No. 3,186,941 JP 2008-300718 A

  Provided are a semiconductor device and a method for manufacturing the same, which enable formation of a TSV structure having desired electrical characteristics.

  The semiconductor device according to the present embodiment includes a semiconductor substrate, a first insulating layer, a first conductive layer, a second insulating layer, a third insulating layer, and a second conductive layer. The semiconductor substrate has a through-hole penetrating from a first surface to a second surface facing the first surface. The first insulating layer is formed on the first surface of the semiconductor substrate and has a first opening having a smaller diameter than the through hole on the first surface of the through hole. The first conductive layer is formed on the first insulating layer so as to cover the first opening. The second insulating layer is formed on the second surface of the semiconductor substrate, and has a second opening on the second surface of the through hole. The third insulating layer is formed to be connected to the side surface of the semiconductor substrate and the side surface of the second insulating layer, has a third opening portion in contact with the first insulating layer and on the first opening portion. . The second conductive layer is formed on the side surface of the second insulating layer, on the upper surface and side surface of the third insulating layer, and on the side surface of the first insulating layer, and is in contact with the first conductive layer. . The film thickness of the second insulating layer formed on the second surface of the semiconductor substrate is equal to or greater than the film thickness of the third insulating layer formed on the side surface of the semiconductor substrate.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 1st Embodiment. FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 2. FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 3. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 4. FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5. FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 6. Sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment following FIG. FIG. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment, following FIG. 11. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 2nd Embodiment following FIG. Sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment, following FIG. 16. FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment, following FIG. 17. FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment, following FIG. 18. FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment, following FIG. 19.

In TSV, when a silicon oxide film (SiO ₂ film) formed by, for example, a P-CVD (Plasma Chemical Vapor Deposition) method is used as an insulating spacer, the coverage is deteriorated. More specifically, the film thickness is thick on the upper side (the back side of the semiconductor substrate, particularly the corner of the semiconductor substrate) in the through hole, and is thin on the lower side (the surface side of the semiconductor substrate). For this reason, when the insulating spacer is formed with a sufficiently thick film on the lower side (bottom side) in the through hole, a shape projecting toward the inside of the through hole (overhang shape) is formed on the upper side. This makes it difficult to fill the conductive layer thereafter, and voids are formed inside the conductive layer. In addition, when a notch is generated on the bottom side in the through hole, the film thickness becomes insufficient, leading to an increase in parasitic capacitance and a short circuit.

  In order to solve the above problem, a method of forming an insulating layer with good coverage as an insulating spacer of TSV has been proposed. As an insulating layer with good coverage, for example, an organic insulating layer formed by a thermal CVD method can be given. Thereby, an insulating spacer can be made into the shape (conformal shape) with a fixed film thickness in a through-hole.

  However, if a conformal insulating spacer is formed in the through hole, the insulating spacer on the upper side of the through hole is excessively removed when the insulating spacer on the bottom side of the through hole is removed. Further, when the insulating layer on the bottom side of the TSV is opened, the insulating spacer on the upper side of the through hole is further removed. Thereby, the film thickness of the insulating spacer on the upper side of the through hole becomes insufficient, and a leak current is generated between the corner portion of the semiconductor substrate and the conductive layer, or a breakdown voltage characteristic failure occurs. By adding a lithography process, the insulating spacer at the bottom of the through hole can be removed, but the process cost increases.

  As described above, in TSV, it is difficult to form a shape having desired electrical characteristics.

  On the other hand, the present embodiment solves the above problem by forming the insulating spacer on the upper side of the through hole sufficiently thick.

  The present embodiment will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals. In addition, redundant description will be given as necessary.

<First Embodiment>
The semiconductor device (TSV) according to the first embodiment will be described with reference to FIGS. The first embodiment is an example in which the thickness of the insulating spacer (third insulating layer 16) in the vicinity of the corner of the semiconductor substrate 10 is increased by increasing the thickness of the second insulating layer 14 serving as a hard mask. is there. Thereby, the shortest distance of the corner | angular part of the semiconductor substrate 10 and the 2nd conductive layer 20 can be enlarged, and deterioration of the electrical property in TSV can be suppressed. Hereinafter, the first embodiment will be described in detail.

[Structure of First Embodiment]
First, the structure of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device includes a semiconductor substrate 10, a first insulating layer 11, a first conductive layer 12, a wiring layer 13, a second insulating layer 14, a third insulating layer 16, a second conductive layer 20, and A bump electrode 22 is provided.

  The semiconductor substrate 10 is a silicon substrate, for example. The semiconductor substrate 10 has a through hole 15 penetrating from the first surface (front surface) to the second surface (back surface) facing the first surface. The planar shape of the through hole 15 is, for example, a circle, and the diameter thereof is, for example, about several μm to several tens of μm. The planar shape of the through hole 15 is not limited to this, and may be an ellipse, a rectangle, or the like. Moreover, the film thickness of the semiconductor substrate 10 is about 10-100 micrometers.

  The first insulating layer 11 is formed on the first surface of the semiconductor substrate 10. The first insulating layer 11 has an opening 18 having a smaller diameter than the through hole 15 on the first surface of the through hole 15. The planar shape of the opening 18 is, for example, a circle, but is not limited thereto, and may be an ellipse, a rectangle, or the like. Further, the opening 18 and the through hole 15 are, for example, concentric in a plane. The first insulating layer 11 is made of, for example, silicon oxide.

  The first conductive layer 12 is formed on the first insulating layer 11. The first conductive layer 12 is formed so as to cover the opening 18 of the first insulating layer 11. The first conductive layer 12 is made of, for example, polysilicon or Ni silicide.

  The wiring layer 13 is formed on the first conductive layer 12. The wiring layer 13 is made of a metal material such as Cu, Al, Ti, or W, for example.

  The first insulating layer 11, the first conductive layer 12, the wiring layer 13, and a transistor (not shown) formed on the first surface of the semiconductor substrate 10 constitute an element and an integrated circuit. Thereby, a semiconductor device such as a memory or an image sensor is formed.

The second insulating layer 14 is formed on the second surface of the semiconductor substrate 10. The second insulating layer 14 has an opening 23 having the same shape as the through hole 15 on the second surface of the through hole 15. The second insulating layer 14 is formed of a single layer film or a laminated film such as silicon oxide or silicon nitride (SiN _x ).

  The third insulating layer 16 is formed on the semiconductor substrate 10 in the through hole 15 and on the second insulating layer 14 in the opening 23. In other words, the third insulating layer 16 is formed so as to be connected to the side surface of the semiconductor substrate 10 and the side surface of the second insulating layer 14. The third insulating layer 16 is formed in contact with the upper surface of the first insulating layer 11, and has the opening 17 having the same shape as the opening 18 on the opening 18.

  Detailed configurations and film thickness regulations of the second insulating layer 14 and the third insulating layer 16 in the present embodiment will be described later.

  The second conductive layer 20 is formed on the barrier metal on the third insulating layer 16 in the through hole 15, the second opening 23, and the third opening 17, and on the first insulating layer 11 in the opening 18. 19 are connected through 19. In other words, the second conductive layer 20 is formed on the side surface and the upper surface of the third insulating layer 16. The second conductive layer 20 is formed in contact with the first conductive layer 12 through the barrier metal 19 on the bottom surface of the opening 18 and is electrically connected to a circuit formed on the first surface of the semiconductor substrate 10. Is done.

  In the drawing, the second conductive layer 20 is formed by being embedded in the through hole 15, the opening 23, the opening 17, and the opening 18. It may be formed only on the top.

  The second conductive layer 20 is made of, for example, Cu. The barrier metal 19 is formed of a film that can suppress the diffusion of the second conductive layer 20 such as Ti, TiN, Ta, or TaN.

  The bump electrode 22 is formed on the second surface of the through hole 15 via the barrier metal 21. That is, the bump electrode 22 is formed in contact with the second conductive layer 20 via the barrier metal 21. Thereby, the bump electrode 22 is electrically connected to a circuit formed on the first surface of the semiconductor substrate 10 via the second conductive layer 20.

  In the present embodiment, the third insulating layer 16 is formed only on the side surface of the second insulating layer 14 outside the through hole 15. That is, the upper surface of the third insulating layer 16 (a surface parallel to the first surface and the second surface) is less than or equal to the height of the upper surface of the second insulating layer 14. In other words, the third insulating layer 16 is formed on the side surface of the second insulating layer 14 at least at a part on the lower side of the opening 23.

  In the drawing, the third insulating layer 16 has a side surface and an upper surface that are curved (having a curved surface) outside the through-hole 15. You may be connected. Further, the third insulating layer 16 may be connected outside the through-hole 15 by a slope formed between the side surface and the upper surface. In the following description, the curved surface is shown as a part of the side surface.

Further, the third insulating layer 16 is formed so that the film thickness W1 (dimension in the direction parallel to the first surface and the second surface) is substantially constant (conformal) at least on the semiconductor substrate 10 in the through hole 15. The The film thickness W1 of the third insulating layer 16 is, for example, about 500 nm. However, the thickness is not limited to this, and may be as long as no leakage current occurs between the semiconductor substrate 10 and the second conductive layer 20. The conformal third insulating layer 16 is made of an organic insulator such as polyimide or BCB. However, the present invention is not limited to this. For example, silicon oxide, silicon nitride, SiOF (Fluorine-Doped SiO ₂ ), porous SiOC (Carbon-Doped SiO ₂ ), or the like may be used.

  Here, the film thickness is substantially constant (conformal), with respect to the minimum film thickness A and the maximum film thickness B on the side surface between the first surface and the second surface of the semiconductor substrate 10, | (A− B) / (A + B) | represents a state in which the film thickness uniformity represented by |

  On the other hand, outside the through hole 15, a corner portion on the second surface of the semiconductor substrate 10 (a corner portion connecting the second surface of the semiconductor substrate 10 and the side surface of the semiconductor substrate 10, hereinafter simply referred to as a corner portion of the semiconductor substrate 10). The film thickness of the third insulating layer 16 formed in the vicinity (for example, the third insulating layer 16 formed on the side surface of the second insulating layer 14) is the film thickness W2 of the second insulating layer 14 serving as a hard mask ( The thickness can be increased by increasing the dimension in the direction perpendicular to the first surface and the second surface. That is, by increasing the film thickness W2 of the second insulating layer 14, the shortest distance W3 between the corner portion of the semiconductor substrate 10 and the second conductive layer 20, and the second portion located immediately above the corner portion of the semiconductor substrate 10 and the corner portion thereof. The distance W4 from the conductive layer 20 (or the bump electrode 22) can be increased.

  More specifically, the film thickness W2 of the second insulating layer 14 is desirably equal to or greater than the film thickness W1 of the third insulating layer 16 formed on the side surface of the semiconductor substrate 10. Thereby, it is possible to prevent the second surface of the semiconductor substrate 10 from being exposed and coming into contact with the second conductive layer 20 or the bump electrode 22 to cause a short circuit. Further, the distance W4 between the corner portion of the semiconductor substrate 10 and the second conductive layer 20 (or the bump electrode 22) located immediately above the corner portion can be increased, and the leakage current can be suppressed.

  The shortest distance W3 between the corner of the semiconductor substrate 10 and the second conductive layer 20 is desirably greater than or equal to the film thickness W1 of the third insulating layer 16. Thereby, the leakage current between the corner | angular part of the semiconductor substrate 10 and the 2nd conductive layer 20 nearest to this can be suppressed. For this reason, for example, it is desirable to set the film thickness W2 of the second insulating layer 14 to at least twice the film thickness W1 of the third insulating layer 16.

  The film thicknesses and the like are not limited to the above, but may be specified to such an extent that no leak current is generated between the semiconductor substrate 10 and the second conductive layer 20 (or the bump electrode 22).

[Production Method of First Embodiment]
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 2 to 7 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment.

  First, as shown in FIG. 2, a first insulating layer 11 is formed on a first surface of a semiconductor substrate 10 made of, for example, a silicon substrate. The first insulating layer 11 is, for example, an interelectrode insulating layer in a circuit and is made of silicon oxide. The film thickness of the first insulating layer 11 is, for example, about 300 nm. A first conductive layer 12 and a wiring layer 13 are sequentially formed on the first insulating layer 11 (on the lower surface in the drawing). The first conductive layer 12 is made of, for example, polysilicon or Ni silicide, and the wiring layer 13 is made of, for example, a metal material such as Cu, Al, Ti, or W. The first insulating layer 11, the first conductive layer 12, the wiring layer 13, and a transistor (not shown) constitute an element and an integrated circuit.

  Next, the first surface side of the semiconductor substrate 10 is bonded to a support substrate (not shown) with an adhesive or the like. Thereafter, the semiconductor substrate 10 is ground from the second surface side, and the film thickness is adjusted to about 10 to 100 μm, for example. In addition, the following processes are performed in the state in which the 1st surface side of the semiconductor substrate 10 was bonded by the support substrate.

  Next, a second insulating layer 14 serving as a hard mask is formed on the second surface of the semiconductor substrate 10. The second insulating layer 14 is composed of a single layer film or a laminated film such as silicon oxide or silicon nitride. The film thickness of the second insulating layer 14 is, for example, about 500 nm to 1 μm, but is not limited thereto. The film thickness of the second insulating layer 14 to be formed is adjusted so that the film thickness exceeding the film thickness of the third insulating layer 16 finally remains in consideration of the etching selectivity in the etching process of various layers to be described later. It is desirable that

  Next, a resist (not shown) is formed on the second insulating layer 14, and the second insulating layer 14 is etched by lithography and RIE (Reactive Ion Etching), for example. As a result, the opening 23 is formed in the second insulating layer 14, and the second surface of the semiconductor substrate 10 is exposed at the bottom surface of the opening 23.

  Next, the semiconductor substrate 10 is etched by, for example, RIE using the second insulating layer 14 or a resist (not shown) as a mask. Thereby, the through hole 15 penetrating from the second surface to the first surface of the semiconductor substrate 10 is formed. Further, the first insulating layer 11 is exposed at the bottom surface of the through hole 15. Thereafter, the resist (not shown) is removed.

  Next, as shown in FIG. 3, the third insulating layer 16 is formed so as to cover the entire surface. More specifically, the third insulating layer 16 is connected to the first insulating layer 11 in the through hole 15, the semiconductor substrate 10 in the through hole 15, and the second insulating layer 14 outside the through hole 15. Formed. In other words, the third insulating layer 16 is formed on the exposed upper surface of the first insulating layer 11, on the side surface of the semiconductor substrate 10, on the side surface and on the upper surface of the second insulating layer 14.

  At this time, the third insulating layer 16 is a film with good coverage, and the film thickness is formed to be substantially constant (conformal). The film thickness W1 of the third insulating layer 16 is, for example, about 500 nm. However, the thickness is not limited to this, and may be as long as no leakage current occurs between the semiconductor substrate 10 and the second conductive layer 20 described later.

  The conformal third insulating layer 16 is made of, for example, an organic insulator such as polyimide or BCB formed by a thermal CVD method. However, it is not limited to the thermal CVD method, and may be formed by, for example, a sputtering method, a vapor deposition method, a spin coating method, a spray coating method, or an ALD (Atomic Layer Deposition) method. Moreover, it is not limited to an organic insulator, and may be composed of silicon oxide, silicon nitride, SiOF, porous SiOC, or the like formed by the above method. In this example, a case where an organic insulator is used will be described.

Next, as shown in FIG. 4, the third insulating layer 16 (the third insulating layer 16 on the upper surface of the first insulating layer 11) located on the bottom surface in the through hole 15, for example, by Ar / O ₂ plasma etching Are etched away. Thus, an opening 17 having a smaller diameter than the through hole 15 is formed in the third insulating layer 16 located on the bottom surface in the through hole 15. Further, the first insulating layer 11 is exposed at the bottom surface of the opening 17.

  At this time, the third insulating layer 16 formed on the upper surface of the second insulating layer 14 is also etched. The third insulating layer 16 formed on the upper side of the through hole 15 (opening 23) has a higher etching rate than the third insulating layer 16 formed on the bottom side. For this reason, the third insulating layer 16 on the upper side is etched more than the thickness of the third insulating layer 16 on the removed bottom side. As a result, not only the third insulating layer 16 formed on the upper surface of the second insulating layer 14 but also the third insulating layer 16 formed on the upper side surface of the second insulating layer 14 is partially etched. Removed.

  Depending on the material constituting the third insulating layer 16, the second insulating layer 14 is also etched. More specifically, the film thickness of the second insulating layer 14 to be etched is calculated by the etching selectivity with the third insulating layer 16 and the film thickness of the third insulating layer 16 to be etched. In this example, since the third insulating layer 16 is made of an organic insulator, the second insulating layer 14 made of silicon oxide or silicon nitride is hardly etched.

  Next, as shown in FIG. 5, the exposed first insulating layer 11 is removed by CF plasma etching. As a result, an opening 18 having the same diameter as the opening 17 is formed in the first insulating layer 11. Further, the first conductive layer 12 is exposed at the bottom surface of the opening 18.

  At this time, the second insulating layer 14 is also etched. More specifically, the film thickness of the second insulating layer 14 to be etched is calculated by the etching selectivity with the first insulating layer 11 and the film thickness of the first insulating layer 11 to be etched.

  Depending on the material constituting the third insulating layer 16, the third insulating layer 16 is also etched. More specifically, the film thickness of the third insulating layer 16 to be etched is calculated by the etching selectivity with respect to the first insulating layer 11 and the film thickness of the first insulating layer 11 to be etched. In this example, since the third insulating layer 16 is made of an organic insulator, the third insulating layer 16 is hardly etched even if the first insulating layer 11 made of silicon oxide is etched.

  As described above, as shown in the steps of FIGS. 4 and 5, the third insulating layer 16 (for example, the third insulating layer 16 on the side surface of the second insulating layer 14) remaining in the vicinity of the corner of the semiconductor substrate 10. The film thickness is determined by the film thickness of the remaining second insulating layer 14. That is, the shortest distance W3 between the corner of the semiconductor substrate 10 and the second conductive layer 20 described later, and the distance W4 between the corner of the semiconductor substrate 10 and the second conductive layer 20 (or the bump electrode 22) positioned immediately above the corner. Is determined by the film thickness of the second insulating layer 14.

  Next, as shown in FIG. 6, a varimetal 19 is formed so as to cover the entire surface by, for example, sputtering, CVD, or vapor deposition. More specifically, the varimetal 19 is formed on the second insulating layer 14 outside the opening 23, on the second insulating layer 14 and the third insulating layer 16 in the opening 23, and on the third insulating layer in the through hole 15. 16, on the third insulating layer 16 in the opening 17, on the first insulating layer 11 in the opening 18, and on the first conductive layer 12. In other words, the barrier metal 19 is on the upper surface and side surface of the second insulating layer 14, on the upper surface and side surface of the third insulating layer 16, on the upper surface of the first insulating layer 11, and on the upper surface of the first conductive layer 12. Formed. The varimetal 19 is made of, for example, TiN or Ti. The film thickness of the barrier metal 19 is, for example, about 5 to 200 nm.

  Next, the second conductive layer 20 is formed on the barrier metal 19 by, for example, a plating technique. As a result, the second conductive layer 20 is embedded in the through hole 15 and in the openings 17, 18, and 23. For this reason, the second conductive layer 20 is formed in contact with the first conductive layer 12 through the barrier metal 19 on the bottom surface of the opening 18, and is electrically connected to the circuit formed on the first surface of the semiconductor substrate 10. Connected. The second conductive layer 20 is also formed outside the opening 23. The second conductive layer 20 is made of Cu, for example.

  At this time, as described above, the shortest distance W3 between the corner of the semiconductor substrate 10 outside the through hole 15 and the second conductive layer 20 is greater than or equal to the film thickness W1 of the third insulating layer 16 on the semiconductor substrate 10. It is desirable to become. That is, the film thickness W2 of the second insulating layer 14 is desirably equal to or greater than the film thickness W1 of the third insulating layer 16, and more desirably equal to or greater than twice the film thickness W1 of the third insulating layer 16.

  Next, as shown in FIG. 7, the excessive second conductive layer 20 and the barrier metal 19 formed outside the opening 23 are removed by, for example, CMP (Chemical Mechanical Polishing). Thereby, the upper surfaces of the second insulating layer 14, the second conductive layer 20, and the barrier metal 19 are planarized.

  Thereafter, as shown in FIG. 1, for example, a barrier metal 21 made of Ti or TiN and a bump electrode made of Cu so as to be in contact with the second conductive layer 20 by a sputtering method, a CVD method, or a plating technique. 22 is formed. Thereby, the bump electrode 22 is electrically connected to a circuit formed on the first surface of the semiconductor substrate 10 via the second conductive layer 20.

  In this way, the TSV according to the first embodiment is formed.

[Effect of the first embodiment]
According to the first embodiment, the second insulating layer 14 serving as a hard mask is formed thicker. More specifically, the film thickness W2 of the second insulating layer 14 is set to be equal to or greater than the film thickness W1 of the third insulating layer 16 serving as a conformal insulating spacer. Thereby, the film thickness of the 3rd insulating layer 16 formed in the corner | angular part (corner | corner part of the semiconductor substrate 10) vicinity of the through-hole 15 can be thickened. That is, the distance between the corner of the semiconductor substrate 10 and the second conductive layer 20 can be increased, and the leakage current therebetween can be suppressed. Therefore, a TSV structure having desired electrical characteristics can be formed.

  In the first embodiment, when the third insulating layer 16 at the bottom of the through hole 15 is removed, it can be performed without adding a new lithography process. That is, the above structure can be realized while suppressing an increase in process cost.

<Second Embodiment>
A semiconductor device according to the second embodiment will be described with reference to FIGS. In the first embodiment, the shortest distance between the corner of the semiconductor substrate 10 and the second conductive layer 20 is increased by increasing the thickness of the second insulating layer 14. On the other hand, in the second embodiment, the conformal fourth insulating layer 26 and the overhanging fifth insulating layer 30 are sequentially formed as insulating spacers. In this example, the insulating spacer (at least the fourth insulating layer 26) is left on the upper surface of the second insulating layer 14, thereby increasing the shortest distance between the corner of the semiconductor substrate 10 and the second conductive layer 20. is there. The second embodiment will be described in detail below.

  Note that in the second embodiment, description of the same points as in the first embodiment will be omitted, and different points will be mainly described.

[Structure of Second Embodiment]
First, the structure of the semiconductor device according to the second embodiment will be described with reference to FIG. FIG. 8 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

  As shown in FIG. 8, the second embodiment is different from the first embodiment in that the fourth insulating layer 26 that is a TSV insulating spacer is not only on the side surface of the second insulating layer 14 but also on the upper surface. It is also a point that is formed.

  More specifically, the fourth insulating layer 26 is formed on the semiconductor substrate 10 in the through hole 15, on the second insulating layer 14 in the opening 23, and on the second insulating layer 14 outside the opening 23. The In other words, the fourth insulating layer 26 is formed on the side surface of the semiconductor substrate 10, on the side surface of the second insulating layer 14, and on the upper surface of the second insulating layer 14.

  Further, the fourth insulating layer 26 is formed so that the film thickness W1 is substantially constant (conformal) at least on the semiconductor substrate 10 in the through hole 15. The film thickness W5 of the fourth insulating layer 26 is, for example, about 500 nm. However, the thickness is not limited to this, and may be as long as no leak current is generated between the semiconductor substrate 10 and the second conductive layer 20. The conformal fourth insulating layer 26 is made of an organic insulator such as polyimide or BCB. However, the present invention is not limited to this, and may be made of, for example, silicon oxide, silicon nitride, SiOF, porous SiOC, or the like.

  On the other hand, the thickness of the fourth insulating layer 26 formed in the vicinity of the corner of the semiconductor substrate 10 outside the through hole 15 is the second insulating layer 14 and the second insulating layer 14 formed on the second insulating layer 14 serving as a hard mask. By increasing the integrated film thickness W6 of the four insulating layers 26, the thickness can be increased. That is, by increasing the integrated film thickness W6 of the second insulating layer 14 and the fourth insulating layer 26 formed on the second surface of the semiconductor substrate 10, the corner portions of the semiconductor substrate 10 and the second conductive layer 20 are increased. The shortest distance W7 and the distance W8 between the corner of the semiconductor substrate 10 and the bump electrode 22 (or the second conductive layer 20) located immediately above the corner can be increased.

  More specifically, the integrated film thickness W6 of the second insulating layer 14 and the fourth insulating layer 26 formed on the second surface of the semiconductor substrate 10 is the fourth insulating layer formed on the side surface of the semiconductor substrate 10. It is desirable that the thickness is 26 or more. Thereby, it is possible to prevent the second surface of the semiconductor substrate 10 from being exposed and coming into contact with the second conductive layer 20 or the bump electrode 22 to cause a short circuit. Further, the distance W8 between the corner portion of the semiconductor substrate 10 and the bump electrode 22 (or the second conductive layer 20) located immediately above the corner portion can be increased, and the leakage current can be suppressed.

  The shortest distance W7 between the corner of the semiconductor substrate 10 and the second conductive layer 20 is desirably greater than or equal to the film thickness W5 of the fourth insulating layer 26. Thereby, the leakage current between the corner | angular part of the semiconductor substrate 10 and the 2nd conductive layer 20 which adjoins most can be suppressed. For this reason, for example, the integrated film thickness W6 of the second insulating layer 14 and the fourth insulating layer 26 formed on the second surface of the semiconductor substrate 10 is set to be twice or more the film thickness W5 of the fourth insulating layer 26. It is desirable.

[Manufacturing Method of Second Embodiment]
Next, a manufacturing method of the semiconductor device according to the second embodiment will be described with reference to FIGS. 9 to 14 are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment.

  First, as shown in FIG. 9, the first insulating layer 11, the first conductive layer 12, and the wiring layer 13 are sequentially formed on the first surface of the semiconductor substrate 10 as in the first embodiment. Thereafter, after the first surface side of the semiconductor substrate 10 is bonded to a support substrate (not shown) with an adhesive or the like, the semiconductor substrate 10 is ground from the second surface side, and the film thickness is adjusted to about 10 to 100 μm, for example. The

  Next, a second insulating layer 14 serving as a hard mask is formed on the second surface of the semiconductor substrate 10. The second insulating layer 14 is composed of a single layer film or a laminated film such as silicon oxide or silicon nitride. The film thickness of the second insulating layer 14 may be smaller than the film thickness of the second insulating layer 14 in the first embodiment, and is formed, for example, about 50 to 500 nm, but is not limited thereto.

  Next, a resist (not shown) is formed on the second insulating layer 14, and the second insulating layer 14 is etched by lithography and RIE, for example. As a result, the opening 23 is formed in the second insulating layer 14, and the second surface of the semiconductor substrate 10 is exposed at the bottom surface of the opening 23.

  Next, the semiconductor substrate 10 is etched by, for example, RIE using the second insulating layer 14 or a resist (not shown) as a mask. Thereby, the through hole 15 penetrating from the second surface to the first surface of the semiconductor substrate 10 is formed. Further, the first insulating layer 11 is exposed at the bottom surface of the through hole 15. Thereafter, the resist (not shown) is removed.

  Next, as shown in FIG. 10, a fourth insulating layer 26 is formed so as to cover the entire surface. More specifically, the fourth insulating layer 26 is formed on the first insulating layer 11 in the through hole 15, on the semiconductor substrate 10 in the through hole 15, and on the second insulating layer 14 outside the through hole 15. Is done. In other words, the fourth insulating layer 26 is formed on the exposed upper surface of the first insulating layer 11, on the side surface of the semiconductor substrate 10, on the side surface and on the upper surface of the second insulating layer 14.

  At this time, the fourth insulating layer 26 is formed with a substantially constant film thickness (conformal). The film thickness of the fourth insulating layer 26 is, for example, about 500 nm, but is not limited thereto, and may be thick enough to prevent leakage current between the semiconductor substrate 10 and the second conductive layer 20 described later.

  The conformal fourth insulating layer 26 is made of, for example, an organic insulator such as polyimide or BCB formed by a thermal CVD method. However, it is not limited to the thermal CVD method, and may be formed by, for example, a sputtering method, a vapor deposition method, a spin coating method, a spray coating method, or an ALD method. Moreover, it is not limited to an organic insulator, and may be composed of silicon oxide, silicon nitride, SiOF, porous SiOC, or the like formed by the above method. In this example, a case where an organic insulator is used will be described.

  Next, as shown in FIG. 11, the fifth insulating layer 30 is formed so as to cover the entire surface. More specifically, the fifth insulating layer 30 is formed continuously on the fourth insulating layer 26 inside and outside the through hole 15. In other words, the fifth insulating layer 30 is formed on the top surface, the side surface, and the bottom surface of the fourth insulating layer 26.

  At this time, the fifth insulating layer 30 is a film with poor coverage, and is formed so as to protrude toward the inside of the through hole 15 (overhang) with a large film thickness on the upper side. The film thickness of the fifth insulating layer 30 is, for example, about 500 nm on the upper surface of the fourth insulating layer 26 outside the through hole 15. The film thickness of the fifth insulating layer 30 is about ½ on the side surface and the bottom surface of the fourth insulating layer 26 in the through hole 15 and on the upper surface of the fourth insulating layer 26 outside the through hole 15. For example, it is about 250 nm.

  The overhanging fifth insulating layer 30 is made of, for example, silicon oxide formed by a P-CVD method. However, it is not limited to the P-CVD method, and may be formed by, for example, a sputtering method, a vapor deposition method, a spin coating method, a spray coating method, or an ALD method. Moreover, it is not limited to silicon oxide, and may be composed of silicon nitride, SiOF, porous SiOC, or an organic insulator such as polyimide or BCB formed by the above method. In this example, a case where silicon oxide is used will be described.

  Here, the overhanging film is a film on the side surface at a position that is 1/2 (central part) in the through-hole axial direction (perpendicular to the first surface and the second surface) of the semiconductor substrate 10. With respect to the thickness C, the film thickness increases toward the second surface (generally gradually increases), decreases toward the first surface (generally gradually decreases), and is located at the position of the second surface of the semiconductor substrate 10. The state where the film thickness D on the side surface is twice or more the film thickness C is shown.

  Next, as shown in FIG. 12, the fifth insulating layer 30 located on the bottom surface in the through hole 15 is etched and removed by, for example, CF-based plasma etching. Thereby, the fourth insulating layer 26 is exposed on the bottom surface in the through hole 15.

  At this time, the fifth insulating layer 30 formed on the upper side (outside the through hole 15) is also etched. The fifth insulating layer 30 formed on the upper side has a higher etching rate than the fifth insulating layer 30 formed on the bottom side. For this reason, the fifth insulating layer 30 on the upper side is etched more than the thickness of the etched fifth insulating layer 30 on the bottom side. However, since the fifth insulating layer 30 is an overhanging film on the upper side, even if the etching rate is high, it is not completely removed and remains. That is, the fourth insulating layer 26 remains covered with the fifth insulating layer 30 except for the bottom side.

Next, the fourth insulating layer 26 exposed at the bottom surface of the through hole 15 is etched and removed by, for example, Ar / O ₂ plasma etching. Thereby, an opening 17 having a smaller diameter than the through hole 15 is formed in the fourth insulating layer 26 located on the bottom surface in the through hole 15. Further, the first insulating layer 11 is exposed at the bottom surface of the opening 17.

  At this time, the upper surface and side surfaces of the fourth insulating layer 26 formed on the upper surface of the second insulating layer 14 are covered with the fifth insulating layer 30. For this reason, the fourth insulating layer 26 located on the upper side is not etched. In this example, since the fourth insulating layer 26 is made of an organic insulator, the fifth insulating layer 30 made of silicon oxide is hardly etched.

  Next, as shown in FIG. 13, the exposed first insulating layer 11 is etched away by CF-based plasma etching. As a result, an opening 18 having the same diameter as the opening 17 is formed in the first insulating layer 11. Further, the first conductive layer 12 is exposed at the bottom surface of the opening 18.

  At this time, the fifth insulating layer 30 formed on the fourth insulating layer 26 is also etched. More specifically, the film thickness of the fifth insulating layer 30 to be etched is calculated by the etching selectivity with the first insulating layer 11 and the film thickness of the first insulating layer 11 to be etched. Thereby, all of the fifth insulating layer 30 may be removed or may remain.

  Note that when the fifth insulating layer 30 is completely removed and the fourth insulating layer 26 is exposed, the fourth insulating layer 26 is also partially etched depending on the material constituting the fourth insulating layer 26. More specifically, the thickness of the fourth insulating layer 26 to be etched is determined by the etching selectivity with respect to the first insulating layer 11 and the film of the first insulating layer 11 that is etched after the fourth insulating layer 26 is exposed. Calculated by thickness. In this example, since the fourth insulating layer 26 is made of an organic insulator, the fourth insulating layer 26 is hardly etched even if the first insulating layer 11 made of silicon oxide is etched.

  Thus, by forming the overhanging fifth insulating layer 30 on the conformal fourth insulating layer 26, the fourth insulating layer 26 is formed on the side surface of the semiconductor substrate 10 and on the side surface of the second insulating layer 14. And on the top surface, it remains in a conformal shape. That is, the fourth insulating layer 26 maintains a conformal shape in the vicinity of the corner of the semiconductor substrate 10 and has a sufficient film thickness.

  Next, as shown in FIG. 14, a varimetal 19 is formed so as to cover the entire surface by, for example, sputtering, CVD, or vapor deposition. More specifically, the varimetal 19 is formed continuously on the fourth insulating layer 26 inside and outside the through hole 15. In other words, the varimetal 19 is formed on the side surface and the upper surface of the fourth insulating layer 26.

  Next, the second conductive layer 20 is formed on the barrier metal 19 by, for example, a plating technique. As a result, the second conductive layer 20 is embedded in the through hole 15 and in the openings 17, 18, and 23. For this reason, the second conductive layer 20 is formed in contact with the first conductive layer 12 through the barrier metal 19 on the bottom surface of the opening 18, and is electrically connected to the circuit formed on the first surface of the semiconductor substrate 10. Connected. The second conductive layer 20 is also formed outside the opening 23. The second conductive layer 20 is made of Cu, for example.

  At this time, as described above, the shortest distance W7 between the corner of the semiconductor substrate 10 outside the through hole 15 and the second conductive layer 20 is greater than or equal to the film thickness W5 of the fourth insulating layer 26 on the semiconductor substrate 10. It is desirable to become. That is, it is desirable that the integrated film thickness W6 of the second insulating layer 14 and the fourth insulating layer 26 formed on the second surface of the semiconductor substrate 10 is equal to or greater than the film thickness W5 of the fourth insulating layer 26. It is more desirable that the thickness be at least twice the thickness W5 of the layer 26.

  Next, excess second conductive layer 20 and barrier metal 19 formed on the upper surface of fourth insulating layer 26 are removed by, for example, CMP. Thereby, the upper surfaces of the fourth insulating layer 26, the second conductive layer 20, and the barrier metal 19 are planarized.

  Thereafter, as shown in FIG. 8, for example, a barrier metal 21 made of Ti or TiN and a bump electrode made of Cu so as to be in contact with the second conductive layer 20 by sputtering, CVD, or plating technology. 22 is formed. Thereby, the bump electrode 22 is electrically connected to a circuit formed on the first surface of the semiconductor substrate 10 via the second conductive layer 20.

  In this way, the TSV according to the second embodiment is formed.

[Effects of Second Embodiment]
According to the second embodiment, the conformal fourth insulating layer 26 and the overhanging fifth insulating layer 30 are sequentially formed as insulating spacers. As a result, the fourth insulating layer 26 serving as an insulating spacer is formed over the side surface of the semiconductor substrate 10, the side surface of the second insulating layer 14, and the upper surface of the second insulating layer 14. Then, the integrated film thickness W6 of the second insulating layer 14 and the fourth insulating layer 26 formed on the second surface of the semiconductor substrate 10 is set to the film thickness W5 of the fourth insulating layer 26 formed on the side surface of the semiconductor substrate 10. Set to above. Thereby, the film thickness of the 4th insulating layer 26 formed in the corner | angular part (corner | corner part of the semiconductor substrate 10) vicinity of the through-hole 15 can be thickened. That is, the distance between the corner of the semiconductor substrate 10 and the second conductive layer 20 can be increased, and the same effect as in the first embodiment can be obtained.

<Third Embodiment>
A semiconductor device according to the third embodiment will be described with reference to FIGS. 15 to 20. In the third embodiment, an overhanging sixth insulating layer 40 and a conformal seventh insulating layer 36 are sequentially formed as insulating spacers. This is an example of increasing the shortest distance between the corner of the semiconductor substrate 10 and the second conductive layer 20 by leaving the insulating spacer (sixth insulating layer 40) also on the upper surface of the second insulating layer 14. . Hereinafter, the third embodiment will be described in detail.

  Note that in the third embodiment, a description of the same points as in the above-described embodiments will be omitted, and different points will mainly be described.

[Structure of Third Embodiment]
First, the structure of the semiconductor device according to the third embodiment will be described with reference to FIG. FIG. 15 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

  As shown in FIG. 15, the third embodiment is different from the above embodiments in that an overhanging sixth insulating layer 40 and a conformal seventh insulating layer 36 are sequentially formed as TSV insulating spacers. It is a point.

  More specifically, the sixth insulating layer 40 is formed on the semiconductor substrate 10 in the through hole 15, on the second insulating layer 14 in the opening 23, and on the second insulating layer 14 outside the opening 23. The In other words, the sixth insulating layer 40 is formed on the side surface of the semiconductor substrate 10, on the side surface of the second insulating layer 14, and on the upper surface of the second insulating layer 14. The sixth insulating layer 40 is formed in contact with the upper surface of the first insulating layer 11, and has an opening 47 having the same shape as the opening 18 on the opening 18.

  The sixth insulating layer 40 is formed to protrude thickly (overhang) on the upper side. The film thickness of the sixth insulating layer 40 is, for example, about 250 nm on the side surface and the bottom surface of the semiconductor substrate 10 in the through hole 15. The overhanging fifth insulating layer 30 is made of, for example, silicon oxide. However, the present invention is not limited to this, and may be made of, for example, silicon nitride, SiOF, porous SiOC, or an organic insulator such as polyimide or BCB.

  The seventh insulating layer 36 is formed only on the side surface of the sixth insulating layer 40 outside the through hole 15. That is, the upper surface of the seventh insulating layer 36 is less than or equal to the height of the upper surface of the sixth insulating layer 40. The seventh insulating layer 36 has the opening 17 having the same shape as the opening 47 on the opening 47 in the plane.

  Further, the seventh insulating layer 36 is formed on the sixth insulating layer 40 in the through hole 15 to have a substantially constant film thickness (conformal). The film thickness of the seventh insulating layer 36 is, for example, about 500 nm. The conformal seventh insulating layer 36 is made of an organic insulator such as polyimide or BCB. However, the present invention is not limited to this, and may be made of, for example, silicon oxide, silicon nitride, SiOF, porous SiOC, or the like.

  Each of the sixth insulating layer 40 and the seventh insulating layer 36 formed on the side surface of the semiconductor substrate 10 is not limited to the above-described film thickness, and the integrated film thickness W9 is not limited to the semiconductor substrate 10, the second conductive layer 20, and the like. It is only necessary that the thickness be thick enough to prevent leakage current between the two.

  Outside the through hole 15, the film thickness of the sixth insulating layer 40 (or the integrated film thickness with the seventh insulating layer 36) formed in the vicinity of the corner of the semiconductor substrate 10 is the second insulating layer 14 serving as a hard mask and The integrated film thickness W10 of the sixth insulating layer 40 formed on the second insulating layer 14 can be increased by increasing it. That is, by increasing the integrated film thickness W10 of the second insulating layer 14 and the sixth insulating layer 40 formed on the second surface of the semiconductor substrate 10, the corner portions of the semiconductor substrate 10 and the second conductive layer 20 are increased. The shortest distance W11 and the distance W12 between the corner of the semiconductor substrate 10 and the bump electrode 22 (or the second conductive layer 20) located immediately above the corner can be increased.

  More specifically, the integrated film thickness W10 of the second insulating layer 14 and the sixth insulating layer 40 formed on the second surface of the semiconductor substrate 10 is equal to the sixth insulating layer 40 and the sixth insulating layer 40 formed on the semiconductor substrate 10. It is desirable for the seventh insulating layer 36 to have an accumulated film thickness W9 or more. Thereby, it is possible to prevent the second surface of the semiconductor substrate 10 from being exposed and coming into contact with the second conductive layer 20 or the bump electrode 22 to cause a short circuit. In addition, the distance W12 between the corner portion of the semiconductor substrate 10 and the bump electrode 22 (or the second conductive layer 20) located immediately above the corner portion can be increased, and leakage current can be suppressed.

  The shortest distance W11 between the corner of the semiconductor substrate 10 and the second conductive layer 20 is preferably greater than or equal to the integrated film thickness W9 of the sixth insulating layer 40 and the seventh insulating layer 36. Thereby, the leakage current between the corner | angular part of the semiconductor substrate 10 and the 2nd conductive layer 20 which adjoins most can be suppressed. Therefore, for example, the integrated thickness W10 of the second insulating layer 14 and the sixth insulating layer 40 formed on the second surface of the semiconductor substrate 10 is set to the sixth insulating layer 40 and the seventh thickness formed on the semiconductor substrate 10. It is desirable to set it to at least twice the integrated film thickness W9 of the insulating layer 36.

[Manufacturing Method of Third Embodiment]
Next, a semiconductor device manufacturing method according to the third embodiment will be described with reference to FIGS. 16 to 20 are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the third embodiment.

  First, similarly to the second embodiment, the process shown in FIG. 9 is performed. That is, the semiconductor substrate 10 is etched using the second insulating layer 14 as a mask, and a through hole 15 penetrating from the second surface to the first surface of the semiconductor substrate 10 is formed.

  Next, as shown in FIG. 16, a sixth insulating layer 40 is formed so as to cover the entire surface. More specifically, the sixth insulating layer 40 is formed on the first insulating layer 11 in the through hole 15, on the semiconductor substrate 10 in the through hole 15, and on the second insulating layer 14 outside the through hole 15. Is done. In other words, the sixth insulating layer 40 is formed on the exposed upper surface of the first insulating layer 11, on the side surface of the semiconductor substrate 10, on the side surface and on the upper surface of the second insulating layer 14.

  At this time, the sixth insulating layer 40 is a film with poor coverage, and is formed to protrude thickly (overhang) on the upper side. The film thickness of the sixth insulating layer 40 is, for example, about 500 nm to 1 μm on the upper surface of the second insulating layer 14 outside the through hole 15. The film thickness of the sixth insulating layer 40 is about ½ on the upper surface of the second insulating layer 14 outside the through hole 15 on the side surface and the bottom surface of the semiconductor substrate 10 in the through hole 15. For example, it is about 250 nm.

  The overhanging sixth insulating layer 40 is made of, for example, silicon oxide formed by a P-CVD method. However, it is not limited to the P-CVD method, and may be formed by, for example, a sputtering method, a vapor deposition method, a spin coating method, a spray coating method, or an ALD method. Moreover, it is not limited to silicon oxide, and may be composed of silicon nitride, SiOF, porous SiOC, or an organic insulator such as polyimide or BCB formed by the above method. In this example, a case where silicon oxide is used will be described.

  Next, as shown in FIG. 17, a seventh insulating layer 36 is formed so as to cover the entire surface. More specifically, the seventh insulating layer 36 is formed in a continuous manner on the sixth insulating layer 40 inside and outside the through hole 15. In other words, the seventh insulating layer 36 is formed on the side surface and the upper surface of the sixth insulating layer 40.

  At this time, the seventh insulating layer 36 is formed with a substantially constant film thickness (conformal). The film thickness of the seventh insulating layer 36 is, for example, about 500 nm.

  The conformal seventh insulating layer 36 is made of, for example, an organic insulator such as polyimide or BCB formed by a thermal CVD method. However, it is not limited to the thermal CVD method, and may be formed by, for example, a sputtering method, a vapor deposition method, a spin coating method, a spray coating method, or an ALD method. Moreover, it is not limited to an organic insulator, and may be composed of silicon oxide, silicon nitride, SiOF, porous SiOC, or the like formed by the above method. In this example, a case where an organic insulator is used will be described.

Next, as shown in FIG. 18, the seventh insulating layer 36 located on the bottom surface of the through hole 15 is etched and removed by, for example, Ar / O ₂ plasma etching. Thereby, an opening 17 having a smaller diameter than the through hole 15 is formed in the seventh insulating layer 36 located on the bottom surface in the through hole 15. Further, the sixth insulating layer 40 is exposed at the bottom surface of the opening 17.

  At this time, the seventh insulating layer 36 formed on the upper side (outside the through hole 15) is also etched. The seventh insulating layer 36 formed on the upper side has a higher etching rate than the seventh insulating layer 36 formed on the bottom side. For this reason, the upper seventh insulating layer 36 is etched to a thickness greater than or equal to the thickness of the removed seventh insulating layer 36 on the bottom side. As a result, not only the seventh insulating layer 36 formed on the upper surface of the sixth insulating layer 40 but also the seventh insulating layer 36 formed on the side surface on the upper side of the sixth insulating layer 40 is partially etched and removed. Is done.

  Next, the sixth insulating layer 40 exposed at the bottom surface of the through hole 15 is etched and removed by, for example, CF-based plasma etching. Thereby, an opening 47 having the same diameter as the opening 17 is formed in the sixth insulating layer 40 located on the bottom surface in the through hole 15. Further, the first insulating layer 11 is exposed at the bottom surface of the opening 47.

  At this time, the sixth insulating layer 40 formed on the upper side (outside the through hole 15) is also etched. The sixth insulating layer 40 formed on the upper side has a higher etching rate than the sixth insulating layer 40 formed on the bottom side. For this reason, the sixth insulating layer 40 on the upper side is etched more than the thickness of the sixth insulating layer 40 on the etched bottom side. However, since the sixth insulating layer 40 is an overhanging film on the upper side, even if the etching rate is high, it is not completely removed and remains. That is, the sixth insulating layer 40 remains on the upper surface and the side surface of the second insulating layer 14.

  Next, as shown in FIG. 19, the exposed first insulating layer 11 is etched away by CF-based plasma etching. Thereby, the opening 18 having the same diameter as the opening 47 is formed in the first insulating layer 11. Further, the first conductive layer 12 is exposed at the bottom surface of the opening 18.

  At this time, the sixth insulating layer 40 formed on the second insulating layer 14 is also etched. More specifically, the film thickness of the sixth insulating layer 40 to be etched is calculated by the etching selectivity with the first insulating layer 11 and the film thickness of the first insulating layer 11 to be etched.

  Depending on the material constituting the seventh insulating layer 36, the seventh insulating layer 36 is also etched. More specifically, the film thickness of the seventh insulating layer 36 to be etched is calculated by the etching selectivity with the first insulating layer 11 and the film thickness of the first insulating layer 11 to be etched. In this example, since the seventh insulating layer 36 is made of an organic insulator, the seventh insulating layer 36 is hardly etched even if the first insulating layer 11 made of silicon oxide is etched.

  Thus, by forming the conformal seventh insulating layer 36 on the overhanging sixth insulating layer 40, insulating spacers (seventh insulating layer 36 and sixth insulating layer 40 near the corners of the semiconductor substrate 10) are formed. ) Can be increased. In addition, the conformal seventh insulating layer 36 is etched larger on the upper side than on the bottom side. For this reason, the overhang shape of the sixth insulating layer 40 is offset. That is, on the side surface of the semiconductor substrate 10, the stacked film of the sixth insulating layer 40 and the seventh insulating layer 36 can be formed in a conformal shape. For this reason, it can prevent that the embedding characteristic deteriorates in the embedding process of the 2nd conductive layer 20 mentioned below.

  Next, as shown in FIG. 20, a varimetal 19 is formed so as to cover the entire surface by, for example, sputtering, CVD, or vapor deposition. More specifically, the varimetal 19 is formed in a continuous manner on the sixth insulating layer 40 and the seventh insulating layer 36 inside and outside the through hole 15. In other words, the varimetal 19 is formed on the side surfaces and the upper surface of the sixth insulating layer 40 and the seventh insulating layer 36.

  Next, the second conductive layer 20 is formed on the barrier metal 19 by, for example, a plating technique. Thereby, the second conductive layer 20 is embedded in the through hole 15 and in the openings 17, 18, 23, 47. For this reason, the second conductive layer 20 is formed in contact with the first conductive layer 12 through the barrier metal 19 on the bottom surface of the opening 18, and is electrically connected to the circuit formed on the first surface of the semiconductor substrate 10. Connected. The second conductive layer 20 is also formed outside the opening 23.

  At this time, as described above, the shortest distance W11 between the corner portion of the semiconductor substrate 10 outside the through hole 15 and the second conductive layer 20 is the sixth insulating layer 40 and the seventh insulation formed on the side surface of the semiconductor substrate 10. It is desirable that the thickness is equal to or greater than the integrated film thickness W9 of the layer 36. That is, the integrated film thickness W10 of the second insulating layer 14 and the sixth insulating layer 40 formed on the second surface of the semiconductor substrate 10 is the sixth insulating layer 40 and the seventh insulating layer formed on the side surface of the semiconductor substrate 10. It is desirable that the integrated film thickness W9 of the layer 36 be greater than or equal to, and it is more desirable that the integrated film thickness W9 of the sixth insulating layer 40 and the seventh insulating layer 36 formed on the side surface of the semiconductor substrate 10 be at least twice. .

  Next, excess second conductive layer 20 and barrier metal 19 formed on the upper surface of sixth insulating layer 40 are removed by, for example, CMP. Thereby, the upper surfaces of the sixth insulating layer 40, the second conductive layer 20, and the barrier metal 19 are planarized.

  Thereafter, as shown in FIG. 15, for example, a barrier metal 21 made of Ti or TiN and a bump electrode made of Cu so as to be in contact with the second conductive layer 20 by sputtering, CVD, or plating technology. 22 is formed. Thereby, the bump electrode 22 is electrically connected to a circuit formed on the first surface of the semiconductor substrate 10 via the second conductive layer 20.

  In this way, the TSV according to the third embodiment is formed.

[Effect of the third embodiment]
According to the third embodiment, the overhanging sixth insulating layer 40 and the conformal seventh insulating layer 36 are sequentially formed as insulating spacers. As a result, the sixth insulating layer 40 is formed on the side surface of the semiconductor substrate 10, the side surface of the second insulating layer 14, and the upper surface of the second insulating layer 14, and on the side surface of the sixth insulating layer 40. Then, the seventh insulating layer 36 is formed. Then, the integrated thickness W10 of the second insulating layer 14 and the sixth insulating layer 40 formed on the second surface of the semiconductor substrate 10 is set to the sixth insulating layer 40 and the seventh insulating layer formed on the side surface of the semiconductor substrate 10. The accumulated film thickness W9 of the layer 36 is set to be greater than or equal to W9. Thereby, the film thickness of the sixth insulating layer 40 and the seventh insulating layer 36 formed in the vicinity of the corner of the through hole 15 (corner of the semiconductor substrate 10) can be increased. That is, the distance between the corner of the semiconductor substrate 10 and the second conductive layer 20 can be increased, and the same effect as in the first embodiment can be obtained.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... 1st insulating layer, 12 ... 1st conductive layer, 14 ... 2nd insulating layer, 15 ... Through-hole, 16 ... 3rd insulating layer, 17, 18, 23, 47 ... Opening part, 20 ... 2nd conductive layer, 26 ... 4th insulating layer, 30 ... 5th insulating layer, 36 ... 7th insulating layer, 40 ... 6th insulating layer.

Claims (13)

A semiconductor substrate having a through-hole penetrating from the first surface to the second surface facing the first surface;
A first insulating layer formed on the first surface of the semiconductor substrate and having a first opening having a smaller diameter than the through hole on the first surface of the through hole;
A first conductive layer formed on the first insulating layer so as to cover the first opening;
A second insulating layer formed on the second surface of the semiconductor substrate and having a second opening on the second surface of the through hole;
A third insulating layer formed on the side surface of the semiconductor substrate and on the side surface of the second insulating layer, in contact with the first insulating layer and having a third opening on the first opening;
A second conductive layer formed on the side surface of the second insulating layer, on the upper surface and side surface of the third insulating layer, and on the side surface of the first insulating layer, and in contact with the first conductive layer;
Comprising
The thickness of the second insulating layer formed on the second surface of the semiconductor substrate is greater than or equal to the thickness of the third insulating layer formed on the side surface of the semiconductor substrate. apparatus.   The semiconductor device according to claim 1, wherein a film thickness of the third insulating layer formed on the side surface of the semiconductor substrate is substantially constant.   The shortest distance from a corner on the second surface of the semiconductor substrate to the second conductive layer is greater than or equal to a film thickness of the third insulating layer formed on the semiconductor substrate. 3. The semiconductor device according to claim 1 or 2. A semiconductor substrate having a through-hole penetrating from the first surface to the second surface facing the first surface;
A first insulating layer formed on the first surface of the semiconductor substrate and having a first opening having a smaller diameter than the through hole on the first surface of the through hole;
A first conductive layer formed on the first insulating layer so as to cover the first opening;
A second insulating layer formed on the second surface of the semiconductor substrate and having a second opening on the second surface of the through hole;
A fourth insulating layer formed on the side surface of the semiconductor substrate, on the side surface and the upper surface of the second insulating layer, and in contact with the first insulating layer and having a third opening on the first opening; When,
A second conductive layer formed on and connected to the side surface of the fourth insulating layer and on the side surface of the first insulating layer, and in contact with the first conductive layer;
Comprising
The integrated film thickness of the second insulating layer and the fourth insulating layer formed on the second surface of the semiconductor substrate is equal to or greater than the film thickness of the fourth insulating layer formed on the side surface of the semiconductor substrate. There is a semiconductor device.   The semiconductor device according to claim 4, wherein the film thickness of the fourth insulating layer formed on the side surface of the semiconductor substrate is substantially constant.   The shortest distance from the corner on the second surface of the semiconductor substrate to the second conductive layer is equal to or greater than the thickness of the fourth insulating layer formed on the side surface of the semiconductor substrate. The semiconductor device according to claim 4 or 5. A semiconductor substrate having a through-hole penetrating from the first surface to the second surface facing the first surface;
A first insulating layer formed on the first surface of the semiconductor substrate and having a first opening having a smaller diameter than the through hole on the first surface of the through hole;
A first conductive layer formed on the first insulating layer so as to cover the first opening;
A second insulating layer formed on the second surface of the semiconductor substrate and having a second opening on the second surface of the through hole;
A sixth insulating layer formed on the side surface of the semiconductor substrate, on the side surface and the upper surface of the second insulating layer, and in contact with the first insulating layer and having a third opening on the first opening. When,
A seventh insulating layer formed on the side surface of the sixth insulating layer and having a fourth opening on the third opening;
A second conductive layer formed on the side surface and the upper surface of the seventh insulating layer, on the side surface of the sixth insulating layer, and on the side surface of the first insulating layer, and in contact with the first conductive layer;
Comprising
The integrated film thicknesses of the second insulating layer and the sixth insulating layer formed on the second surface of the semiconductor substrate are the same as the sixth insulating layer and the seventh insulating layer formed on the side surface of the semiconductor substrate. A semiconductor device having a thickness equal to or greater than an integrated film thickness of the layer.   The semiconductor device according to claim 7, wherein the sixth insulating layer is formed to protrude toward the inside of the through hole in the vicinity of a corner portion on the second surface of the semiconductor substrate.   9. The semiconductor device according to claim 7, wherein a film thickness of the seventh insulating layer formed on a side surface of the sixth insulating layer in the through hole is substantially constant.   The shortest distance from the corner on the second surface of the semiconductor substrate to the second conductive layer is equal to or greater than the integrated film thickness of the sixth insulating layer and the seventh insulating layer formed on the side surface of the semiconductor substrate. The semiconductor device according to claim 7, wherein the semiconductor device is a semiconductor device. Forming a first insulating layer on the first surface of the semiconductor substrate;
Forming a first conductive layer on the first insulating layer;
Forming a second opening by etching the second insulating layer after forming a second insulating layer on the second surface of the semiconductor substrate opposite to the first surface;
Forming a through-hole penetrating from the second surface to the first surface in the semiconductor substrate using the second insulating layer as a mask;
Forming a third insulating layer so as to be connected to the upper surface of the first insulating layer, the side surface of the semiconductor substrate, the side surface and the upper surface of the second insulating layer;
Etching the third insulating layer formed on the upper surface of the first insulating layer to form a third opening;
Etching the first insulating layer through the third opening to form the first opening;
Forming a second conductive layer on the side surface of the second insulating layer, on the top surface and side surface of the third insulating layer, on the first insulating layer, and in contact with the first conductive layer; When,
Comprising
The thickness of the second insulating layer formed on the second surface of the semiconductor substrate is greater than or equal to the thickness of the third insulating layer formed on the side surface of the semiconductor substrate. Device manufacturing method. Forming a first insulating layer on the first surface of the semiconductor substrate;
Forming a first conductive layer on the first insulating layer;
Forming a second opening by etching the second insulating layer after forming a second insulating layer on the second surface of the semiconductor substrate opposite to the first surface;
Forming a through-hole penetrating from the second surface to the first surface in the semiconductor substrate using the second insulating layer as a mask;
Forming a fourth insulating layer so as to be connected to the upper surface of the first insulating layer, the side surface of the semiconductor substrate, the side surface and the upper surface of the second insulating layer;
The film thickness on the upper surface of the fourth insulating layer is thicker than the film thickness on the upper surface, the side surface, and the bottom surface of the fourth insulating layer, and on the side surface and the bottom surface of the fourth insulating layer. Forming a fifth insulating layer,
Etching the fourth insulating layer and the fifth insulating layer formed on the upper surface of the first insulating layer to form a third opening;
Etching the first insulating layer through the third opening to form the first opening;
Forming a second conductive layer on the side surface of the third insulating layer or on the side surface of the fourth insulating layer and on the side surface of the first insulating layer so as to be in contact with the first conductive layer;
Comprising
The integrated film thickness of the second insulating layer and the third insulating layer formed on the second surface of the semiconductor substrate is equal to or greater than the film thickness of the third insulating layer formed on the side surface of the semiconductor substrate. A method for manufacturing a semiconductor device. Forming a first insulating layer on the first surface of the semiconductor substrate;
Forming a first conductive layer on the first insulating layer;
Forming a second opening by etching the second insulating layer after forming a second insulating layer on the second surface of the semiconductor substrate opposite to the first surface;
Forming a through-hole penetrating from the second surface to the first surface in the semiconductor substrate using the second insulating layer as a mask;
On the upper surface of the first insulating layer, on the side surface of the semiconductor substrate, on the side surface and on the upper surface of the second insulating layer, and on the upper surface of the first insulating layer, on the side surface of the semiconductor substrate; and Forming a sixth insulating layer such that the film thickness on the upper surface of the second insulating layer is thicker than the film thickness on the side surface of the second insulating layer;
Forming a seventh insulating layer on the top surface, side surface, and bottom surface of the sixth insulating layer so that the film thickness is substantially constant;
Etching the sixth insulating layer and the seventh insulating layer formed on the upper surface of the first insulating layer to form a third opening;
Etching the first insulating layer through the third opening to form the first opening;
Forming a second conductive layer on the side surface of the sixth insulating layer, on the side surface and upper surface of the seventh insulating layer, and on the side surface of the first insulating layer, and in contact with the first conductive layer; When,
Comprising
The integrated film thicknesses of the second insulating layer and the sixth insulating layer formed on the second surface of the semiconductor substrate are the sixth insulating layer and the seventh insulating layer formed on the side surface of the semiconductor substrate. A method for manufacturing a semiconductor device, wherein the thickness is equal to or greater than the thickness of the semiconductor device.

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