CN105355577B - Plasma damage tests structure and preparation method thereof - Google Patents
Plasma damage tests structure and preparation method thereof Download PDFInfo
- Publication number
- CN105355577B CN105355577B CN201410414962.1A CN201410414962A CN105355577B CN 105355577 B CN105355577 B CN 105355577B CN 201410414962 A CN201410414962 A CN 201410414962A CN 105355577 B CN105355577 B CN 105355577B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- interconnection
- metallic
- top layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
This application discloses a kind of plasma damages to test structure, and it includes: transistor which, which tests structure, is set in substrate；Interconnection layer, including the first top layer metallic layer and the first bottom metal layer are formed between the first bottom metal layer and the grid in transistor and are electrically connected；Interconnection layer, including the second top layer metallic layer and the second bottom metal layer are tested, test interconnection layer is set on substrate；Pad structure, including the dielectric layer with through-hole and the metal pad being set in through-hole, pad structure is set on the second top layer metallic layer, the plasma damage tests structure further include: metal connecting layer, the first end of metal connecting layer is set on the surface of the first top layer metallic layer, is formed and is electrically connected between metal connecting layer and test interconnection layer.The plasma damage generated during making plasma damage test structure is reduced, to reduce the plasma damage in plasma damage test structure.
Description
Technical field
This application involves the technical fields of semiconductor integrated circuit, test in particular to a kind of plasma damage
Structure and preparation method thereof.
Background technique
In the manufacturing process of semiconductor chip, it usually needs using plasma process to form required device, such as
Using plasma enhances chemical vapor deposition (PECVD) process deposits dielectric layer or metal layer etc., in another example using plasma
Body etching technics performs etching substrate or dielectric layer etc..However, plasma electric can be generated during plasma process
Lotus.It, will grid between grid and substrate if the conductor for having accumulated plasma electric charge is directly connected on the grid of device
Grid leakage current is formed in oxide layer.When the charge of accumulation is more than certain amount, this grid leakage current can damage gate oxidation
Layer, so that the reliability of the even entire chip of device and service life be made seriously to reduce.Such case is usually known as plasma damage
(PID), also known as antenna effect (PAE).
In order to detect the plasma damage during semiconductor chip fabrication, usually structure will be tested comprising plasma damage
Wafer be placed in the manufacturing process of semiconductor chip, to detect the plasma damage that semiconductor chip is subject to.Fig. 1 is existing
The schematic diagram of some plasma damage test structures.As shown in Figure 1, existing plasma damage test structure includes: to be set to
Transistor 20 ' in substrate 10 ', the interconnection layer 30 ' being set on transistor 20 ', the test being set on the surface of substrate 10
Interconnection layer 40 ', and the pad structure 50 ' being set on test interconnection layer 40 '.Wherein, interconnection layer 30 ' and test interconnection layer
40 ' are connected by top layer metallic layer；Pad structure 50 ' includes the dielectric layer 51 ' with through-hole and the metal being set in through-hole
Pad 53 '.
In above-mentioned plasma damage test structure, pad structure is to be formed after forming top layer metallic layer, and weld
The production of dish structure needs using plasma enhancing chemical vapor deposition (PECVD) and plasma etch process, such as
Using plasma enhances chemical vapor deposition process and forms dielectric layer, in another example using plasma enhances chemical vapor deposition
Technique forms through-hole in the dielectric layer.It is generated in above-mentioned plasma enhanced chemical vapor deposition and plasma etch process
Plasma electric charge can be transmitted on the grid of device by top layer metallic layer, thus on the gate oxide between grid and substrate
Form grid leakage current, and then damage gate oxide so that the reliability of the even entire chip of plasma damage test structure and
Service life seriously reduces, and accuracy when being tested structure detection plasma damage using above-mentioned plasma damage is reduced.Mesh
Before, there are no effective solution methods regarding to the issue above.
Summary of the invention
The application is intended to provide a kind of plasma damage test structure and preparation method thereof, to reduce production plasma damage
The plasma damage generated during wound test structure, and improve and structure detection plasma damage is tested using plasma damage
Accuracy.
To achieve the goals above, this application provides a kind of plasma damages to test structure, the plasma damage
Testing structure includes: transistor, is set in substrate；Interconnection layer, including the first top layer metallic layer and the first bottom metal layer, the
It is formed and is electrically connected between one bottom metal layer and the grid in transistor；Test interconnection layer, including the second top layer metallic layer and the
Two bottom metal layers, test interconnection layer are set on substrate；Pad structure including the dielectric layer with through-hole and is set to through-hole
In metal pad, pad structure is set on the second top layer metallic layer, which tests structure further include: metal
Articulamentum, the first end of metal connecting layer are set on the surface of the first top layer metallic layer, metal connecting layer and test interconnection layer
Between formed electrical connection.
Further, in above-mentioned plasma damage test structure, the second end of metal connecting layer is set to the second top layer
On the surface of metal layer, and the second end of metal connecting layer is connected with dielectric layer.
Further, in above-mentioned plasma damage test structure, plasma damage tests structure further include: intermediate mutual
Even layer, including third top layer metallic layer and third bottom metal layer, intermediate interconnection layers be set to interconnection layer and test interconnection layer it
Between, and third bottom metal layer is connected with the second bottom metal layer；The second end of metal connecting layer is set to third top layer gold
On the surface for belonging to layer, and the second end of metal connecting layer is connected with dielectric layer.
Further, in above-mentioned plasma damage test structure, the material of metal connecting layer and the material of metal pad
It is identical.
Further, in above-mentioned plasma damage test structure, the material of metal connecting layer and metal pad is aluminium.
Further, above-mentioned plasma damage tests structure further include: antenna structure is electrically connected setting with interconnection layer；
And diode, it is set in substrate, is formed and be electrically connected between diode and the second bottom metal layer.
Present invention also provides a kind of production methods of plasma damage test structure, which includes following step
It is rapid: to form transistor in the substrate；The interconnection including the first top layer metallic layer and the first bottom metal layer is formed on transistor
Layer, and the test interconnection layer including the second top layer metallic layer and the second bottom metal layer, the first underlying metal is formed on the substrate
Layer is electrically connected with being formed between the grid in transistor；The dielectric layer with through-hole is formed on the second top layer metallic layer；Logical
Metal pad is formed in hole, and forms the metal connecting layer that first end is located on the surface of the first top layer metallic layer, metal connection
It is formed and is electrically connected between layer and test interconnection layer.
Further, it in above-mentioned production method, forms metal pad and the step of metal connecting layer includes: to form covering the
The metal on surface and dielectric layer and through-hole between one top layer metallic layer, the first top layer metallic layer and the second top layer metallic layer is pre-
Standby layer；Part metals preparation layers on the surface of etching removal dielectric layer, form metal pad and second end are located at the second top layer
Metal connecting layer on the surface of metal layer.
Further, in above-mentioned production method, in the step of forming interconnection layer and test interconnection layer, in interconnection layer and survey
It tries to form the intermediate interconnection layers including third top layer metallic layer and third bottom metal layer, third bottom metal layer between interconnection layer
It is connected with the second bottom metal layer；In the step of forming metal pad and metal connecting layer, the first top-level metallic of covering is formed
Surface, third top layer metallic layer between layer, third top layer metallic layer, the first top layer metallic layer and third top layer metallic layer and
The metal preparation layers on surface and dielectric layer and through-hole between two top layer metallic layers, then etching removal is located at the table of dielectric layer
Part metals preparation layers on face form the metal that metal pad is located on the surface of third top layer metallic layer with second end and connect
Layer.
Further, in above-mentioned production method, forming the step of having the dielectric layer of through-hole includes: to form the first top of covering
Surface between layer metal layer and the surface and the first top layer metallic layer and the second top layer metallic layer of the second top layer metallic layer
Medium preparation layers；Etch media preparation layers are to form through-hole and dielectric layer.
Further, in above-mentioned production method, before forming the step of testing interconnection layer, two poles are formed in the substrate
Pipe；In forming the step of testing interconnection layer, the second bottom metal layer being electrically connected with diode is formed.
Further, in above-mentioned production method, in the step of forming interconnection layer, the antenna being electrically connected with interconnection layer is formed
Structure.
Using the technical solution of the application, dielectric layer is arranged on test interconnection layer by elder generation and in dielectric layer
Through-hole, then the metal connecting layer for making interconnection layer and testing interconnection layer electrical connection is set, so that dielectric layer is arranged and is located at
The plasma electric charge generated in plasma process used by through-hole in dielectric layer will not be transmitted to by interconnection layer
The plasma damage tested on the grid of structure, and then generated during reducing production plasma damage test structure, makes
The plasma damage obtained in plasma damage test structure is reduced, and is improved to test using the plasma damage and be tied
The accuracy of structure detection plasma damage.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.In the accompanying drawings:
Fig. 1 shows the schematic diagram of the section structure of existing plasma damage test structure；
Fig. 2 shows plasma damages provided by a kind of preferred embodiment of the application to test structural profile structural representation
Figure；
Fig. 3 shows the test of plasma damage provided by the application another kind preferred embodiment structural profile structure and shows
It is intended to；
Fig. 4 shows the process signal of the production method of the test structure of plasma damage provided by the application embodiment
Figure；
Fig. 5 shows the production method of the test structure of plasma damage provided by a kind of preferred embodiment of the application
In, the schematic diagram of the section structure of the matrix after transistor is formed in the substrate；
It includes the first top layer metallic layer and the first bottom metal layer that Fig. 6, which shows and formed on transistor shown in Fig. 5,
Interconnection layer, and the test interconnection layer including the second top layer metallic layer and the second bottom metal layer, the first bottom is formed on the substrate
The schematic diagram of the section structure of the matrix after being electrically connected is formed between metal layer and grid in transistor；
Fig. 7 shows cuing open for the matrix after forming the dielectric layer with through-hole on the second top layer metallic layer shown in Fig. 6
Face structural schematic diagram；
Fig. 7-1 shows to form covering the first top layer metallic layer, the second top layer metallic layer and the first top layer shown in fig. 6
The schematic diagram of the section structure of matrix after the medium preparation layers on the surface between metal layer and the second top layer metallic layer；
Fig. 8, which is shown, forms metal pad in through-hole shown in Fig. 7, and forms first end and be located at the first top layer metallic layer
Surface on, second end be located at the matrix after the metal connecting layer on the surface of the second top layer metallic layer cross-section structure signal
Figure；
Fig. 8-1 shows to be formed between covering the first top layer metallic layer shown in Fig. 7, the first top layer metallic layer and dielectric layer
Surface and dielectric layer and through-hole metal preparation layers after matrix the schematic diagram of the section structure；
Fig. 9 shows the production method of the test structure of plasma damage provided by a kind of preferred embodiment of the application
In, the schematic diagram of the section structure of the matrix after transistor is formed in the substrate；
It includes the first top layer metallic layer and the first bottom metal layer that Figure 10, which shows and formed on transistor shown in Fig. 9,
Interconnection layer, and the centre including third top layer metallic layer and third bottom metal layer is formed between interconnection layer and test interconnection layer
The schematic diagram of the section structure of matrix after interconnection layer；
Figure 11 shows the matrix after forming the dielectric layer with through-hole on the second top layer metallic layer shown in Fig. 10
The schematic diagram of the section structure；
Figure 11-1 shows to form covering the first top layer metallic layer shown in Fig. 10, the second top layer metallic layer and the first top
The schematic diagram of the section structure of matrix after the medium preparation layers on the surface between layer metal layer and the second top layer metallic layer；
Figure 12, which is shown, forms metal pad in the through-hole shown in Figure 11, and forms first end and be located at the first top-level metallic
On the surface of layer, second end is located at the cross-section structure signal of the matrix after the metal connecting layer on the surface of third top layer metallic layer
Figure；And
Figure 12-1 shows to form the first top layer metallic layer, third top layer metallic layer shown in coverage diagram 11, the first top layer
Surface, third top layer metallic layer between metal layer and third top layer metallic layer and the surface between the second top layer metallic layer and
The schematic diagram of the section structure of matrix after the metal preparation layers of dielectric layer and through-hole.
Specific embodiment
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular
Also be intended to include plural form, additionally, it should be understood that, when in the present specification using belong to "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or their combination.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
As described in background technique, plasma damage can be generated during production plasma damage test structure
Wound.Present inventor studies regarding to the issue above, proposes a kind of plasma damage test structure.Such as Fig. 2 and
Shown in Fig. 3, it includes: transistor 20 which, which tests structure, is set in substrate 10；Interconnection layer 30, including first
Top layer metallic layer 31 and the first bottom metal layer 33 form electricity between the grid 21 in first bottom metal layer 33 and transistor 20
Connection；Interconnection layer 40, including the second top layer metallic layer 41 and the second bottom metal layer 43 are tested, test interconnection layer 40 is set to lining
On bottom 10；Pad structure 50, including the dielectric layer 51 with through-hole and the metal pad 53 being set in through-hole, pad structure 50
It is set on the second top layer metallic layer 41, which tests structure further include: metal connecting layer 60, metal connecting layer
60 first end is set on the surface of the first top layer metallic layer 31, forms electricity between metal connecting layer 60 and test interconnection layer 40
Connection.
In above-mentioned plasma damage test structure, by elder generation, setting has the dielectric layer of through-hole on test interconnection layer 40
51, then be arranged make interconnection layer 30 and test interconnection layer 40 be electrically connected metal connecting layer 60 so that setting dielectric layer 51 with
And the plasma electric charge generated in plasma process used by the through-hole in dielectric layer 51 will not pass through interconnection
Layer 40 is transmitted on the grid 21 of test structure, and then generated during reducing production plasma damage test structure etc.
Ion dam age, so that the plasma damage in plasma damage test structure is reduced, and improve using plasma
The accuracy of damage measure structure detection plasma damage.
In above-mentioned plasma damage test structure, formation is electrically connected between metal connecting layer 60 and test interconnection layer 40
There are many kinds of modes.In a preferred embodiment, the second end of metal connecting layer 60 is set to the second top layer metallic layer
It is electrically connected on 41 surface so as to be formed between metal connecting layer 60 and test interconnection layer 40, and the second end of metal connecting layer 60
It is connected with dielectric layer 51, structure is as shown in Figure 2.In another preferred embodiment, above-mentioned plasma damage test
Structure further include: be set to interconnection layer 30 and test the intermediate interconnection layers 70 between interconnection layer 40, which includes
Third top layer metallic layer 71 and third bottom metal layer 73, and third bottom metal layer 73 is connected with the second bottom metal layer 43
It connects, the second end of metal connecting layer 60 is set on the surface of third top layer metallic layer 71 so that metal connecting layer 60 and survey at this time
It tries to form electrical connection between interconnection layer 40, and the second end of metal connecting layer 60 is connected with dielectric layer 51, structure such as Fig. 3 institute
Show.
Above-mentioned interconnection layer 30 further includes N layers of intermediate metal layer (marking in figure two layers), and test interconnection layer 40 also includes in N layers
Between metal layer (being marked in figure two layers), and between each metal layer pass through interlayer dielectric layer formed isolation.Above-mentioned metal connecting layer 60
Material with metal pad 53 can be the common metal material in this field.Preferably, the material and metal of metal connecting layer 60
The material of pad 53 is identical.It is further preferable that the material of metal connecting layer 60 and metal pad 53 is aluminium.
Above-mentioned plasma damage test structure can also include: the antenna structure 80 that setting is electrically connected with interconnection layer 30,
And it is set to the diode 90 in substrate 10, and formed and be electrically connected between the diode 90 and the second bottom metal layer 43.On
Antenna structure 80 is stated for detecting the plasma damage that semiconductor chip is subject in the production process.Above-mentioned plasma damage is surveyed
The plasma generated during examination structure fabrication can be guided away by diode 90.
Present invention also provides a kind of production methods of plasma damage test structure.As shown in figure 4, the production method
The following steps are included: forming transistor in the substrate；Formed on transistor includes the first top layer metallic layer and the first bottom gold
Belong to the interconnection layer of layer, and the test interconnection layer of the second top layer metallic layer and the second bottom metal layer, the first bottom is formed on the substrate
It is formed and is electrically connected between layer metal layer and grid in transistor；The dielectric layer with through-hole is formed on the second top layer metallic layer；
Metal pad is formed in through-holes, and forms the metal connecting layer that first end is located on the surface of the first top layer metallic layer, metal
It is formed and is electrically connected between articulamentum and test interconnection layer.
In above-mentioned production method, dielectric layer and the through-hole in dielectric layer are formed on test interconnection layer by elder generation,
The metal connecting layer for making interconnection layer and testing interconnection layer electrical connection is re-formed, so that forming dielectric layer and being located at dielectric layer
In through-hole used by the plasma electric charge that generates in plasma process test knot will not be transmitted to by interconnection layer
On the grid of structure, and then the plasma damage generated during reducing production plasma damage test structure, and improve
Using the accuracy of plasma damage test structure detection plasma damage.
The illustrative embodiments according to the application are described in more detail below.However, these illustrative embodiments
It can be implemented by many different forms, and should not be construed to be limited solely to embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure herein is thoroughly and complete, and by these exemplary realities
The design for applying mode is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer and region
Thickness, and make that identical device is presented with like reference characters, thus description of them will be omitted.
Fig. 5 to Fig. 8 shows the system of the test structure of plasma damage provided by a kind of preferred embodiment of the application
Make in method, the schematic diagram of the section structure of the matrix obtained after each step.Below in conjunction with Fig. 5 to Fig. 8, furtherly
The production method of the test structure of plasma damage provided by bright the application preferred embodiment.
Firstly, forming transistor 20 in substrate 10, and then form base structure as shown in Figure 5.Above-mentioned transistor packet
The grid 21 being set on 10 surface of substrate is included, the side wall layer (not marking in figure) of 21 two sides of grid is set to, and is set to
Source-drain electrode (not marked in figure) in the substrate 10 of 21 two sides of grid.The technique for forming above-mentioned transistor 20 is the existing skill in this field
Art, details are not described herein.
In the step of forming above-mentioned transistor 20, diode 90 can also be formed in substrate 10, with being subsequently formed
Test interconnection layer 40 formed electrical connection.Above-mentioned diode 90 includes p type island region and N-type region, the technique for forming above-mentioned diode 90
It can be set according to the prior art.Meanwhile in the step of forming above-mentioned transistor 20, it can also be formed on grid 21
Contact hole structure forms contact hole structure with being subsequently formed on diode 90 to connect with the interconnection layer 30 being subsequently formed
Test interconnection layer 40 connect.
Formed after completing the step of forming transistor 20 in substrate 10, on transistor 20 shown in Fig. 5 includes the
The interconnection layer 30 of one top layer metallic layer 31 and the first bottom metal layer 33, and being formed on substrate 10 includes the second top layer metallic layer
41 and second bottom metal layer 43 test interconnection layer 40, formed between grid 21 in the first bottom metal layer 33 and transistor 20
Electrical connection, and then form base structure as shown in FIG. 6.Above-mentioned interconnection layer 30 further includes that N layers of intermediate metal layer (mark two in figure
Layer), test interconnection layer 40 also includes N layers of intermediate metal layer (marking in figure two layers), and passes through inter-level dielectric between each metal layer
Layer forms isolation.The method for forming above-mentioned interconnection layer 30 and test interconnection layer 40 may refer to the prior art, and details are not described herein.
Preferably, in the step of forming above-mentioned interconnection layer 30, the antenna structure 80 being electrically connected with interconnection layer 30 can also be formed.
It completes to form the interconnection layer 30 including the first top layer metallic layer 31 and the first bottom metal layer 33 on transistor 20,
And after the step of forming the test interconnection layer 40 of the second top layer metallic layer 41 and the second bottom metal layer 43 on substrate 10,
The dielectric layer 51 with through-hole is formed on second top layer metallic layer 41 shown in fig. 6, and then forms matrix knot as shown in Figure 7
Structure.In a preferred embodiment, the step of forming above-mentioned through-hole and dielectric layer 51 includes: to form covering the first top layer gold
Belong to the table between layer 31 and the surface and the first top layer metallic layer 31 and the second top layer metallic layer 41 of the second top layer metallic layer 41
The medium preparation layers 51 ' in face, and then form the base structure as shown in Fig. 7-1；Etch media preparation layers 51 ' with formed through-hole and
Dielectric layer 51, and then form base structure as shown in Figure 7.
The material of above-mentioned medium preparation layers 51 ' can be dielectric material common in this field, such as silica or nitrogen
SiClx etc..The technique for forming above-mentioned medium preparation layers 51 ' can be chemical vapor deposition or sputtering etc..Etch above-mentioned medium preparation
The technique of layer 51 ' can be dry etching, preferably plasma etching.Above-mentioned technique is state of the art, herein not
It repeats again.It should be noted that being covered when being formed with the antenna structure 80 being electrically connected with grid 21 on transistor 21 in formation
Between lid the first top layer metallic layer 31, the second top layer metallic layer 41 and the first top layer metallic layer 31 and the second top layer metallic layer 41
Surface medium preparation layers 51 ' in the step of forming medium preparation layers 51 ', it is also possible that medium preparation layers 51 ' cover
Antenna structure 80 (does not mark) in figure.
It completes to be formed in through-holes after formation has the step of dielectric layer 51 of through-hole on the second top layer metallic layer 41
Metal pad 53, and form that first end is located on the surface of the first top layer metallic layer 31, second end is located at the second top layer metallic layer
Metal connecting layer 60 on 41 surface, and then form base structure as shown in Figure 8.In a preferred embodiment,
The step of forming above-mentioned metal pad 53 and metal connecting layer 60 includes: to form covering the first top layer metallic layer 31, the first top layer
The metal preparation layers 60 ' on surface and dielectric layer 51 and through-hole between metal layer 31 and dielectric layer 51, and then form such as Fig. 8-1
Shown in base structure；Part metals preparation layers 60 ' on the surface of etching removal dielectric layer 51, to form 53 He of metal pad
Metal connecting layer 60, and then form base structure as shown in Figure 8.
The material of above-mentioned metal preparation layers 60 ' can be metal material common in this field, such as aluminium or copper etc..It is formed
The technique of above-mentioned metal preparation layers 60 ' can be chemical vapor deposition or sputtering etc..The technique for etching above-mentioned metal preparation layers 60 '
It can be dry etching, more preferably plasma etching.Above-mentioned technique is state of the art, and details are not described herein.
Fig. 9 to Figure 12 shows the system of the test structure of plasma damage provided by a kind of preferred embodiment of the application
Make in method, the schematic diagram of the section structure of the matrix obtained after each step.Below in conjunction with Fig. 9 to Figure 12, further
Illustrate the production method of the test structure of plasma damage provided by the application preferred embodiment.
Firstly, forming transistor 20 in substrate 10, and then form base structure as shown in Figure 9.Above-mentioned transistor 20
Including the grid 21 being set on 10 surface of substrate, it is set to the side wall layer (not marking in figure) of 21 two sides of grid, and setting
Source-drain electrode (not marked in figure) in the substrate 10 of 21 two sides of grid.The technique for forming above-mentioned transistor 20 is that this field is existing
Technology, details are not described herein.
In the step of forming above-mentioned transistor 20, diode 90 can also be formed in substrate 10, with being subsequently formed
Test interconnection layer 40 formed electrical connection.Above-mentioned diode 90 includes p type island region and N-type region, the technique for forming above-mentioned diode 90
It can be set according to the prior art.Meanwhile in the step of forming above-mentioned transistor 20, it can also be formed on grid 21
Contact hole structure forms contact hole structure with being subsequently formed on diode 90 to connect with the interconnection layer 30 being subsequently formed
Test interconnection layer 40 connect.
Formed after completing the step of forming transistor 20 in substrate 10, on transistor 20 shown in Fig. 9 includes the
The interconnection layer 30 of 33 layers of one top layer metallic layer 31 and the first underlying metal, being formed on substrate 10 includes the second top layer metallic layer 41
With 43 layers of test interconnection layer 40 of the second underlying metal, and interconnection layer 30 and test interconnection layer 40 between formed include third top
The intermediate interconnection layers 70 of layer metal layer 71 and third bottom metal layer 73, and then form base structure as shown in Figure 10.It is above-mentioned
Interconnection layer 30 further includes N layers of intermediate metal layer (marking in figure two layers), and test interconnection layer 40 also includes N layers of intermediate metal layer (figure
In mark two layers), intermediate interconnection layers 70 also include N layers of intermediate metal layer (marking in figure two layers), and are passed through between each metal layer
Interlayer dielectric layer forms isolation.The method for forming above-mentioned interconnection layer 30, test interconnection layer 40 and intermediate interconnection layers 70 may refer to
The prior art, details are not described herein.Preferably, it in the step of forming above-mentioned interconnection layer 30, can also be formed and interconnection layer 30
The antenna structure 80 of electrical connection.
It completes to form the interconnection layer 30 including 33 layers of the first top layer metallic layer 31 and the first underlying metal on transistor 20,
The test interconnection layer 40 including 43 layers of the second top layer metallic layer 41 and the second underlying metal is formed on substrate 10, and in interconnection layer
The intermediate interconnection layers 70 including third top layer metallic layer 71 and third bottom metal layer 73 are formed between 30 and test interconnection layer 40
The step of after, the dielectric layer 51 with through-hole is formed on the second top layer metallic layer 41, and then form base as shown in figure 11
Body structure.In a preferred embodiment, the step of forming above-mentioned through-hole and dielectric layer 51 includes: to form the first top of covering
Layer metal layer 31, surface between the second top layer metallic layer 41 and the first top layer metallic layer 31 and the second top layer metallic layer 41
Medium preparation layers 51 ', and then form the base structure as shown in Figure 11-1；Etch media preparation layers 51 ' are to form through-hole and Jie
Matter layer 51, and then form base structure as shown in figure 11.
The material of above-mentioned medium preparation layers 51 ' can be dielectric material common in this field, such as silica or nitrogen
SiClx etc..The technique for forming above-mentioned medium preparation layers 51 ' can be chemical vapor deposition or sputtering etc..Etch above-mentioned medium preparation
The technique of layer 51 ' can be dry etching, preferably plasma etching.Above-mentioned technique is state of the art, herein not
It repeats again.It should be noted that being covered when being formed with the antenna structure 80 being electrically connected with grid 21 on transistor 21 in formation
Between lid the first top layer metallic layer 31, the second top layer metallic layer 41 and the first top layer metallic layer 31 and the second top layer metallic layer 41
Surface medium preparation layers 51 ' in the step of forming medium preparation layers 51 ', it is also possible that medium preparation layers 51 ' cover
Antenna structure 80 (does not mark) in figure.
It completes to be formed in through-holes after formation has the step of dielectric layer 51 of through-hole on the second top layer metallic layer 41
Metal pad 53, and form first end and be located on the surface of the first top layer metallic layer 31, second end is located at third top layer metallic layer
Metal connecting layer 60 on 71 surface, and then form base structure as shown in figure 12.In a preferred embodiment,
The step of forming above-mentioned metal pad 53 and metal connecting layer 60 includes: to form covering the first top layer metallic layer 31, third top layer
Surface, third top layer metallic layer 71 and second between metal layer 71, the first top layer metallic layer 31 and third top layer metallic layer 71
The metal preparation layers 60 ' on surface and dielectric layer 51 and through-hole between top layer metallic layer 41, and then formed as shown in Figure 12-1
Base structure；Etching removal is located at the part metals preparation layers 60 ' on the surface of dielectric layer 51, forms metal pad 53 and gold
Belong to articulamentum 60, and then forms base structure as shown in figure 12.
The material of above-mentioned metal preparation layers 60 ' can be metal material common in this field, such as aluminium or copper etc..It is formed
The technique of above-mentioned metal preparation layers 60 ' can be chemical vapor deposition or sputtering etc..The technique for etching above-mentioned metal preparation layers 60 '
It can be dry etching, more preferably plasma etching.Above-mentioned technique is state of the art, and details are not described herein.
It can be seen from the above description that the application the above embodiments realize following technical effect: being existed by elder generation
It tests and dielectric layer and the through-hole in dielectric layer is set on interconnection layer, then being arranged is electrically connected interconnection layer and test interconnection layer
Metal connecting layer so that plasma process used by setting dielectric layer and through-hole in dielectric layer
The plasma electric charge of middle generation will not be transmitted on the grid of test structure by interconnection layer, and then reduces production plasma damage
The plasma damage generated during wound test structure, so that the plasma damage in plasma damage test structure obtains
To reduce, and improve the accuracy using plasma damage test structure detection plasma damage.
The foregoing is merely preferred embodiment of the present application, are not intended to limit this application, for the skill of this field
For art personnel, various changes and changes are possible in this application.Within the spirit and principles of this application, made any to repair
Change, equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (6)
1. a kind of production method of plasma damage test structure, which is characterized in that the production method the following steps are included:
Transistor is formed in the substrate；
The interconnection layer including the first top layer metallic layer and the first bottom metal layer is formed on the transistor, and in the substrate
It is upper formed include the second top layer metallic layer and the second bottom metal layer test interconnection layer, first bottom metal layer with it is described
Electrical connection is formed between grid in transistor；
The dielectric layer with through-hole is formed on second top layer metallic layer；
Metal pad is formed in the through hole, and forms the metal that first end is located on the surface of first top layer metallic layer
Articulamentum is formed between the metal connecting layer and the test interconnection layer and is electrically connected.
2. manufacturing method according to claim 1, which is characterized in that form the metal pad and the metal connecting layer
The step of include:
Form the table covered between first top layer metallic layer, first top layer metallic layer and second top layer metallic layer
The metal preparation layers of face and the dielectric layer and the through-hole；
Etching removes the part metal preparation layers on the surface of the dielectric layer, forms the metal pad and second end position
The metal connecting layer on the surface of second top layer metallic layer.
3. manufacturing method according to claim 1, which is characterized in that
In the step of forming the interconnection layer and the test interconnection layer, between the interconnection layer and the test interconnection layer
Formed include third top layer metallic layer and third bottom metal layer intermediate interconnection layers, the third bottom metal layer and described the
Two bottom metal layers are connected；
In the step of forming the metal pad and the metal connecting layer, is formed and cover first top layer metallic layer, described
Surface, the third top layer between third top layer metallic layer, first top layer metallic layer and the third top layer metallic layer
The metal preparation layers on surface and the dielectric layer and the through-hole between metal layer and second top layer metallic layer, then
Etching removal is located at the part metal preparation layers on the surface of the dielectric layer, forms the metal pad and second end position
The metal connecting layer on the surface of the third top layer metallic layer.
4. production method according to any one of claim 1 to 3, which is characterized in that form the institute with the through-hole
The step of stating dielectric layer include:
Form surface and first top-level metallic of covering first top layer metallic layer and second top layer metallic layer
The medium preparation layers on the surface between layer and second top layer metallic layer；
The medium preparation layers are etched to form the through-hole and dielectric layer.
5. production method according to any one of claim 1 to 3, which is characterized in that
Before the step of forming the test interconnection layer, diode is formed in the substrate；
In the step of forming the test interconnection layer, second bottom metal layer being electrically connected with the diode is formed.
6. production method according to any one of claim 1 to 3, which is characterized in that in the step for forming the interconnection layer
In rapid, the antenna structure being electrically connected with the interconnection layer is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410414962.1A CN105355577B (en) | 2014-08-21 | 2014-08-21 | Plasma damage tests structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410414962.1A CN105355577B (en) | 2014-08-21 | 2014-08-21 | Plasma damage tests structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105355577A CN105355577A (en) | 2016-02-24 |
| CN105355577B true CN105355577B (en) | 2019-01-08 |
Family
ID=55331518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410414962.1A Active CN105355577B (en) | 2014-08-21 | 2014-08-21 | Plasma damage tests structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105355577B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109560099A (en) * | 2018-11-29 | 2019-04-02 | 德淮半导体有限公司 | For the semiconductor devices and its detection method of plasma damage detection, forming method |
| CN113497002B (en) * | 2020-04-07 | 2024-02-06 | 长鑫存储技术有限公司 | PID test structure and semiconductor test structure |
| CN113437047B (en) * | 2021-06-21 | 2022-07-12 | 长江存储科技有限责任公司 | Test structure of semiconductor device, manufacturing method thereof and memory |
| CN113451276A (en) * | 2021-06-28 | 2021-09-28 | 长江存储科技有限责任公司 | Test structure, test system and test method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330040A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Interconnection layer top layer wiring layer of semiconductor device and method for forming the same |
| CN102142429B (en) * | 2010-01-28 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage (PID) detection structure and manufacture method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034816B (en) * | 2009-09-29 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage test device and method for producing test device |
| CN102110638B (en) * | 2009-12-23 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Method and structure for overcoming discharge shortcoming of semiconductor device during manufacturing process |
| CN102446886B (en) * | 2010-09-30 | 2014-10-15 | 中国科学院微电子研究所 | 3D (three-dimensional) integrated circuit structure and forming method thereof |
| CN102790032B (en) * | 2011-05-16 | 2015-01-21 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
-
2014
- 2014-08-21 CN CN201410414962.1A patent/CN105355577B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330040A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Interconnection layer top layer wiring layer of semiconductor device and method for forming the same |
| CN102142429B (en) * | 2010-01-28 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Plasma induced damage (PID) detection structure and manufacture method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105355577A (en) | 2016-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105355577B (en) | Plasma damage tests structure and preparation method thereof | |
| US8232115B2 (en) | Test structure for determination of TSV depth | |
| US7498680B2 (en) | Test structure | |
| US10186463B2 (en) | Method of filling probe indentations in contact pads | |
| US9470715B2 (en) | Probe head | |
| TW201511189A (en) | Semiconductor device and method of inspecting the same | |
| US20080203388A1 (en) | Apparatus and method for detection of edge damages | |
| US20150270234A1 (en) | Pad structure for semiconductor device connection | |
| CN104779238A (en) | Detection structure and detection method for detecting the quality of wafer bonding | |
| TW200617410A (en) | Semiconductor wafer and inspection method thereof | |
| JP2014122882A (en) | Pre space transformer, space transformer manufactured using the pre space transformer, and semiconductor device inspecting apparatus including the space transformer | |
| JP2021502549A (en) | Contact probe for test heads for testing high frequency devices | |
| CN103187403A (en) | Semiconductor failure analysis structure, forming method of semiconductor failure analysis structure and failure time detection method thereof | |
| CN206422042U (en) | Discharge the PID test structures of weld pad plasma | |
| JP2014122872A (en) | Pre space transformer, space transformer manufactured using the pre space transformer, and semiconductor device inspecting apparatus including the space transformer | |
| US20160313375A1 (en) | Chip scale current sensor package and method of producing a current sensor package | |
| US9851398B2 (en) | Via leakage and breakdown testing | |
| KR102026733B1 (en) | Measurment sensor for plasma process and method thereof | |
| CN105244310A (en) | Formation method of interconnection structure | |
| CN106443410B (en) | A kind of IC testing method | |
| KR100520509B1 (en) | A equipment for monitoring electrical test of dielectric layer using guardring pattern | |
| CN106340466B (en) | A kind of IC test structure and forming method thereof | |
| Xu et al. | Low-frequency testing of through silicon vias for defect diagnosis in three-dimensional integration circuit stacking technology | |
| CN103904058A (en) | Gate-oxide medium testing structure | |
| US9646928B2 (en) | Semiconductor arrangement and formation thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |