CN103543365B - The test structure of interconnection structure minimum spacing and method of testing - Google Patents
The test structure of interconnection structure minimum spacing and method of testing Download PDFInfo
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Abstract
The test structure of interconnection structure minimum spacing and a method of testing, described test structure comprises: the first test lead, the second test lead and the MOS transistor be positioned between the two; Test cell comprises the first interconnection line, multiple second interconnection line parallel with the first interconnection line, three interconnection line identical with the second interconnections, be positioned at the conductive plunger on the second interconnection line surface, spacing between the second different interconnection lines and the first interconnection line is different, and the conductive plunger surface that the second interconnection line that each test cell is identical with the first interconnection line spacing is corresponding is connected with same 3rd interconnection line; The grid of MOS transistor is connected with the first interconnection line electricity of described test cell, and described 3rd test lead is connected with the 3rd interconnection line.Only need test when utilizing the test structure of the embodiment of the present invention to test each spacing once, greatly can reduce the test duration, test simple and convenient.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of test structure of interconnection structure minimum spacing and method of testing.
Background technology
Along with the development of semiconductor technology, the structure of semiconductor devices becomes more and more less, also becomes more and more less for the size and spacing connecting the interconnection structure of each semiconductor devices.In the prior art, interconnection structure often comprises metal interconnecting wires, polysilicon interconnection line and the conductive plunger for being connected adjacent layer metal interconnecting wires.
Please refer to Fig. 1, for the structural representation of interconnection structure of the prior art, comprise: the first metal interconnecting wires 01 and the second metal interconnecting wires 02 be arranged in parallel, be positioned at the conductive plunger 03 on described second metal interconnecting wires 02 surface, utilize described conductive plunger 03 to be connected with the metal interconnecting wires electricity of last layer by described second metal interconnecting wires 02.In order to can chip area be effectively utilized, the size of described first metal interconnecting wires and the second metal interconnecting wires, spacing need little as much as possible, the width of described first metal interconnecting wires 01 and the second metal interconnecting wires 02 close to or equal the characteristic dimension of semiconductor technology.But due to the restriction of manufacture craft, the diameter of described conductive plunger 03 is often greater than the characteristic dimension of semiconductor technology, the diameter of described conductive plunger 03 is made often to be greater than the width of the second metal interconnecting wires 02, the spacing of described conductive plunger 03 and the first metal interconnecting wires 01 is less than the spacing of described first metal interconnecting wires 01 and the second metal interconnecting wires 02, even if do not have leakage current between described first metal interconnecting wires 01 of corresponding spacing and the second metal interconnecting wires 02 or be not short-circuited, also may there is leakage current between described conductive plunger 03 and the first metal interconnecting wires 01 or be short-circuited.And in the semiconductor process of reality, described conductive plunger 03 may not aimed at the second metal interconnecting wires 02 completely, spacing between described conductive plunger 03 and the first metal interconnecting wires 01 also may be made too small, leakage current may be had or be short-circuited.Therefore, for a semiconductor fabrication process, need to test out the minimum spacing between described first metal interconnecting wires 01 and the second metal interconnecting wires 02 that can not cause conductive plunger 03 and the first metal interconnecting wires 01 short circuit, and using described minimum spacing as design rule, avoid described interconnection structure to be short-circuited.
In the prior art, method of testing generally includes: make some first metal interconnecting wires and second metal interconnecting wires with different spacing, and form conductive plunger on described second metal interconnecting wires surface, by detecting the electric current between each the first metal interconnecting wires and conductive plunger, whether the first metal interconnecting wires and the second metal interconnecting wires that detect different spacing are short-circuited, thus obtain interconnection structure minimum spacing.But utilize described method of testing to test one by one, testing efficiency is low, in order to reduce error need to test many groups of the first metal interconnecting wires of each spacing and the second metal interconnecting wires time, test more, the overlong time expended, and each test needs test lead to be connected with the first metal interconnecting wires, the second metal interconnecting wires electricity, testing process bothers.
More measuring methods about the characteristic dimension in semiconductor technology please refer to the american documentation literature that publication number is US2002/0177057A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of test structure and method of testing of interconnection structure minimum spacing, and testing process is simple and convenient.
For solving the problem, embodiments provide a kind of test structure of interconnection structure minimum spacing, comprise: the first test lead, the second test lead and the 3rd test lead, some identical MOS transistor and some identical test cells, described test cell and described MOS transistor one_to_one corresponding; Described test cell comprises the first interconnection line, multiple and described first interconnection line parallel the second interconnection line, three interconnection line identical with described second interconnections, be positioned at the conductive plunger on described second interconnection line surface, spacing between described the second different interconnection line and the first interconnection line is different, and the conductive plunger surface that the second interconnection line that each test cell is identical with the first interconnection line spacing is corresponding is connected with same 3rd interconnection line; The source electrode of described MOS transistor is connected with the first test lead, the drain electrode of described MOS transistor is connected with the second test lead, the grid of described MOS transistor is connected with the first interconnection line electricity of described test cell, and described 3rd test lead is connected with the 3rd interconnection line.
Optionally, described MOS transistor is nmos pass transistor or PMOS transistor.
Optionally, the quantity of described MOS transistor is 5 ~ 1000.
Optionally, described first interconnection line, the second interconnection line are metal interconnecting wires or polysilicon interconnection line.
Optionally, described 3rd test lead comprises multiple sub-test lead, and described sub-test lead is with the 3rd interconnection line one_to_one corresponding and be connected.
Optionally, the spacing between described first interconnection line and each the second interconnection line is pressed arithmetic progression and is arranged.
Optionally, described second interconnection line, conductive plunger measure-alike.
Optionally, described first interconnection line surface also has conductive plunger.
Optionally, described first interconnection line is many interconnection lines, and each first interconnection line is corresponding with second interconnection line, and each first interconnection line is different with the spacing of the second corresponding interconnection line.
The embodiment of the present invention additionally provides a kind of method of testing utilizing the test structure of described interconnection structure minimum spacing, comprising: apply source-drain voltage at the source electrode of described MOS transistor with drain electrode by the first test lead and the second test lead; Described 3rd test lead is utilized test voltage to be applied to wherein on one article of the 3rd interconnection line successively, detect total source-drain current of described MOS transistor, when described total source-drain current equals the N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to the N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line; Using the minimum spacing of the minimum value in the spacing between multiple the second interconnection line of not being short-circuited and the first interconnection line as interconnection structure.
Optionally, described first test lead and the second test lead wherein apply operating voltage, other end ground connection in one end.
Optionally, described test voltage is operating voltage.
Optionally, the quantity of described MOS transistor is 5 ~ 1000.
Optionally, described 3rd test lead comprises multiple sub-test lead, and described sub-test lead is with the 3rd interconnection line one_to_one corresponding and be connected, and test voltage is applied to wherein on one article of the 3rd interconnection line, remaining the 3rd interconnection line floating or ground connection.
Compared with prior art, the present invention has the following advantages:
The conductive plunger corresponding due to each second interconnection line identical with the first interconnection line spacing is connected with same 3rd interconnection line, when the 3rd interconnection line is applied with test voltage, test voltage can be applied on the second corresponding interconnection line simultaneously, when part first interconnection line and the second interconnection line are short-circuited, described test voltage will be applied on the grid of corresponding MOS transistor, make MOS transistor conducting, total source-drain current of the first test lead and the second test lead changes, thus can judge whether be short-circuited, determine whether corresponding spacing is interconnection structure safe spacing, and using the minimum value of described safe spacing as interconnection structure minimum spacing.Only need test when utilizing the test structure of the embodiment of the present invention to test each spacing once, greatly can reduce the test duration, test simple and convenient.
Accompanying drawing explanation
Fig. 1 is the structural representation of the interconnection structure of prior art;
Fig. 2 is the structural representation of the test structure of the interconnection structure minimum spacing of the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of the method for testing of the embodiment of the present invention.
Embodiment
Due to too low to the method for testing efficiency of interconnection structure minimum spacing in prior art, and in order to reduce error, needing to test many groups of the first metal interconnecting wires of each spacing and the second metal interconnecting wires, testing more, the overlong time expended.For this reason, inventor is through research, propose a kind of test structure and method of testing of interconnection structure minimum spacing, when utilizing described test structure to test, only need the total source-drain current testing several MOS transistor parallel connections, just can judge whether be short-circuited between the first interconnection line that a certain spacing is corresponding and the second interconnection line, thus obtain the minimum spacing of interconnection structure, simple and fast.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
The embodiment of the present invention provide firstly a kind of test structure of interconnection structure minimum spacing, please refer to Fig. 2, for the structural representation of the test structure of the interconnection structure minimum spacing of the embodiment of the present invention, specifically comprise: the first test lead 110, second test lead 120 and the 3rd test lead 130, some identical MOS transistor 140 and some identical test cells 150, described test cell 150 and described MOS transistor 140 one_to_one corresponding; Described test cell 150 comprises the first interconnection line 151, many articles of second interconnection line 152, with described second interconnection line 152 quantity identical three interconnection lines 160 parallel with described first interconnection line 151, spacing between described the second different interconnection line 152 and the first interconnection line 151 is different, be positioned at the conductive plunger 153 on described second interconnection line 152 surface, conductive plunger 152 surface that the second interconnection line 152 identical with the first interconnection line 151 spacing in each test cell 150 is corresponding is connected with same 3rd interconnection line 160; The source electrode of described MOS transistor 140 is connected with the first test lead 110, the drain electrode of described MOS transistor 140 is connected with the second test lead 120, the grid of described MOS transistor 140 is connected with the first interconnection line 151 electricity of described test cell 150, described 3rd test lead 130 comprises multiple sub-test lead 131, and described sub-test lead 131 is with the 3rd interconnection line 160 one_to_one corresponding and be connected.
Concrete, described MOS transistor 140 is nmos pass transistor or PMOS transistor, and in the present embodiment, described MOS transistor 140 is nmos pass transistor.Each mos transistor structure described is identical, make when each MOS transistor is when the voltage that grid, source electrode and drain electrode apply is identical, the saturated drain-source current of each MOS transistor is identical with cut-off source-drain current, by recording total source-drain current of several MOS transistor between described first test lead 110, second test lead 120, just can understand in test structure and have the grid of several MOS transistor to be applied with operating voltage, thus can judge to be short-circuited between the first interconnection line that how many test cells are corresponding and the second interconnection line.
Described first test lead 110 is connected with the source electrode of all MOS transistor 140, and described second test lead 120 is connected with the drain electrode of all MOS transistor 140, and all MOS transistor 140 are connected in parallel.When described first test lead 110, second test lead 120 is applied with voltage, the source electrode that simultaneously can be applied to MOS transistor 140, with in drain electrode, makes the upper voltage applied of the source electrode of described MOS transistor 140 and drain electrode identical.In the present embodiment, described first test lead 110 applies operating voltage, such as 1.8V, 2.0V or 2.5V etc., described second test lead 120 ground connection, when the grid applying voltage of described MOS transistor 140 makes the channel region of described MOS transistor 140 that conducting occur, the source-drain current of described MOS transistor 140 is saturated drain-source current.
In other embodiments, operating voltage can also be applied, by described first test lead ground connection at described second test lead.
In the present embodiment, test cell 150 comprises one article of first interconnection line 151, many articles of second interconnection line 152, with described second interconnection line 152 quantity identical three interconnection lines 160 parallel with described first interconnection line 151, be positioned at the conductive plunger 153 on described second interconnection line 152 surface, utilize described conductive plunger 153 will be positioned at described second interconnection line 152 and be connected with the 3rd interconnection line 160.Wherein, all conductive plunger 153, second interconnection lines 152 measure-alike.A test cell 150 corresponds to a MOS transistor, and the grid of MOS transistor is connected with the first interconnection line 151 electricity.In the present embodiment, the quantity of described MOS transistor is 5 ~ 1000, and the quantity of described test cell 150 is also 5 ~ 1000.
Described first interconnection line 151, second interconnection line 152 is metal interconnecting wires or polysilicon interconnection line.When described first interconnection line 151, second interconnection line 152 is metal interconnecting wires, described test structure is used for the minimum spacing between detection two metal interconnecting wires, when making to be minimum spacing between described two metal interconnecting wires, two metal interconnecting wires short circuits can not be caused because of the conductive plunger on metal interconnecting wires.
In other embodiments, when described first interconnection line is metal interconnecting wires, when second interconnection line is polysilicon interconnection line, described test structure is used for detecting the minimum spacing between metal interconnecting wires and polysilicon interconnection line, when making to be minimum spacing between described metal interconnecting wires and polysilicon interconnection line, described metal interconnecting wires and the short circuit of polysilicon interconnection line can not be caused because of the conductive plunger on polysilicon interconnection line.
In other embodiments, described first interconnection line can also be polysilicon interconnection line, second interconnection line is polysilicon interconnection line or metal interconnecting wires, and described test structure is used for detecting between polysilicon interconnection line and polysilicon interconnection line, or and metal interconnecting wires between minimum spacing.
In other embodiments, described first interconnection line surface also can have conductive plunger, described first interconnection line is made all to have conductive plunger with on the second parallel interconnection line, more easily be short-circuited between described first interconnection line and the second interconnection line, described test structure is used for minimum spacing when detection first interconnection line and the second interconnection line all having conductive plunger.
In the present embodiment, described first interconnection line 151 is a metal line, there are in described first interconnection line 151 side some second interconnection lines 152 parallel with the first interconnection line 151, the spacing of described second interconnection line 152 and the first interconnection line 151 is different, spacing is arithmetic progression arrangement, such as from 20nm ~ 100nm, tolerance is 5nm.Be not short-circuited when recording the first interconnection line and the second interconnection line when spacing is more than or equal to X, then using X as the minimum spacing between the first interconnection line and the second interconnection line.
In other embodiments, described first interconnection line is many interconnection lines, each first interconnection line is corresponding with second interconnection line, each first interconnection line is different with the spacing of the second corresponding interconnection line, spacing is arithmetic progression arrangement, described many first interconnection lines are connected by the grid electricity of conductive plunger and the metal interconnecting wires and MOS transistor that are positioned at conductive plunger surface, or by being connected with the grid electricity of MOS transistor with the 4th interconnection line that the first interconnection line contacts.Be not short-circuited when recording the first interconnection line and the second interconnection line when spacing is more than or equal to X, then using X as the minimum spacing between the first interconnection line and the second interconnection line.
In other embodiments, the spacing of described second interconnection line 152 and the first interconnection line 151 is different, but the not arrangement in arithmetic progression.Be not short-circuited when recording the first interconnection line and the second interconnection line when spacing is more than or equal to X, then using X as the minimum spacing between the first interconnection line and the second interconnection line.
In the present embodiment, described conductive plunger 153 is positioned at the surface of described second interconnection line 152, and described conductive plunger 153 surface is connected with sub-test lead 131 electricity of one of them in the 3rd test lead 130 by the 3rd interconnection line 160.Because the structure of each test cell 150 is identical, conductive plunger 153 corresponding to a kind of spacing is all connected with same the 3rd interconnection line 160, and is connected with one of them sub-test lead 131 of the 3rd test lead 130 by described 3rd interconnection line 160.
In the present embodiment, the quantity of described MOS transistor is 5 ~ 1000, and the quantity of described test cell 150 is also 5 ~ 1000.Group test lead 131 is applied with test voltage, described test voltage is applied on each second interconnection line 152 corresponding to a kind of spacing simultaneously, when wherein have be short-circuited between several groups of the first interconnection lines 151 and the second interconnection line 152 time, described test voltage is applied on the grid of corresponding MOS transistor, the channel region of MOS transistor is opened, the electric current of the channel region in MOS transistor is saturated drain-source current, by calculating the total current of the first test lead 110 and the second test lead 120, can judge to be short-circuited between the first interconnection line of total how many group test cell and the second interconnection line.Only have when not having to be short-circuited between one group of first interconnection line 151 and the second interconnection line 152, corresponding spacing is just the safe spacing of interconnection structure, and chooses the minimum spacing of minimum value as interconnection structure from some safe spacings.And due to the test cell quantity of the embodiment of the present invention larger, manufacturing process can be reduced as much as possible, test contacts the error brought, only need test when utilizing the test structure of the embodiment of the present invention to test each spacing once simultaneously, greatly can reduce the test duration, test simple and convenient.
The embodiment of the present invention additionally provides a kind of method of testing utilizing the test structure of described interconnection structure minimum spacing, please refer to Fig. 3, is the schematic flow sheet of the method for testing of the embodiment of the present invention, comprises:
Step S101, applies source-drain voltage at the source electrode of described MOS transistor with drain electrode by the first test lead and the second test lead;
Step S102, described 3rd test lead is utilized test voltage to be applied to wherein on one article of the 3rd interconnection line successively, detect total source-drain current of described MOS transistor, when described total source-drain current equals the N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to the N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line,
Step S103, using the minimum spacing of the minimum value in the spacing between multiple the second interconnection line of not being short-circuited and the first interconnection line as interconnection structure.
Concrete, apply source-drain voltage at the source electrode of described MOS transistor 140 with drain electrode by the first test lead 110 and the second test lead 120.
In the present embodiment, described first test lead 110 applies operating voltage, such as 1.8V, 2.0V or 2.5V etc., described second test lead 120 ground connection, when the grid applying voltage of described MOS transistor makes the channel region of described MOS transistor that conducting occur, the source-drain current of described MOS transistor is saturated drain-source current.In other embodiments, operating voltage can also be applied, by described first test lead ground connection at described second test lead.
Test the first interconnection line corresponding to each spacing and the second interconnection line successively, obtain several first interconnection lines be not short-circuited and distance values corresponding to the second interconnection line.
Wherein, the concrete grammar that first interconnection line corresponding to wherein a kind of spacing and the second interconnection line are tested comprises: apply test voltage at one of them sub-test lead 131 of the 3rd test lead 130, and by other sub-test lead 131 floating or ground connection, detect the total source-drain current between the first test lead 110 and the second test lead 120.Described test voltage is more than or equal to the cut-in voltage of MOS transistor, and in the present embodiment, described test voltage is also operating voltage, such as 1.8V, 2.0V or 2.5V etc.Test voltage is applied with owing to only having a sub-test lead 131, the second interconnection line only having a kind of spacing corresponding is applied with test voltage, between part first interconnection line corresponding to described spacing and the second interconnection line during short circuit, described test voltage is applied on the grid of corresponding MOS transistor, the channel region of MOS transistor is opened, and the electric current of the channel region in MOS transistor is saturated drain-source current.Because the saturated drain-source current of MOS transistor differs greatly with cut-off source-drain current, usual difference 3 to 4 orders of magnitude, when the electric current in wherein at least one MOS transistor is saturated drain-source current, can identify easily whether to have between at least one group of the first interconnection line and the second interconnection line and be short-circuited, simple and convenient.And pass through total source-drain current of calculating first test lead 110 and the second test lead 120, described total source-drain current can be drawn divided by saturated drain-source current and be short-circuited between the first interconnection line of total how many test cells and the second interconnection line.Because described test voltage is only applied on the second interconnection line corresponding to a kind of spacing, may be only that the first interconnection line corresponding to a kind of spacing and the second interconnection line are short-circuited, thus can judge to have the first interconnection line of described spacing and whether the second interconnection line meets design rule.Only have when the first interconnection line of corresponding spacing and the second interconnection line are not all short-circuited, total source-drain current of described first test lead 110 and the second test lead 120 equals the N of the cut-off source-drain current of MOS transistor doubly, when N is the quantity of MOS transistor, show that corresponding spacing is the safe spacing of interconnection structure.In the present embodiment, although the quantity of test cell is a lot, but some group first interconnection lines corresponding for a kind of spacing and the second interconnection line only need test once, need compared to existing technology to organize the first interconnection line to each and the second interconnection line is tested, the time spent by test can be reduced greatly, simple and convenient.
After obtaining some groups of the first interconnection lines be not short-circuited and safe spacing corresponding to the second interconnection line, using the minimum spacing of the minimum value in multiple safe spacing as interconnection structure.
To sum up, have several MOS transistor between the first test lead of the embodiment of the present invention and the second test lead, the grid of described MOS transistor is with the first interconnection line one_to_one corresponding of test cell and be connected; Described test cell comprises the first interconnection line, many articles of second interconnection lines parallel with described first interconnection line and three interconnection line identical with described second interconnections, is positioned at the conductive plunger on described second interconnection line surface, spacing between described the second different interconnection line and the first interconnection line is different, and the conductive plunger that described second interconnection line identical with the first interconnection line spacing is corresponding is connected with same 3rd interconnection line; Described 3rd test lead is connected with the 3rd interconnection line.The conductive plunger corresponding due to each second interconnection line identical with the first interconnection line spacing is connected with same 3rd interconnection line, when the 3rd interconnection line is applied with test voltage, test voltage can be applied on the second corresponding interconnection line simultaneously, when part first interconnection line and the second interconnection line are short-circuited, described test voltage will be applied on the grid of corresponding MOS transistor, make MOS transistor conducting, total source-drain current of the first test lead and the second test lead changes, thus can judge whether be short-circuited, determine whether corresponding spacing is interconnection structure safe spacing, and using the minimum value of described safe spacing as interconnection structure minimum spacing.Only need test when utilizing the test structure of the embodiment of the present invention to test each spacing once, greatly can reduce the test duration, test simple and convenient.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (13)
1. a test structure for interconnection structure minimum spacing, is characterized in that, comprising:
First test lead, the second test lead and the 3rd test lead, some identical MOS transistor and some identical test cells, described test cell and described MOS transistor one_to_one corresponding;
Described test cell comprises the first interconnection line, multiple and described first interconnection line parallel the second interconnection line, three interconnection line identical with described second interconnections, be positioned at the conductive plunger on described second interconnection line surface, spacing between described the second different interconnection line and the first interconnection line is different, and the conductive plunger surface corresponding to the second interconnection line identical with the first interconnection line spacing in each test cell connects same 3rd interconnection line;
The source electrode of described MOS transistor is connected with the first test lead, the drain electrode of described MOS transistor is connected with the second test lead, the grid of described MOS transistor is connected with the first interconnection line electricity of described test cell, described 3rd test lead comprises multiple sub-test lead, and described sub-test lead is with the 3rd interconnection line one_to_one corresponding and be connected.
2. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, described MOS transistor is nmos pass transistor or PMOS transistor.
3. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, the quantity of described MOS transistor is 5 ~ 1000.
4. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, described first interconnection line, the second interconnection line are metal interconnecting wires or polysilicon interconnection line.
5. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, the spacing between described first interconnection line and each the second interconnection line is pressed arithmetic progression and is arranged.
6. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described second interconnection line, conductive plunger measure-alike.
7. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, described first interconnection line surface also has conductive plunger.
8. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, described first interconnection line is many interconnection lines, and each first interconnection line is corresponding with second interconnection line, and each first interconnection line is different with the spacing of the second corresponding interconnection line.
9. utilize a method of testing for the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, comprising:
Source-drain voltage is applied at the source electrode of described MOS transistor with drain electrode by the first test lead and the second test lead;
Described 3rd test lead is utilized test voltage to be applied to wherein on one article of the 3rd interconnection line successively, detect total source-drain current of described MOS transistor, when described total source-drain current equals the N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to the N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part second interconnection line that described 3rd interconnection line is corresponding and the first interconnection line;
Using the minimum spacing of the minimum value in the spacing between multiple the second interconnection line of not being short-circuited and the first interconnection line as interconnection structure.
10. method of testing as claimed in claim 9, is characterized in that, described first test lead and the second test lead wherein one end apply operating voltage, other end ground connection.
11. method of testings as claimed in claim 9, it is characterized in that, described test voltage is operating voltage.
12. method of testings as claimed in claim 9, is characterized in that, the quantity of described MOS transistor is 5 ~ 1000.
13. method of testings as claimed in claim 9, it is characterized in that, described 3rd test lead comprises multiple sub-test lead, and described sub-test lead is with the 3rd interconnection line one_to_one corresponding and be connected, test voltage is applied to wherein on one article of the 3rd interconnection line, remaining the 3rd interconnection line floating or ground connection.
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| CN107367678B (en) * | 2016-05-11 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Test structure, test probe card, test system and test method |
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| CN114001692B (en) * | 2020-07-27 | 2023-04-07 | 长鑫存储技术有限公司 | Method for measuring shortest distance between capacitors and method for evaluating capacitor manufacturing process |
| US11933863B2 (en) | 2020-07-27 | 2024-03-19 | Changxin Memory Technologies, Inc. | Method for measuring shortest distance between capacitances and method for evaluating capacitance manufacture procedure |
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| CN1819158A (en) * | 2005-01-28 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101771032A (en) * | 2008-12-31 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through hole structure, semiconductor device, metal interconnection structure and mask plate |
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| US8586470B2 (en) * | 2010-04-27 | 2013-11-19 | Stmicroelectronics S.R.L. | Multilevel interconnect structures and methods of fabricating same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1330398A (en) * | 2000-06-16 | 2002-01-09 | 国际商业机器公司 | Tube core level encapsulation and manufacturing method thereof |
| CN1819158A (en) * | 2005-01-28 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101771032A (en) * | 2008-12-31 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Method for forming through hole structure, semiconductor device, metal interconnection structure and mask plate |
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