CN103543365A - Test structure and test method for minimum distances of interconnection structures - Google Patents
Test structure and test method for minimum distances of interconnection structures Download PDFInfo
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- CN103543365A CN103543365A CN201210238280.0A CN201210238280A CN103543365A CN 103543365 A CN103543365 A CN 103543365A CN 201210238280 A CN201210238280 A CN 201210238280A CN 103543365 A CN103543365 A CN 103543365A
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Abstract
The invention discloses a test structure and a test method for minimum distances of interconnection structures. The test structure comprises a first test end, a second test end and MOS (metal oxide semiconductor) transistors; the MOS transistors are positioned between the first test end and the second test end; each test unit comprises a first interconnection line, a plurality of second interconnection lines, third interconnection lines and conductive plugs, the second interconnection lines of each test unit are parallel to the corresponding first interconnection line, the quantity of the third interconnection lines of each test unit is identical to that of the second interconnection line of the test unit, the conductive plugs are positioned on the surfaces of the second interconnection lines, the distances from the different second interconnection lines of each test unit to the first interconnection line of the test unit are different from one another, and the surfaces of the conductive plugs, which correspond to the second interconnection lines with identical distances to the first interconnection lines, of each test unit are connected with the same third interconnection line of the test unit; grid electrodes of the MOS transistors are electrically connected with the first interconnection lines of the test units, and a third test end is connected with the third interconnection lines. The test structure and the test method in an embodiment of the invention have the advantages that each distance only needs to be tested once, so that the test time can be greatly shortened, and the minimum distances can be easily and conveniently tested.
Description
Technical field
The present invention relates to semiconductor applications, particularly a kind of test structure of interconnection structure minimum spacing and method of testing.
Background technology
Along with the development of semiconductor technology, the structure of semiconductor devices becomes more and more less, for connecting size and the spacing of the interconnection structure of each semiconductor devices, also becomes more and more less.In the prior art, interconnection structure often comprise metal interconnecting wires, polysilicon interconnection line with for being connected the conductive plunger of adjacent layer metal interconnecting wires.
Please refer to Fig. 1, structural representation for interconnection structure of the prior art, comprise: the first metal interconnecting wires 01 be arrangeding in parallel and the second metal interconnecting wires 02, be positioned at the conductive plunger 03 on described the second metal interconnecting wires 02 surface, utilize described conductive plunger 03 that described the second metal interconnecting wires 02 is connected with the metal interconnecting wires electricity of last layer.In order to effectively utilize chip area, the size of described the first metal interconnecting wires and the second metal interconnecting wires, spacing need as much as possible little, and the width of described the first metal interconnecting wires 01 and the second metal interconnecting wires 02 approaches or equal the characteristic dimension of semiconductor technology.But the restriction due to manufacture craft, the diameter of described conductive plunger 03 is often greater than the characteristic dimension of semiconductor technology, make the diameter of described conductive plunger 03 often be greater than the width of the second metal interconnecting wires 02, the spacing of described conductive plunger 03 and the first metal interconnecting wires 01 is less than the spacing of described the first metal interconnecting wires 01 and the second metal interconnecting wires 02, even do not have leakage current or be not short-circuited between described first metal interconnecting wires 01 of corresponding spacing and the second metal interconnecting wires 02, between described conductive plunger 03 and the first metal interconnecting wires 01, also may there is leakage current or be short-circuited.And in actual semiconductor fabrication process, described conductive plunger 03 may not aimed at the second metal interconnecting wires 02 completely, also may make between described conductive plunger 03 and the first metal interconnecting wires 01 spacing too small, may there is leakage current or be short-circuited.Therefore, for a semiconductor fabrication process, need to test out and can not cause described first metal interconnecting wires 01 of conductive plunger 03 and the first metal interconnecting wires 01 short circuit and the minimum spacing between the second metal interconnecting wires 02, and using described minimum spacing as design rule, avoid described interconnection structure to be short-circuited.
In the prior art, method of testing generally includes: make some the first metal interconnecting wires and second metal interconnecting wires with different spacing, and form conductive plunger on described the second metal interconnecting wires surface, by detecting the electric current between each first metal interconnecting wires and conductive plunger, whether the first metal interconnecting wires and the second metal interconnecting wires that detect different spacing are short-circuited, thereby obtain interconnection structure minimum spacing.But utilize described method of testing to test one by one, testing efficiency is low, in the time of need to testing many groups of the first metal interconnecting wires of each spacing and the second metal interconnecting wires in order to reduce error, test more, the overlong time expending, and each test need to be connected test lead with the first metal interconnecting wires, the second metal interconnecting wires electricity, testing process trouble.
More measuring methods about the characteristic dimension in semiconductor technology please refer to the american documentation literature that publication number is US2002/0177057A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of test structure and method of testing of interconnection structure minimum spacing, and testing process is simple and convenient.
For addressing the above problem, the embodiment of the present invention provides a kind of test structure of interconnection structure minimum spacing, comprise: the first test lead, the second test lead and the 3rd test lead, some identical MOS transistor and some identical test cells, described test cell is corresponding one by one with described MOS transistor; Described test cell comprises the second parallel interconnection line of the first interconnection line, a plurality of and described the first interconnection line, three interconnection line identical with described the second interconnections, be positioned at the conductive plunger on described the second interconnection line surface, described the second different interconnection line and the spacing between the first interconnection line are different, and conductive plunger surface corresponding to the second interconnection line that each test cell is identical with the first interconnection line spacing is connected with same the 3rd interconnection line; The source electrode of described MOS transistor is connected with the first test lead, the drain electrode of described MOS transistor is connected with the second test lead, the grid of described MOS transistor is connected with the first interconnection line electricity of described test cell, and described the 3rd test lead is connected with the 3rd interconnection line.
Optionally, described MOS transistor is nmos pass transistor or PMOS transistor.
Optionally, the quantity of described MOS transistor is 5～1000.
Optionally, described the first interconnection line, the second interconnection line are metal interconnecting wires or polysilicon interconnection line.
Optionally, described the 3rd test lead comprises a plurality of sub-test leads, and described sub-test lead and the 3rd interconnection line are corresponding and be connected one by one.
Optionally, the spacing between described the first interconnection line and each the second interconnection line is pressed arithmetic progression and is arranged.
Optionally, described the second interconnection line, conductive plunger is measure-alike.
Optionally, described the first interconnection line surface also has conductive plunger.
Optionally, described the first interconnection line is many interconnection lines, and each first interconnection line is corresponding with second interconnection line, and each first interconnection line is different with the spacing of corresponding the second interconnection line.
The embodiment of the present invention also provides a kind of method of testing of utilizing the test structure of described interconnection structure minimum spacing, comprising: by the first test lead and the second test lead, in source electrode and the drain electrode of described MOS transistor, apply source-drain voltage; Utilize described the 3rd test lead successively test voltage to be applied to wherein on one article of the 3rd interconnection line, detect total source-drain current of described MOS transistor, when described total source-drain current equals N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line; Minimum spacing using a plurality of the second interconnection lines that are not short-circuited and the minimum value in the spacing between the first interconnection line as interconnection structure.
Optionally, described the first test lead and the second test lead wherein apply operating voltage in one end, other end ground connection.
Optionally, described test voltage is operating voltage.
Optionally, the quantity of described MOS transistor is 5～1000.
Optionally, described the 3rd test lead comprises a plurality of sub-test leads, and described sub-test lead and the 3rd interconnection line are corresponding and be connected one by one, test voltage is applied to wherein on one article of the 3rd interconnection line to the floating sky of remaining the 3rd interconnection line or ground connection.
Compared with prior art, the present invention has the following advantages:
The conductive plunger corresponding due to each second interconnection line identical with the first interconnection line spacing is connected with same the 3rd interconnection line, when the 3rd interconnection line is applied with test voltage, test voltage can be applied on the second corresponding interconnection line simultaneously, when part the first interconnection line and the second interconnection line are short-circuited, described test voltage will be applied on the grid of corresponding MOS transistor, make MOS transistor conducting, total source-drain current of the first test lead and the second test lead changes, thereby can judge, whether be short-circuited, determine whether corresponding spacing is interconnection structure safe spacing, and using the minimum value of described safe spacing as interconnection structure minimum spacing.While utilizing the test structure of the embodiment of the present invention to test each spacing, only need to test once, can greatly reduce the test duration, test simple and convenient.
Accompanying drawing explanation
Fig. 1 is the structural representation of the interconnection structure of prior art;
Fig. 2 is the structural representation of test structure of the interconnection structure minimum spacing of the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of the method for testing of the embodiment of the present invention.
Embodiment
Because the method for testing efficiency to interconnection structure minimum spacing in prior art is too low, and in order to reduce error, need to test many groups of the first metal interconnecting wires of each spacing and the second metal interconnecting wires, test more, the overlong time expending.For this reason, inventor is through research, a kind of test structure and method of testing of interconnection structure minimum spacing have been proposed, while utilizing described test structure to test, only need to test total source-drain current of several MOS transistor parallel connections, just can judge between the first interconnection line corresponding to a certain spacing and the second interconnection line and whether be short-circuited, thus the minimum spacing of acquisition interconnection structure, simple and fast.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
First the embodiment of the present invention provides a kind of test structure of interconnection structure minimum spacing, please refer to Fig. 2, structural representation for the test structure of the interconnection structure minimum spacing of the embodiment of the present invention, specifically comprise: the first test lead 110, the second test lead 120 and the 3rd test lead 130, some identical MOS transistor 140 and some identical test cells 150, described test cell 150 is corresponding one by one with described MOS transistor 140; Described test cell 150 comprises the first interconnection line 151, many second interconnection lines 152 parallel with described the first interconnection line 151, three interconnection line 160 identical with described the second interconnection line 152 quantity, described the second different interconnection line 152 and the spacing between the first interconnection line 151 are different, be positioned at the conductive plunger 153 on described the second interconnection line 152 surfaces, conductive plunger 152 surfaces corresponding to the second interconnection line 152 identical with the first interconnection line 151 spacing in each test cell 150 are connected with same the 3rd interconnection line 160; The source electrode of described MOS transistor 140 is connected with the first test lead 110, the drain electrode of described MOS transistor 140 is connected with the second test lead 120, the grid of described MOS transistor 140 is connected with the first interconnection line 151 electricity of described test cell 150, described the 3rd test lead 130 comprises a plurality of sub-test leads 131, and described sub-test lead 131 and the 3rd interconnection line 160 are corresponding and be connected one by one.
Concrete, described MOS transistor 140 is nmos pass transistor or PMOS transistor, in the present embodiment, described MOS transistor 140 is nmos pass transistor.Described each mos transistor structure is identical, while making the voltage that applies in grid, source electrode and drain electrode when each MOS transistor identical, the saturated drain-source current of each MOS transistor is identical with cut-off source-drain current, by recording total source-drain current of several MOS transistor between described the first test lead 110, the second test lead 120, just can understand in test structure and have the grid of several MOS transistor to be applied with operating voltage, thereby can judge between the first interconnection line that how many test cells are corresponding and the second interconnection line, be short-circuited.
Described the first test lead 110 is connected with the source electrode of all MOS transistor 140, and described the second test lead 120 is connected with the drain electrode of all MOS transistor 140, and all MOS transistor 140 are connected in parallel.When described the first test lead 110, the second test lead 120 are applied with voltage, source electrode and the drain electrode that can be applied to MOS transistor 140 upper simultaneously, makes the source electrode of described MOS transistor 140 identical with the voltage applying in drain electrode.In the present embodiment, on described the first test lead 110, apply operating voltage, such as 1.8V, 2.0V or 2.5V etc., described the second test lead 120 ground connection, when the grid of described MOS transistor 140 applies channel region that voltage makes described MOS transistor 140 conducting occurs, the source-drain current of described MOS transistor 140 is saturated drain-source current.
In other embodiments, can also apply operating voltage at described the second test lead, by described the first test lead ground connection.
In the present embodiment, test cell 150 comprises first interconnection line 151, many second interconnection lines 152 parallel with described the first interconnection line 151, three interconnection line 160 identical with described the second interconnection line 152 quantity, be positioned at the conductive plunger 153 on described the second interconnection line 152 surfaces, utilize described conductive plunger 153 will be positioned at described the second interconnection line 152 and be connected with the 3rd interconnection line 160.Wherein, all conductive plungers 153, the second interconnection line 152 is measure-alike.A test cell 150 is corresponding to a MOS transistor, and the grid of MOS transistor is connected with the first interconnection line 151 electricity.In the present embodiment, the quantity of described MOS transistor is 5～1000, and the quantity of described test cell 150 is also 5～1000.
Described the first interconnection line 151, the second interconnection line 152 are metal interconnecting wires or polysilicon interconnection line.When described the first interconnection line 151, the second interconnection line 152 are metal interconnecting wires, described test structure is used for detecting two minimum spacings between metal interconnecting wires, while making between described two metal interconnecting wires as minimum spacing, can not cause because of the conductive plunger on metal interconnecting wires two metal interconnecting wires short circuits.
In other embodiments, when described the first interconnection line is metal interconnecting wires, when the second interconnection line is polysilicon interconnection line, described test structure is used for detecting the minimum spacing between metal interconnecting wires and polysilicon interconnection line, while making between described metal interconnecting wires and polysilicon interconnection line as minimum spacing, can not cause because of the conductive plunger on polysilicon interconnection line described metal interconnecting wires and the short circuit of polysilicon interconnection line.
In other embodiments, described the first interconnection line can also be polysilicon interconnection line, the second interconnection line is polysilicon interconnection line or metal interconnecting wires, and described test structure is used for detecting between polysilicon interconnection line and polysilicon interconnection line, or and metal interconnecting wires between minimum spacing.
In other embodiments, described the first interconnection line surface also can have conductive plunger, make described the first interconnection line all there is conductive plunger with on parallel the second interconnection line, between described the first interconnection line and the second interconnection line, be more easily short-circuited, minimum spacing when described test structure is used for detecting and all has conductive plunger on the first interconnection line and the second interconnection line.
In the present embodiment, described the first interconnection line 151 is a metal line, in described the first interconnection line 151 1 sides, there are some second interconnection lines 152 parallel with the first interconnection line 151, the spacing of described the second interconnection line 152 and the first interconnection line 151 is different, spacing is arithmetic progression and arranges, for example, from 20nm～100nm, tolerance is 5nm.When recording spacing and be more than or equal to X, the first interconnection line and the second interconnection line are not short-circuited, the minimum spacing using X as the first interconnection line and between the second interconnection line.
In other embodiments, described the first interconnection line is many interconnection lines, each first interconnection line is corresponding with second interconnection line, each first interconnection line is different with the spacing of corresponding the second interconnection line, spacing is arithmetic progression and arranges, described many first interconnection lines are by conductive plunger and be positioned at the metal interconnecting wires on conductive plunger surface and the grid electricity of MOS transistor is connected, or are connected with the grid electricity of MOS transistor by the 4th interconnection line contacting with the first interconnection line.When recording spacing and be more than or equal to X, the first interconnection line and the second interconnection line are not short-circuited, the minimum spacing using X as the first interconnection line and between the second interconnection line.
In other embodiments, the spacing of described the second interconnection line 152 and the first interconnection line 151 is different, but be not arithmetic progression, does not arrange.When recording spacing and be more than or equal to X, the first interconnection line and the second interconnection line are not short-circuited, the minimum spacing using X as the first interconnection line and between the second interconnection line.
In the present embodiment, described conductive plunger 153 is positioned at the surface of described the second interconnection line 152, and described conductive plunger 153 surfaces are connected with one of them sub-test lead 131 electricity in the 3rd test lead 130 by the 3rd interconnection line 160.Because the structure of each test cell 150 is identical, conductive plunger 153 corresponding to a kind of spacing is all connected with same the 3rd interconnection line 160, and is connected with one of them sub-test lead 131 of the 3rd test lead 130 by described the 3rd interconnection line 160.
In the present embodiment, the quantity of described MOS transistor is 5～1000, and the quantity of described test cell 150 is also 5～1000.Group test lead 131 is applied with test voltage, described test voltage is applied on each second interconnection line 152 corresponding to a kind of spacing simultaneously, when wherein having while being short-circuited between several groups of the first interconnection lines 151 and the second interconnection line 152, described test voltage is applied on the grid of corresponding MOS transistor, the channel region of MOS transistor is opened, the electric current of the channel region in MOS transistor is saturated drain-source current, by calculating the total current of the first test lead 110 and the second test lead 120, can judge between the first interconnection line of total how many group test cells and the second interconnection line and be short-circuited.Only have when not having to be short-circuited between one group of first interconnection line 151 and the second interconnection line 152, corresponding spacing is just the safe spacing of interconnection structure, and chooses minimum value as the minimum spacing of interconnection structure from some safe spacings.And because the test cell quantity of the embodiment of the present invention is larger, can reduce as much as possible manufacturing process, test the error that contact brings, while utilizing the test structure of the embodiment of the present invention to test each spacing, only need to test once simultaneously, can greatly reduce the test duration, test simple and convenient.
The embodiment of the present invention also provides a kind of method of testing of utilizing the test structure of described interconnection structure minimum spacing, please refer to Fig. 3, and the schematic flow sheet for the method for testing of the embodiment of the present invention, comprising:
Step S101, applies source-drain voltage by the first test lead and the second test lead in source electrode and the drain electrode of described MOS transistor;
Step S102, utilize described the 3rd test lead successively test voltage to be applied to wherein on one article of the 3rd interconnection line, detect total source-drain current of described MOS transistor, when described total source-drain current equals N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line,
Step S103, the minimum spacing using a plurality of the second interconnection lines that are not short-circuited and the minimum value in the spacing between the first interconnection line as interconnection structure.
Concrete, by the first test lead 110 and the second test lead 120, in source electrode and the drain electrode of described MOS transistor 140, apply source-drain voltage.
In the present embodiment, on described the first test lead 110, apply operating voltage, such as 1.8V, 2.0V or 2.5V etc., described the second test lead 120 ground connection, when the grid of described MOS transistor applies channel region that voltage makes described MOS transistor conducting occurs, the source-drain current of described MOS transistor is saturated drain-source current.In other embodiments, can also apply operating voltage at described the second test lead, by described the first test lead ground connection.
Test successively the first interconnection line corresponding to each spacing and the second interconnection line, obtain several first interconnection lines that are not short-circuited and distance values corresponding to the second interconnection line.
Wherein, the concrete grammar that the first interconnection line corresponding to a kind of spacing wherein and the second interconnection line are tested comprises: one of them the sub-test lead 131 at the 3rd test lead 130 applies test voltage, and by other floating sky of sub-test lead 131 or ground connection, detect the total source-drain current between the first test lead 110 and the second test lead 120.Described test voltage is more than or equal to the cut-in voltage of MOS transistor, and in the present embodiment, described test voltage is also operating voltage, such as 1.8V, 2.0V or 2.5V etc.Owing to only having a sub-test lead 131 to be applied with test voltage, only have the second interconnection line corresponding to a kind of spacing to be applied with test voltage, when between part the first interconnection line corresponding to described spacing and the second interconnection line during short circuit, described test voltage is applied on the grid of corresponding MOS transistor, the channel region of MOS transistor is opened, and the electric current of the channel region in MOS transistor is saturated drain-source current.Because the saturated drain-source current of MOS transistor and cut-off source-drain current differ greatly, conventionally differ 3 to 4 orders of magnitude, when the electric current at least one MOS transistor is wherein saturated drain-source current, can identify at an easy rate whether to have between at least one group of the first interconnection line and the second interconnection line and be short-circuited, simple and convenient.And by calculating total source-drain current of the first test lead 110 and the second test lead 120, described total source-drain current can be drawn between the first interconnection line of total how many test cells and the second interconnection line and is short-circuited divided by saturated drain-source current.Because described test voltage is only applied on the second interconnection line corresponding to a kind of spacing, may be only that the first interconnection line corresponding to a kind of spacing and the second interconnection line are short-circuited, thereby can judge the first interconnection line and second interconnection line with described spacing, whether meet design rule.Only have the first interconnection line and the second interconnection line when corresponding spacing not all to be short-circuited, total source-drain current of described the first test lead 110 and the second test lead 120 equal MOS transistor cut-off source-drain current N doubly, when N is the quantity of MOS transistor, show that corresponding spacing is the safe spacing of interconnection structure.In the present embodiment, although the quantity of test cell is a lot, but only need to test once for some groups of the first interconnection lines corresponding to a kind of spacing and the second interconnection line, compared to existing technology, need each to organize the first interconnection line and the second interconnection line is tested, can reduce greatly the spent time of test, simple and convenient.
After having obtained the safe spacing that some groups of the first interconnection lines of not being short-circuited and the second interconnection line are corresponding, the minimum spacing using the minimum value in a plurality of safe spacings as interconnection structure.
To sum up, between the first test lead of the embodiment of the present invention and the second test lead, have several MOS transistor, the grid of described MOS transistor is corresponding and connected one by one with the first interconnection line of test cell; Described test cell comprises the first interconnection line, many second interconnection lines parallel with described the first interconnection line and three interconnection line identical with described the second interconnections, is positioned at the conductive plunger on described the second interconnection line surface, described the second different interconnection line and the spacing between the first interconnection line are different, and the conductive plunger that described second interconnection line identical with the first interconnection line spacing is corresponding is connected with same the 3rd interconnection line; Described the 3rd test lead is connected with the 3rd interconnection line.The conductive plunger corresponding due to each second interconnection line identical with the first interconnection line spacing is connected with same the 3rd interconnection line, when the 3rd interconnection line is applied with test voltage, test voltage can be applied on the second corresponding interconnection line simultaneously, when part the first interconnection line and the second interconnection line are short-circuited, described test voltage will be applied on the grid of corresponding MOS transistor, make MOS transistor conducting, total source-drain current of the first test lead and the second test lead changes, thereby can judge, whether be short-circuited, determine whether corresponding spacing is interconnection structure safe spacing, and using the minimum value of described safe spacing as interconnection structure minimum spacing.While utilizing the test structure of the embodiment of the present invention to test each spacing, only need to test once, can greatly reduce the test duration, test simple and convenient.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (14)
1. a test structure for interconnection structure minimum spacing, is characterized in that, comprising:
The first test lead, the second test lead and the 3rd test lead, some identical MOS transistor and some identical test cells, described test cell is corresponding one by one with described MOS transistor;
Described test cell comprises the second parallel interconnection line of the first interconnection line, a plurality of and described the first interconnection line, three interconnection line identical with described the second interconnections, be positioned at the conductive plunger on described the second interconnection line surface, described the second different interconnection line and the spacing between the first interconnection line are different, and conductive plunger surface corresponding to the second interconnection line that each test cell is identical with the first interconnection line spacing is connected with same the 3rd interconnection line;
The source electrode of described MOS transistor is connected with the first test lead, the drain electrode of described MOS transistor is connected with the second test lead, the grid of described MOS transistor is connected with the first interconnection line electricity of described test cell, and described the 3rd test lead is connected with the 3rd interconnection line.
2. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described MOS transistor is nmos pass transistor or PMOS transistor.
3. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, the quantity of described MOS transistor is 5～1000.
4. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described the first interconnection line, the second interconnection line are metal interconnecting wires or polysilicon interconnection line.
5. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described the 3rd test lead comprises a plurality of sub-test leads, and described sub-test lead and the 3rd interconnection line are corresponding and be connected one by one.
6. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, the spacing between described the first interconnection line and each the second interconnection line is pressed arithmetic progression and arranged.
7. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described the second interconnection line, conductive plunger measure-alike.
8. the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, described the first interconnection line surface also has conductive plunger.
9. the test structure of interconnection structure minimum spacing as claimed in claim 1, it is characterized in that, described the first interconnection line is many interconnection lines, and each first interconnection line is corresponding with second interconnection line, and each first interconnection line is different with the spacing of corresponding the second interconnection line.
10. a method of testing of utilizing the test structure of interconnection structure minimum spacing as claimed in claim 1, is characterized in that, comprising:
By the first test lead and the second test lead, in source electrode and the drain electrode of described MOS transistor, apply source-drain voltage;
Utilize described the 3rd test lead successively test voltage to be applied to wherein on one article of the 3rd interconnection line, detect total source-drain current of described MOS transistor, when described total source-drain current equals N times of cut-off source-drain current of MOS transistor, N is the quantity of MOS transistor, show not to be short-circuited between the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line, when described source-drain current is not equal to N times of cut-off source-drain current of MOS transistor, show to be short-circuited between part the second interconnection line that described the 3rd interconnection line is corresponding and the first interconnection line;
Minimum spacing using a plurality of the second interconnection lines that are not short-circuited and the minimum value in the spacing between the first interconnection line as interconnection structure.
11. method of testings as claimed in claim 10, is characterized in that, described the first test lead and the second test lead wherein apply operating voltage in one end, other end ground connection.
12. method of testings as claimed in claim 10, is characterized in that, described test voltage is operating voltage.
13. method of testings as claimed in claim 10, is characterized in that, the quantity of described MOS transistor is 5～1000.
14. method of testings as claimed in claim 10, it is characterized in that, described the 3rd test lead comprises a plurality of sub-test leads, and described sub-test lead and the 3rd interconnection line are corresponding and be connected one by one, test voltage is applied to wherein on one article of the 3rd interconnection line to the floating sky of remaining the 3rd interconnection line or ground connection.
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| CN107367678A (en) * | 2016-05-11 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure, test probe card, test system and method for testing |
| CN109817538A (en) * | 2019-01-22 | 2019-05-28 | 上海华虹宏力半导体制造有限公司 | SRAM failure on-line testing method |
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