CN102693959B

CN102693959B - Grid resistor test structure for MOS transistor

Info

Publication number: CN102693959B
Application number: CN201110072999.7A
Authority: CN
Inventors: 刘梅; 李平梁
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-03-25
Filing date: 2011-03-25
Publication date: 2014-12-10
Anticipated expiration: 2031-03-25
Also published as: CN102693959A

Abstract

The invention discloses a grid resistor test structure for a metal-oxide-semiconductor (MOS) transistor. The test structure includes m groups of MOS transistors; each group of the MOS transistors comprises n MOS transistors with various channel widths, wherein the MOS transistors in the same group have the identical channel length and different groups of MOS transistors have different channel lengths; and all the MOS transistors have the same type. According to the grid resistor test structure of MOS transistors, all coefficients in a resistance element Rg functional expression in an MOS transistor model can be visually obtained with consideration of the influence of a grid resistor on MOS transistor characteristics.

Description

MOS transistor resistance test structure

Technical field

The present invention relates to semiconductor test technology, particularly a kind of test structure of resistance on device property impact that quantize.

Background technology

Along with MOS (Metal-Oxide-Semiconductor, metal-oxide semiconductor (MOS)) transistor size dwindles, resistance increases gradually on the impact of MOS transistor characteristic, particularly in 45 nanometers and following technique, needs this factor to introduce when MOS transistor model is set up.

While considering resistance on the affecting of MOS transistor characteristic, the model of MOS transistor as shown in Figure 2, mainly on MOS transistor grid, to add a resistive element Rg, this resistive element Rg can be expressed as channel length L, the channel width W of MOS transistor, the function of temperature T: Rg=Func (W, L, T).

But based on prior art, cannot obtain intuitively each coefficient in the functional expression of this resistive element Rg.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of MOS transistor resistance test structure, utilize this MOS transistor resistance test structure, in the time of obtaining more intuitively considering resistance on the affecting of MOS transistor characteristic, each coefficient in the functional expression of the resistive element Rg in the model of MOS transistor.

For solving the problems of the technologies described above, MOS transistor resistance test structure of the present invention, comprises m group MOS transistor;

Each group MOS transistor comprises the MOS transistor of n different channel widths;

Same group of MOS transistor has same channel length;

MOS transistor does not have different channel lengths on the same group;

The type of each MOS transistor is identical;

M, n are positive integer.

The channel length L of e group MOS transistor _e=L _min+ e* △ L, L _minfor minimum channel length, △ L is channel length difference, and e is more than or equal to 0 integer that is less than or equal to m-1.

The channel width W of f MOS transistor in same group of MOS transistor _f=W _min+ f* △ W, W _minfor minimum channel width, △ W is channel width difference, and f is more than or equal to 0 integer that is less than or equal to n-1.

Each channel length of organizing MOS transistor can be less than or equal to 0.5 μ m.

The channel width of each MOS transistor can be more than or equal to 1 μ m.

Can get n >=3.

Same group of MOS transistor can be defined in same polysilicon.

Same group of MOS transistor can form a line along channel width dimension.

The grid of each MOS transistor, source electrode and substrate connect altogether.

N in a same group MOS transistor, the width of its source and drain active area is identical.

N in a same group MOS transistor, the active area that its substrate terminal is drawn is identical apart from the spacing of source and drain active area.

N in a same group MOS transistor, its grid exit polysilicon is identical apart from the spacing of source and drain active area.

The metal of each end of each MOS transistor utilizes multiple layer metal stacking.

The raceway groove of each MOS transistor is identical to the distance on the border, both sides of trap.

The raceway groove of each MOS transistor is more than or equal to 10 μ m to the distance on the border, both sides of trap.

The type of each MOS transistor is all N-type or is all P type.

Described MOS transistor resistance test structure is positioned in the test chip on silicon chip or scribe line area.

MOS transistor resistance test structure of the present invention, can obtain by test the individual P type of different channel widths of n or electrical quantity characteristic (the threshold voltage vt h of N-type MOS transistor of each channel length, saturation current Idsat) the actual measurement relation curve and between resistance, utilize the individual P type of different channel widths of n or electrical quantity characteristic (the threshold voltage vt h of N-type MOS transistor of each channel length of described test acquisition, saturation current Idsat) the actual measurement relation curve and between resistance, by matching, can extract the functional expression Rg=Func (W of the resistive element Rg in the model of this P type or N-type MOS transistor, L, T) each coefficient in.Utilize MOS transistor resistance test structure of the present invention, can obtain intuitively, while considering resistance on the affecting of MOS transistor characteristic, each coefficient in the functional expression of resistive element Rg in the model of MOS transistor, thereby obtain the concrete functional expression of resistive element Rg in the model of MOS transistor, to quantize the impact of resistance on MOS transistor device property.

Accompanying drawing explanation

Below in conjunction with the drawings and the specific embodiments, the present invention is described in further detail.

Fig. 1 is the same group of MOS transistor one embodiment schematic diagram of MOS transistor resistance test structure of the present invention;

Fig. 2 is the model schematic diagram of the MOS transistor while considering resistance on the affecting of MOS transistor characteristic.

Embodiment

MOS transistor resistance test structure of the present invention, comprise m group MOS transistor, each group MOS transistor comprises the MOS transistor of n different channel widths, same group of MOS transistor has same channel length, MOS transistor does not have different channel lengths on the same group, the type identical (be all N-type or be all P type) of each MOS transistor, m, n are positive integer;

The channel length L of e group MOS transistor _efor: L _e=L _min+ e* △ L, L _minfor minimum channel length, △ L is channel length difference, and e is more than or equal to 0 integer that is less than or equal to m-1, and the channel length of respectively organizing MOS transistor is respectively: L ₀= _lmin, L ₁=L _min+ △ L, L ₂=Lmin+2 △ L ..., L _m-1=L _min+ (m-1) △ L; It is degree that each channel length of organizing MOS transistor be take in accordance with design rule, chooses short channel device, a preferred embodiment, and each channel length of organizing MOS transistor is less than or equal to 0.5 μ m;

N MOS transistor in same group of MOS transistor, the channel width W of f MOS transistor _ffor: W _f=W _min+ f* △ W, W _minfor minimum channel width, △ W is channel width difference, and f is more than or equal to 0 integer that is less than or equal to n-1, and the channel width that belongs to n the MOS transistor of same group is respectively: W ₀=W _min, W ₁=W _min+ △ W, W ₂=W _min+ 2 △ W ..., W _n-1=W _min+ (n-1) △ W; The channel width of MOS transistor chooses to eliminate narrow-channel effect degree of being, a preferred embodiment, and the channel width of each MOS transistor is more than or equal to 1 μ m;

One preferred embodiment, same group of MOS transistor as shown in Figure 1, comprises the individual MOS transistor of n (n >=3); This n MOS transistor of same group utilizes same polysilicon to define, and has identical channel length, different channel width; N the MOS transistor that this of same group has the different channel widths of same channel length forms a line along channel width dimension; The grid of each MOS transistor, source electrode and substrate connect altogether; Described n MOS transistor in same group, the width of its source and drain active area 101 is identical, the active area 205 that its substrate terminal is drawn is identical apart from the spacing of source and drain active area 101, and its grid 201 exit polysilicons 102 are identical apart from the spacing of source and drain active area 101; On its source and drain active area 101, there is through hole 103 as much as possible; The metal 104 of each end of each MOS transistor utilizes multiple layer metal stacking, to reduce as far as possible connection resistances, the raceway groove 106 of each MOS transistor (being source and drain active area 101 and the overlapping place of polysilicon) is identical and as far as possible far away to the distance on the border, both sides 100 of trap, for example, be more than or equal to 10 μ m;

Each structure of organizing MOS transistor is except channel length, and other shape structural feature is all consistent; In order to affect in the face with elimination technique, each group MOS transistor utilizes same polysilicon to define.

MOS transistor resistance test structure of the present invention, can be positioned in the test chip on silicon chip or scribe line area.

Claims

1. a MOS transistor resistance test structure, is characterized in that, comprises m group MOS transistor;

Same group of MOS transistor has same channel length;

MOS transistor does not have different channel lengths on the same group;

The type of each MOS transistor is identical;

M, n are positive integer;

The channel length L of e group MOS transistor _e=L _min+ e* △ L, L _minfor minimum channel length, △ L is channel length difference, and e is more than or equal to 0 integer that is less than or equal to m-1;

2. MOS transistor resistance test structure according to claim 1, is characterized in that, each channel length of organizing MOS transistor is less than or equal to 0.5 μ m.

3. MOS transistor resistance test structure according to claim 1, is characterized in that, the channel width of each MOS transistor is more than or equal to 1 μ m.

4. MOS transistor resistance test structure according to claim 1, is characterized in that n >=3.

5. MOS transistor resistance test structure according to claim 1, is characterized in that, same group of MOS transistor is defined in same polysilicon.

6. MOS transistor resistance test structure according to claim 1, is characterized in that, same group of MOS transistor forms a line along channel width dimension.

7. MOS transistor resistance test structure according to claim 1, is characterized in that, the grid of each MOS transistor, source electrode and substrate connect altogether.

8. MOS transistor resistance test structure according to claim 1, is characterized in that, n MOS transistor in same group, and the width of its source and drain active area is identical.

9. MOS transistor resistance test structure according to claim 1, is characterized in that, n MOS transistor in same group, and the active area that its substrate terminal is drawn is identical apart from the spacing of source and drain active area.

10. MOS transistor resistance test structure according to claim 1, is characterized in that, n MOS transistor in same group, and its grid exit polysilicon is identical apart from the spacing of source and drain active area.

11. MOS transistor resistance test structures according to claim 1, is characterized in that, the metal of each end of each MOS transistor utilizes multiple layer metal stacking.

12. MOS transistor resistance test structures according to claim 1, is characterized in that, the raceway groove of each MOS transistor is identical to the distance on the border, both sides of trap.

13. MOS transistor resistance test structures according to claim 14, is characterized in that, the raceway groove of each MOS transistor is more than or equal to 10 μ m to the distance on the border, both sides of trap.

14. MOS transistor resistance test structures according to claim 1, is characterized in that, the type of each MOS transistor is all N-type or is all P type.

15. MOS transistor resistance test structures according to claim 1, is characterized in that, described MOS transistor resistance test structure is positioned in the test chip on silicon chip or scribe line area.