CN205452276U - Structure for testing semiconductor - Google Patents
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- CN205452276U CN205452276U CN201620195460.9U CN201620195460U CN205452276U CN 205452276 U CN205452276 U CN 205452276U CN 201620195460 U CN201620195460 U CN 201620195460U CN 205452276 U CN205452276 U CN 205452276U
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Abstract
The utility model provides a structure for testing semiconductor, structure for testing semiconductor includes the measuring circuit of being established ties in proper order and being formed by a plurality of epitaxys portion and a plurality of light dope portion, and is located two of measuring circuit both ends the part of extending do not is connected with a measuring electrode, wherein, epitaxy portion is including heavy doping epitaxial layer and encirclement the non - doping epitaxial layer or the light dope epitaxial layer of heavy doping epitaxial layer lateral wall and bottom, the thickness of epitaxy portion is greater than the thickness of light dope portion, just light dope portion is close to the first half of epitaxy portion. The utility model discloses a structure for testing semiconductor can be used for testing the transistor source and leak transition zone resistance R_transient to realize that epitaxial technology of comprehensive monitoring and thermal treatment technology change, be favorable to timely troubleshooting, improve production efficiency. And the utility model discloses a structure for testing semiconductor's manufacture craft is plug -to -plug compatibility with present process flow, need not use extra mask version, can not increase manufacturing cost.
Description
Technical field
This utility model belongs to field of semiconductor manufacture, relates to a kind of semi-conductor test structure.
Background technology
Current semiconductor manufacturing industry develops rapidly under the guidance of Moore's Law, constantly improves performance and the integration density of integrated circuit, reduces the power consumption of integrated circuit as far as possible simultaneously.Therefore, preparation high-performance, the ultrashort channel device of low-power consumption will become the manufacturing focus of future semiconductor.For complete depletion type transistor, in order to obtain the ideal sub-threshold gradients of transistor, the thickness of silicon main body must be about 1/3rd of transistor gate length.Reducing however as grid length, the demand as far as possible reducing silicon film thickness becomes actual, because thickness is extremely difficult less than the processing of the silicon fiml of 10 nanometers.On the one hand, the concordance obtaining wafer in the magnitude of a nanometer is abnormal difficult, and on the other hand, thin silicon films is easy to be consumed in follow-up various cleaning procedures so that subsequent source drain electrode growth becomes the most difficult.Therefore, fin field-effect transistor (FinField-EffectTransistor is called for short FinFET) arises at the historic moment.
Fig. 1 is shown as a kind of profile (being parallel to strip fin direction) of FinFET, extension area 103 being lightly doped including both sides before and after body district 101, enclosure body district 101 and the grid structure 102 (before and after grid structure, both sides are not shown) at top, the source region, drain region and a pair that are respectively formed in the left and right sides, described body district 101, described source region and drain region all contact electrode 104 and connect with one.As a example by p-type FinFET, described source region and drain region are formed by first epitaxial layer the 105, second epitaxial layer 106 and Si cap layers 107, wherein said first epitaxial layer 105 is as initial epitaxial layer, by undoped or material is lightly doped constitutes (the germanium silicon that the most germanic amount is 15%～30%, boron doping concentration is 0～1%)；Described second epitaxial layer 106, as source region or the main body in drain region, is made up of (the most boron doped and germanic amount germanium silicon more than 30%) heavily doped material；Described Si cap layers 107 is as the 3rd epitaxial layer, by undoped or Si material (boron doping concentration be 0～2%) is lightly doped constitutes.N-type FinFET is roughly the same with p-type FinFET structure, and simply respective regions doping type is contrary.
As shown in Figure 2, in epitaxy technique, the series resistance of transistor source and drain is made up of three parts: source and drain resistance R_sd, source drain extension district resistance R_extension and source and drain switch region resistance R_transient, the technology controlling and process of this three partial ohmic is the most extremely important to transistor performance.And test structure of the prior art is only used for test source ohmic leakage R_sd and source drain extension district resistance R_extension, it is impossible to realize the change of comprehensive monitoring extension, Technology for Heating Processing so that product yield reduces.
As it is shown on figure 3, be shown as in prior art the test structure for test source ohmic leakage R_sd, it includes that electrode 111 is measured in substrate 108, well region 109, epitaxial material 110 and a pair.Apply voltage on electrode 111 by measuring at a pair, measure and obtain measuring interelectrode electric current, the resistance of epitaxial material unit length can be calculated.Wherein, the epitaxy technique of described epitaxial material 110 is consistent with the epitaxy technique of source transistor drain extensions material.
As shown in Figure 4, being shown as in prior art the test structure for test source drain extension region resistance R_extension, it includes substrate 108, well region 109, lightly-doped layer 112, hard mask layer 113, is positioned at a pair epitaxial material 110 of described lightly-doped layer 112 left and right sides and measures electrode 111 a pair.Apply voltage on electrode 111 by measuring at a pair, measure and obtain measuring interelectrode electric current, the resistance of described lightly-doped layer unit length can be calculated.Wherein, the epitaxy technique of described epitaxial material 110 lightly-doped layer 112 consistent, described with the epitaxy technique of source transistor drain extensions material is consistent with the processing technology that transistor is lightly doped extension area material.
Therefore, how a kind of semi-conductor test structure is provided, for test transistor source and drain switch region resistance R_transient, to realize comprehensive monitoring epitaxy technique and Technology for Heating Processing change, and fix a breakdown in time, improve production efficiency, become the important technological problems that those skilled in the art are urgently to be resolved hurrily.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of semi-conductor test structure, for solving the problem that test structure of the prior art cannot test source and drain switch region resistance R_transient.
For achieving the above object and other relevant purposes, this utility model provides a kind of semi-conductor test structure, described semi-conductor test structure includes the measuring circuit being sequentially connected in series by multiple epitaxy parts and multiple portion of being lightly doped, and two the described epitaxy parts being positioned at described measuring circuit two ends are connected to a measurement electrode；Wherein, described epitaxy part includes heavy doping epitaxial layer and surrounds described heavy doping epitaxial layer sidewall and the undoped epitaxial layer of bottom or lightly doped epitaxial layer；The thickness of described epitaxy part is lightly doped the thickness in portion described in being more than, and described in portion top half near described epitaxy part is lightly doped.
Alternatively, portion upper surface is lightly doped described in and is also formed with hard mask layer.
Alternatively, portion upper surface is lightly doped described in and is also formed with grid structure.
Alternatively, described epitaxy part top is additionally provided with undoped Si cap layers or Si cap layers is lightly doped.
Alternatively, described semi-conductor test structure also includes substrate and is formed at the p-well on described substrate top, and described measuring circuit is formed in described p-well.
Alternatively, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be n-type doping.
Alternatively, described epitaxy part uses silicon materials.
Alternatively, described semi-conductor test structure also includes substrate and is formed at the N trap on described substrate top, and described measuring circuit is formed in described N trap.
Alternatively, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be p-type doping.
Alternatively, described epitaxy part uses germanium silicon material.
As mentioned above, semi-conductor test structure of the present utility model, have the advantages that semi-conductor test structure of the present utility model may be used for test transistor source and drain switch region resistance R_transient, thus realize comprehensive monitoring epitaxy technique and Technology for Heating Processing change, be conducive to fixing a breakdown in time, improve production efficiency.And the processing technology of semi-conductor test structure of the present utility model is completely compatible with existing technological process, it is not necessary to use extra mask plate, will not increase manufacturing cost.
Accompanying drawing explanation
Fig. 1 is shown as a kind of cross-sectional view of FinFET in prior art.
Fig. 2 is shown as the series resistance composition of transistor source and drain.
Fig. 3 is shown as in prior art the test structure for test source ohmic leakage R_sd.
Fig. 4 is shown as in prior art the test structure for test source drain extension region resistance R_extension.
Fig. 5 is shown as the semi-conductor test structure of the present utility model sectional structure chart in embodiment one.
Fig. 6 is shown as the semi-conductor test structure of the present utility model sectional structure chart in embodiment two.
Element numbers explanation
101 body districts
102 grid structures
103 are lightly doped extension area
104 contact electrodes
105 first epitaxial layers
106 second epitaxial layers
107Si cap layers
108 substrates
109 well regions
110 epitaxial material
111 measure electrode
112 lightly-doped layers
113 hard mask layers
201 epitaxy parts
202 are lightly doped portion
203 measure electrode
204 hard mask layers
205 grid structures
206 substrates
207 well regions
Detailed description of the invention
By particular specific embodiment, embodiment of the present utility model being described below, those skilled in the art can be understood other advantages of the present utility model and effect easily by the content disclosed by this specification.
Refer to Fig. 5 to Fig. 6.Notice, structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only in order to coordinate the content disclosed in description, understand for those skilled in the art and read, it is not limited to the enforceable qualifications of this utility model, therefore do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, under not affecting effect that this utility model can be generated by and the purpose that can reach, all should still fall in the range of the technology contents disclosed in this utility model obtains and can contain.Simultaneously, in this specification cited as " on ", D score, "left", "right", the term of " middle " and " " etc., it is merely convenient to understanding of narration, and it is not used to limit the enforceable scope of this utility model, being altered or modified of its relativeness, changing under technology contents without essence, when being also considered as the enforceable category of this utility model.
Embodiment one
As shown in Figure 5, this utility model provides a kind of semi-conductor test structure, described semi-conductor test structure includes by multiple epitaxy parts 201 and multiple measuring circuit that portion 202 be sequentially connected in series is lightly doped, and two the described epitaxy parts being positioned at described measuring circuit two ends are connected to a measurement electrode 203；Wherein, described epitaxy part 201 includes heavy doping epitaxial layer and surrounds described heavy doping epitaxial layer sidewall and the undoped epitaxial layer of bottom or lightly doped epitaxial layer (in Fig. 5, not concrete layering illustrates)；The thickness of described epitaxy part 201 is lightly doped the thickness in portion 202 described in being more than, and described in portion 202 top half near described epitaxy part 201 is lightly doped.As example, described in portion 202 and described epitaxy part 201 upper surface flush are lightly doped.
In the present embodiment, described in portion 202 upper surface be lightly doped be also formed with hard mask layer 204.
In the present embodiment, described in that the doping process in portion 202 is lightly doped is consistent with the doping process that extension area is lightly doped of FinFET.
Concrete, the epitaxy technique of described epitaxy part 201 is consistent with the epitaxy technique of the epitaxial material of FinFET source-drain area, described undoped epitaxial layer or lightly doped epitaxial layer (doping content scope is 0%-1%) are as the initial epitaxial layer of described epitaxy part 201, described heavy doping epitaxial layer is as the main part of described epitaxy part 201, described epitaxy part 201 top may also be further provided with undoped Si cap layers or Si cap layers (not shown) be lightly doped, described undoped Si cap layers or Si cap layers be lightly doped as the 3rd epitaxial layer, its doping content scope is 0%-2%.It is to be noted; although the most deliberately adulterating as in the described undoped epitaxial layer of initial epitaxial layer; but the impurity in follow-up described heavy doping epitaxial layer may be diffused in described undoped epitaxial layer and make it have certain doping, the most should too not limit protection domain of the present utility model.
Semi-conductor test structure of the present utility model is for testing the source and drain switch region resistance R_transient of FinFET, herein, described source and drain switch region resistance refers to transistor source region and extension area transition region the is lightly doped resistance of (being equivalent to described initial epitaxial layer), or drain region and the resistance that extension area transition region (be equivalent to described initial epitaxial layer) is lightly doped.
Concrete, described semi-conductor test structure also includes substrate 206 and is formed at the well region 207 on described substrate 206 top, and described measuring circuit is formed in described well region 207.When described test structure is for testing (being applicable to N-type FinFET) when N-type heavy doping epitaxial layer and N-type are lightly doped the resistance of extension area transition region, described well region 207 is p-well, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be n-type doping (such as phosphorus doping), and described epitaxy part 201 preferably employs silicon materials (if described n-type doping uses phosphorus, then eventually become phosphorus silicon materials).When described test structure is for testing (being applicable to p-type FinFET) when p-type heavy doping epitaxial layer and p-type are lightly doped the resistance of extension area transition region, described well region 207 is N trap, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be p-type doping (such as boron doping), and described epitaxy part 201 preferably employs germanium silicon material (if the doping of described p-type uses boron, then eventually become boron germanium silicon material).
Concrete, in described measuring circuit, described in the quantity in portion 202 is lightly doped is N, and meet N more than 2.In the present embodiment, described in the quantity in portion 202 be lightly doped be preferably 5-100.As example, Fig. 5 shows described in the situation that quantity be 6 in portion 202 is lightly doped.
In the present embodiment, it is preferably and the width that portion 202 is lightly doped in described measuring circuit described in each is set to identical, and in addition to two the described epitaxy parts being positioned at described measuring circuit two ends, in measuring circuit, the width of other each described epitaxy part 201 is also configured as identical.The width a in the portion 202 and width b of described epitaxy part 201 is lightly doped described in Fig. 5 shows.
The source and drain switch region resistance R_transient using semi-conductor test structure of the present utility model test FinFET can comprise the steps:
(1) measure applying predeterminated voltage between electrode 203 at a pair, and test the electric current between a pair measurement electrode 203, i.e. can get total resistance R1 of measuring circuit；
(2) use test structure (structure shown in Fig. 3) test being currently used for test source ohmic leakage R_sd to obtain the resistance R2 of epitaxial material unit length, use test structure (structure as shown in Figure 4) test being currently used for test source drain extension region resistance R_extension to obtain the resistance R3 of lightly-doped layer unit length；
(3) resistance of two epitaxy parts being positioned at test circuit two ends is ignored, and owing to switch region (initial epitaxial layer) width is much smaller than the width of described epitaxy part 201, can be ignored, then resistance sum R4=R1-(N-1) × a × R2-N × b × R3 of all source and drain switch regions in test circuit；In another calculation, the resistance of two epitaxy parts being positioned at test circuit two ends can not also be ignored, but the two is merged into the resistance of the epitaxy part that width is b, then the resistance sum R4=R1-N × a × R2-N × b × R3 of all source and drain switch regions in test circuit.
Due in described test circuit, each corresponding two switch regions, two ends that portion 202 is lightly doped, and described in the quantity in portion 202 is lightly doped is N, in the most described test circuit, the value of resistance sum R4 of all source and drain switch regions is proportionate with 2N.
The processing technology of semi-conductor test structure of the present utility model is completely compatible with the processing technology of existing FinFET.As example, the conventional flowsheet of FinFET comprises the steps:
A () active area defines: include depositing hard mask, active area is graphical, etch hard mask, remove the steps such as photoresistance；
B () fleet plough groove isolation structure makes: include the filling of oxide in groove, chemically-mechanicapolish polish, the step such as annealing；
C () makes N trap/p-well: include that N trap/p-well is graphical, N trap/p-well is injected, N trap/p-well Vt is graphical, N trap/p-well Vt is injected, the step such as annealing, hard mask are removed, growth gate oxide；
(d) gate patterns: include deposit polycrystalline silicon and the step such as graphical；
E () stack makes: include side wall making, halo injection, hard mask deposition, mask lithography (masking is used for defining p-type/N-type source and drain areas), hard mask open and isotropism RIE, anisotropic wet sigma cavity etching, eSiGe (for p-type source and drain) or the growth in situ of epitaxial silicon (for N-type source and drain) or inject the steps such as doping；
F () alternative gate makes；
(g) silicide and contact for producing；
H () BEOL interconnects.
Wherein, in the test structure of the present embodiment, the definition of described hard mask layer 204 (non-epitaxial region) have employed the mask plate used in mask lithography in above-mentioned steps (e) (masking) process, the i.e. making of the test structure of the present embodiment can use existing mask plate, it is not necessary to extra mask plate.Utilize blocking of described hard mask layer 204, can at the cavity that etching obtains for accommodating described epitaxy part 201 about, follow-up in described cavity extension SiGe or Si etc. for making the material of source-drain area, i.e. can get described epitaxy part 201.
Semi-conductor test structure of the present utility model compensate for existing test structure can not the shortcoming of test transistor source and drain switch region resistance R_transient, thus realize comprehensive monitoring epitaxy technique and Technology for Heating Processing change, be conducive to fixing a breakdown in time, improve production efficiency.And the processing technology of semi-conductor test structure of the present utility model is completely compatible with existing technological process, it is not necessary to use extra mask plate, will not increase manufacturing cost.
Embodiment two
As shown in Figure 6, this utility model provides a kind of semi-conductor test structure, described semi-conductor test structure includes by multiple epitaxy parts 201 and multiple measuring circuit that portion 202 be sequentially connected in series is lightly doped, and two the described epitaxy parts being positioned at described measuring circuit two ends are connected to a measurement electrode 203；Wherein, described epitaxy part 201 includes heavy doping epitaxial layer and surrounds described heavy doping epitaxial layer sidewall and the undoped epitaxial layer of bottom or lightly doped epitaxial layer (in Fig. 6, not concrete layering illustrates)；The thickness of described epitaxy part 201 is lightly doped the thickness in portion 202 described in being more than, and described in portion 202 top half near described epitaxy part 201 is lightly doped.As example, described in portion 202 and described epitaxy part 201 upper surface flush are lightly doped.
In the present embodiment, described in portion 202 upper surface be lightly doped be also formed with grid structure 205.
In the present embodiment, described in that the doping process in portion 202 is lightly doped is consistent with the doping process of the Vt injection region of FinFET.Wherein Vt refers to threshold voltage, and Vt injects the injection referring to carry out under gate oxide surface somewhat, and effect is for modulation theresholds voltage, and this is any technique commonly known.Owing to the doping content of the Vt injection region of FinFET is the most close, herein with the doping content that extension area is lightly doped of FinFET, it is believed that described in that the doping content in portion 202 is lightly doped is consistent with the doping content that extension area is lightly doped of FinFET.
Concrete, the epitaxy technique of described epitaxy part 201 is consistent with the epitaxy technique of the epitaxial material of FinFET source-drain area, described undoped epitaxial layer or lightly doped epitaxial layer (doping content scope is 0%-1%) are as the initial epitaxial layer of described epitaxy part 201, described heavy doping epitaxial layer is as the main part of described epitaxy part 201, described epitaxy part 201 top may also be further provided with undoped Si cap layers or Si cap layers (not shown) be lightly doped, described undoped Si cap layers or Si cap layers be lightly doped as the 3rd epitaxial layer, its doping content scope is 0%-2%.It is to be noted; although the most deliberately adulterating as in the described undoped epitaxial layer of initial epitaxial layer; but the impurity in follow-up described heavy doping epitaxial layer may be diffused in described undoped epitaxial layer and make it have certain doping, the most should too not limit protection domain of the present utility model.
Semi-conductor test structure of the present utility model is for testing the source and drain switch region resistance R_transient of FinFET, herein, described source and drain switch region resistance refers to transistor source region and extension area transition region the is lightly doped resistance of (being equivalent to described initial epitaxial layer), or drain region and the resistance that extension area transition region (be equivalent to described initial epitaxial layer) is lightly doped.
Concrete, described semi-conductor test structure also includes substrate 206 and is formed at the well region 207 on described substrate 206 top, and described measuring circuit is formed in described well region 207.When described test structure is for testing (being applicable to N-type FinFET) when N-type heavy doping epitaxial layer and N-type are lightly doped the resistance of extension area transition region, described well region 207 is p-well, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be n-type doping (such as phosphorus doping), and described epitaxy part 201 preferably employs silicon materials (if described n-type doping uses phosphorus, then eventually become phosphorus silicon materials).When described test structure is for testing (being applicable to p-type FinFET) when p-type heavy doping epitaxial layer and p-type are lightly doped the resistance of extension area transition region, described well region 207 is N trap, described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be p-type doping (such as boron doping), and described epitaxy part 201 preferably employs germanium silicon material (if the doping of described p-type uses boron, then eventually become boron germanium silicon material).
Concrete, in described measuring circuit, described in the quantity in portion 202 is lightly doped is N, and meet N more than 2.In the present embodiment, described in the quantity in portion 202 be lightly doped be preferably 5-100.As example, Fig. 6 shows described in the situation that quantity be 6 in portion 202 is lightly doped.
In the present embodiment, it is preferably and the width that portion 202 is lightly doped in described measuring circuit described in each is set to identical, and in addition to two the described epitaxy parts being positioned at described measuring circuit two ends, in measuring circuit, the width of other each described epitaxy part 201 is also configured as identical.The width a in the portion 202 and width b of described epitaxy part 201 is lightly doped described in Fig. 6 shows.
The source and drain switch region resistance R_transient using semi-conductor test structure of the present utility model test FinFET can comprise the steps:
(1) measure applying predeterminated voltage between electrode 203 at a pair, and test the electric current between a pair measurement electrode 203, i.e. can get total resistance R1 of measuring circuit；
(2) use test structure (structure shown in Fig. 3) test being currently used for test source ohmic leakage R_sd to obtain the resistance R2 of epitaxial material unit length, use test structure (structure as shown in Figure 4) test being currently used for test source drain extension region resistance R_extension to obtain the resistance R3 of lightly-doped layer unit length；
(3) resistance of two epitaxy parts being positioned at test circuit two ends is ignored, and owing to switch region (initial epitaxial layer) width is much smaller than the width of described epitaxy part 201, can be ignored, then resistance sum R4=R1-(N-1) × a × R2-N × b × R3 of all source and drain switch regions in test circuit；In another calculation, the resistance of two epitaxy parts being positioned at test circuit two ends can not also be ignored, but the two is merged into the resistance of the epitaxy part that width is b, then the resistance sum R4=R1-N × a × R2-N × b × R3 of all source and drain switch regions in test circuit.
Due in described test circuit, each corresponding two switch regions, two ends that portion 202 is lightly doped, and described in the quantity in portion 202 is lightly doped is N, in the most described test circuit, the value of resistance sum R4 of all source and drain switch regions is proportionate with 2N.
The processing technology of semi-conductor test structure of the present utility model is completely compatible with the processing technology of existing FinFET.As example, the conventional flowsheet of FinFET comprises the steps:
A () active area defines: include depositing hard mask, active area is graphical, etch hard mask, remove the steps such as photoresistance；
B () fleet plough groove isolation structure makes: include the filling of oxide in groove, chemically-mechanicapolish polish, the step such as annealing；
C () makes N trap/p-well: include that N trap/p-well is graphical, N trap/p-well is injected, N trap/p-well Vt is graphical, N trap/p-well Vt is injected, the step such as annealing, hard mask are removed, growth gate oxide；
(d) gate patterns: include deposit polycrystalline silicon and the step such as graphical；
E () stack makes: include side wall making, halo injection, hard mask deposition, mask lithography (masking is used for defining p-type/N-type source and drain areas), hard mask open and isotropism RIE, anisotropic wet sigma cavity etching, eSiGe (for p-type source and drain) or the growth in situ of epitaxial silicon (for N-type source and drain) or inject the steps such as doping；
F () alternative gate makes；
(g) silicide and contact for producing；
H () BEOL interconnects.
Wherein, in the test structure of the present embodiment, the described injection technology that portion 202 be lightly doped is consistent with the Vt injection technology in above-mentioned steps (c), the definition of described grid structure 205 (non-epitaxial region) have employed the mask plate in above-mentioned steps (d) used in gate patterns process, the i.e. making of the test structure of the present embodiment can use existing mask plate, it is not necessary to extra mask plate.Utilize blocking of described grid structure 205, can at the cavity that etching obtains for accommodating described epitaxy part 201 about, follow-up in described cavity extension SiGe or Si etc. for making the material of source-drain area, i.e. can get described epitaxy part 201.
Semi-conductor test structure of the present utility model compensate for existing test structure can not the shortcoming of test transistor source and drain switch region resistance R_transient, thus realize comprehensive monitoring epitaxy technique and Technology for Heating Processing change, be conducive to fixing a breakdown in time, improve production efficiency.And the processing technology of semi-conductor test structure of the present utility model is completely compatible with existing technological process, it is not necessary to use extra mask plate, will not increase manufacturing cost.Relative to embodiment one, in the present embodiment, the described width a that portion 202 be lightly doped can less (the mask plate characteristic size owing to being used be less, the width of described grid structure 205 is less than the width of hard mask layer 204 described in embodiment one), and resistance that portion is lightly doped is much greater relative to the resistance of heavy doping epitaxial layer, the portion that is lightly doped of less width can reduce measurement error, improves the measuring accuracy of transistor source and drain switch region resistance R_transient.
In sum, semi-conductor test structure of the present utility model may be used for test transistor source and drain switch region resistance R_transient, thus realizes comprehensive monitoring epitaxy technique and Technology for Heating Processing change, is conducive to fixing a breakdown in time, improves production efficiency.The processing technology of semi-conductor test structure of the present utility model is completely compatible with existing technological process, it is not necessary to use extra mask plate, will not increase manufacturing cost.So, this utility model effectively overcomes various shortcoming of the prior art and has high industrial utilization.
Above-described embodiment only illustrative principle of the present utility model and effect thereof, not for limiting this utility model.Above-described embodiment all can be modified under spirit and the scope of the present utility model or change by any person skilled in the art.Therefore, art has all equivalence modification or changes that usually intellectual is completed under without departing from the spirit disclosed in this utility model and technological thought such as, must be contained by claim of the present utility model.
Claims (10)
1. a semi-conductor test structure, it is characterized in that, described semi-conductor test structure includes the measuring circuit being sequentially connected in series by multiple epitaxy parts and multiple portion of being lightly doped, and two the described epitaxy parts being positioned at described measuring circuit two ends are connected to a measurement electrode；Wherein, described epitaxy part includes heavy doping epitaxial layer and surrounds described heavy doping epitaxial layer sidewall and the undoped epitaxial layer of bottom or lightly doped epitaxial layer；The thickness of described epitaxy part is lightly doped the thickness in portion described in being more than, and described in portion top half near described epitaxy part is lightly doped.
Semi-conductor test structure the most according to claim 1, it is characterised in that portion upper surface is lightly doped described in: and is also formed with hard mask layer.
Semi-conductor test structure the most according to claim 1, it is characterised in that portion upper surface is lightly doped described in: and is also formed with grid structure.
Semi-conductor test structure the most according to claim 1, it is characterised in that: described epitaxy part top is additionally provided with undoped Si cap layers or Si cap layers is lightly doped.
5. according to the semi-conductor test structure described in claim 1-4 any one, it is characterised in that: described semi-conductor test structure also includes substrate and is formed at the p-well on described substrate top, and described measuring circuit is formed in described p-well.
Semi-conductor test structure the most according to claim 5, it is characterised in that: described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be n-type doping.
Semi-conductor test structure the most according to claim 6, it is characterised in that: described epitaxy part uses silicon materials.
8. according to the semi-conductor test structure described in claim 1-4 any one, it is characterised in that: described semi-conductor test structure also includes substrate and is formed at the N trap on described substrate top, and described measuring circuit is formed in described N trap.
Semi-conductor test structure the most according to claim 8, it is characterised in that: described heavy doping epitaxial layer and described in the doping type in portion be lightly doped be p-type doping.
Semi-conductor test structure the most according to claim 9, it is characterised in that: described epitaxy part uses germanium silicon material.
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