CN103887202B - monitoring method - Google Patents
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- CN103887202B CN103887202B CN201410109846.9A CN201410109846A CN103887202B CN 103887202 B CN103887202 B CN 103887202B CN 201410109846 A CN201410109846 A CN 201410109846A CN 103887202 B CN103887202 B CN 103887202B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
Disclosed herein a kind of monitoring method, for for on-line monitoring SiGe structure and STI interface performance.Described monitoring method, by forming the identical peripheral type PN junction of junction area and area-type PN junction, measures both leakage currents, is obtained the state at the interface of SiGe structure and STI by comparing and analysis.As such, it is possible to directly monitored the state at the interface of SiGe structure and STI by the leakage current of monitoring SiGe structure and the interface of STI.Thus realize the monitoring in real time of product on line, it is not necessary to the problem generation of waiting until carries out TEM section again and studies interface the most normally, substantially increases product yield.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of monitoring SiGe structure and STI interface performance
Monitoring method.
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element is constantly reducing,
Generally including the reduction of MOSFET element channel length, the thinning grade of gate oxide thickness is to obtain faster
Device speed.But it is as very large scale integration technology when being developed to sub-micro level, particularly 90
When nanometer and techniques below node, reduce channel length and can bring series of problems, in order to control short channel effect
Should, the impurity of higher concentration can be doped with in channels, this can reduce the mobility of carrier, thus cause device
Part hydraulic performance decline, simple device size reduction is difficult to meet the development of large scale integrated circuit technology.Therefore,
The widely studied mobility being used for improving carrier of stress engineering, thus reach faster device speed, and
Meet the rule of Moore's Law.
The eighties in last century to the nineties, academia just has begun to realize heterojunction structure based on silicon-based substrate
Research, until just realizing business application the beginning of this century.Wherein there are two kinds of representational stress application, Yi Zhongshi
The biaxial stress technology (Biaxial Technique) proposed by IBM；Another kind is the single shaft proposed by Intel
Stress technique (Uniaxial Technique)；I.e. SMT(Stress Memorization Technology) right
The raceway groove of NMOSFET applies tensile stress and improves the mobility of electronics, and selectivity (or embedding) epitaxial growth
Germanium silicon (SiGe structure) applies two kinds of techniques that compressive stress improves the mobility in hole to PMOSFET raceway groove
Method, thus improve the performance of device.Wherein, referring to the drawings 1, selective epitaxial growth SiGe technique shape
Become COMS device to generally include following steps: first to carry out step S100, carry out shallow trench isolation and make,
To form fleet plough groove isolation structure on substrate；Then carry out step S101, carry out trap injection, form p-type
Trap or N-type trap；Then carry out step S102, form grid；Carry out step S103 afterwards, be lightly doped
Inject, form leakage light-dope structure；Then carry out step S104, gate lateral wall makes grid the first side
Wall；Carry out step S105 afterwards, carry out selective epitaxial growth SiGe technique, formed at source and drain areas heavily doped
Miscellaneous SiGe structure；Carry out step S106, make grid the second side wall；Carry out step S107, carry out source
Leakage is injected to form source-drain electrode；Then carry out step S108, carry out pre-metal dielectric, through hole, metal plug
Making with metal level.
For selectivity (or embedding) epitaxial growth SiGe technique, research in large quantities has been had to find growth work
The gas composition of skill, flow, cavity reaction temperature, time, annealing temperature, time etc. can produce by counter stress
Impact, and set up wired upper real-time monitoring system to monitor the stability of above-mentioned technological parameter.But, these
It is all the performance only characterizing germanium silicon SiGe structure self, and SiGe structure and SI interface and SiGe
Structure and STI interface performance quality, can directly affect device performance, thus affect the work shape of whole circuit
State, the monitoring that existing monitoring system can not reflect, the performance at the two interface.It is typically only capable in work
When product goes wrong in skill research and development or production line, problem sample is carried out TEM section and studies interface
The most normal, the most good semiconductor process line method of real-time.
For SiGe structure and SI interface, it will usually be designed with large-area p-type heavy doping SiGe structure with
N-type trap PN junction, characterizes interfacial characteristics by the leakage current of this PN junction of on-line measurement.But for SiGe
Structure and STI interface, the most good on-line monitoring method.
Summary of the invention
The present invention provides a kind of monitoring method, to realize on-line monitoring SiGe structure and the mesh of STI interface performance
's.
For solving problem above, the present invention provides a kind of monitoring method, for on-line monitoring SiGe structure and STI
Interface performance, described monitoring method includes:
The domain of the area-type PN junction that design SiGe structure is formed with N-type trap；
Design multiple peripheral type PN junction parallel-connection structure, the junction area of the plurality of peripheral type PN junction and described
The junction area of long-pending type PN junction is identical；
On substrate, described peripheral type PN junction and area-type PN junction is formed in device manufacturing processes；
The leakage current of two kinds of PN junctions of on-line measurement record；
It is normalized calculating, calculates area-type PN junction normallized current IL respectivelyAPWith peripheral type PN junction
Normallized current ILEP；
Calculate the difference Δ IL, Δ IL=IL of normallized currentAP-ILEP；
Carry out ILAP、ILEPAnd the data analysis of Δ IL, it is judged that SiGe structure and the interface performance of STI.
Optionally, IL is carried outAP、ILEPAnd the data analysing method of Δ IL is: by ILAP、ILEPAnd Δ IL
Contrast with critical field, when PN junction has abnormal, ILAPAnd ILEPThe most abnormal；When SiGe structure and
During the exception of STI interface, ILAPNormally, ILEPAbnormal with Δ IL.
Optionally, formed on substrate during selectivity epitaxial growth SiGe technique forms COMS device
Two kinds of above-mentioned PN junctions, including:
Carry out shallow trench isolation to make, to form fleet plough groove isolation structure on substrate；
Carry out trap injection, form p-type trap or N-type trap, concurrently form peripheral type PN junction and area-type PN junction
N-type trap；
Form grid；
Carry out being lightly doped injection, form leakage light-dope structure；
Gate lateral wall makes grid the first side wall；
Carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas,
Peripheral type PN junction and the SiGe of area-type PN junction is formed in the N-type trap of peripheral type PN junction and area-type PN junction
Structure, to form peripheral type PN junction and area-type PN junction；
Make grid the second side wall, carry out source and drain inject to form source-drain electrode, and carry out pre-metal dielectric,
The making step of through hole, metal plug and metal level.
Optionally, described grid is polysilicon material.
Optionally, being injected the source-drain electrode forming p-type by the drain electrode of p-type doped source, described p-type is doped to boron
Doping.
Optionally, described selective epitaxial growth SiGe technique includes, the region to SiGe structure to be formed
Carry out back carving technology, then selective epitaxial growth SiGe structure
Compared with prior art, detection method provided by the present invention device formed during, shape simultaneously
Become peripheral type PN junction and area-type PN junction that junction area is identical, then measure the electric leakage analyzing two kinds of PN junctions
Stream, it is achieved judge the purpose of the interface performance of SiGe structure and STI.So, can be to the product on production line
It is monitored, it is not necessary to after product goes wrong, carry out TEM section again study, be greatly improved product good
Rate.
Accompanying drawing explanation
Fig. 1 is the flow chart that existing selective epitaxial growth SiGe technique forms COMS device；
Fig. 2 is the flow chart of embodiment of the present invention monitoring method；
Fig. 3 is area-type PN junction and the vertical view domain of marginality PN junction of embodiment of the present invention monitoring method；
Fig. 4 is the cross-section structure signal of part peripheral type PN junction and area-type PN junction in this enforcement monitoring method
Figure.
Detailed description of the invention
In the introduction it has been already mentioned that prior art does not has the SiGe structure to online product and SI interface
State carries out the method detected, and problem sample can only be carried out TEM section time product goes wrong on line
Study, have a strong impact on product yield.
To this end, the present invention provides a kind of monitoring method, for on-line monitoring SiGe structure and STI interface performance.
The core concept of the present invention is, realizes monitoring by the leakage current of monitoring SiGe structure and the interface of STI
The state at the interface of SiGe structure and STI.The PN junction of peripheral type is in addition to PN junction leakage current, at knot
Also there will be leakage current in the SiGe structure at edge and the interface of STI, this is owing to SiGe structure is to select
The epitaxial growth of type, i.e. be epitaxially formed SiGe structure based on Si " seed ", and STI material is SiO2,
Therefore the interface of SiGe structure and STI is not the most perfect, there will be leakage current yet.Peripheral type PN junction and
Area-type PN junction has an identical junction area, and peripheral type PN junction marginal existence larger area SiGe structure
The electric leakage at the interface of SiGe structure and STI is i.e. can get with the interface of STI, so both leakage currents of contrast
Stream, can realize being realized by the leakage current of monitoring SiGe structure and the interface of STI monitoring SiGe structure
Purpose with the state at the interface of STI.
Refer to Fig. 2, it is the flow chart of embodiment of the present invention monitoring method, and described method comprises the steps:
Step S010, the domain of the area-type PN junction that design SiGe structure is formed with N-type trap；
Step S011, designs multiple peripheral type PN junction parallel-connection structure, the junction of the plurality of peripheral type PN junction
Long-pending identical with the junction area of described area-type PN junction；
Step S012, forms above-mentioned two kind PN junction in device manufacturing processes on substrate；
Step S013, the leakage current of two kinds of PN junctions of on-line measurement record；
Step S014, is normalized calculating, calculates area-type PN junction normallized current IL respectivelyAPWith
Peripheral type PN junction normallized current ILEP；
Step S015, calculates the difference Δ IL, Δ IL=IL of normallized currentAP-ILEP；
Step S016, carries out data analysis: by ILAP、ILEPAnd Δ IL contrasts with critical field, work as PN
When having abnormal, ILAPAnd ILEPThe most abnormal；When SiGe structure and STI interface exception, ILAPJust
Often, ILEPAbnormal with Δ IL.Wherein, described critical field can be by online a large amount of ILAP、ILEPAnd Δ IL
Data are formulated and are obtained.
By specifically knot and in CMOS fabrication processing, the present invention is described in more detail below, its
In illustrate the preferred embodiments of the present invention, be described herein it should be understood that those skilled in the art can revise
The present invention, and still realize the advantageous effects of the present invention.Therefore, description below be appreciated that for
Those skilled in the art's is widely known, and is not intended as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.In the following description, it is not described in detail public affairs
The function known and structure, because they can make to due to the fact that unnecessary details and chaotic.Will be understood that
In the exploitation of any practical embodiments, it is necessary to make a large amount of implementation detail to realize the specific objective of developer,
Such as according to about system or about the restriction of business, an embodiment change into another embodiment.Separately
Outward, it should think that this development is probably complicated and time-consuming, but for people in the art
It it is only routine work for Yuan.
Referring to the drawings the present invention the most more particularly described below in the following passage.According to following explanation and
Claims, advantages and features of the invention will be apparent from.It should be noted that, accompanying drawing all uses the simplest
The form changed and all use non-ratio accurately, only in order to convenient, aid in illustrating the embodiment of the present invention lucidly
Purpose.
First, step S010 and S011, the area-type PN that design SiGe structure is formed are performed with N-type trap
The domain of knot, and design multiple peripheral type PN junction parallel-connection structure, the area of the plurality of peripheral type PN junction
With described area-type PN junction equal area.With reference to Fig. 3, wherein, 401 is the vertical view version of area-type PN junction
Figure, 402 is the vertical view domain of marginality PN junction.In the present embodiment, the domain 401 of described marginality PN junction
Can include all shapes of selective epitaxial growth SiGe structure in COMS technique, such as I-shaped,
" ten " font, " mouth " font etc..It is understood that the shape in Fig. 3 is only peripheral type PN junction
Knot and the detailed description of the invention of CMOS processing technology in the present embodiment, its layout shape is not limited only to Fig. 3
In shape, can include actual process produce in all distribution of shapes of SiGe structure, those skilled in the art
Can tie according to the core concept of the present invention and concrete device fabrication design peripheral type PN junction domain shape
Shape.
Then perform step S012, COMS device manufacturing processes is formed on substrate above-mentioned two kind
PN junction, is part peripheral type PN junction and area-type PN junction in this enforcement monitoring method with reference to Fig. 4, Fig. 4
Cross-sectional view.Described area-type PN junction has bigger junction area, and described peripheral type PN junction is on knot limit
The more contact surface with STI is had at edge.Wherein, process is utilized to can refer to background section and accompanying drawing 1:
First carry out step S100, carry out shallow trench isolation and make, to form fleet plough groove isolation structure on substrate
(STI) 403；Then carry out step S101, carry out trap injection, form p-type trap or N-type trap, in this step
In Zhou, concurrently form the N-type trap 405 of peripheral type PN junction and area-type PN junction；Then step S102 is carried out,
Forming grid, in the present embodiment, described grid is polysilicon material；Carry out step S103 afterwards, carry out light
Doping is injected, and forms leakage light-dope structure；Then carry out step S104, gate lateral wall makes grid the
One side wall；Carry out step S105 afterwards, carry out selective epitaxial growth SiGe technique, formed at source and drain areas
Heavily doped SiGe structure, in same step, in peripheral type PN junction and the N-type trap of area-type PN junction
Upper formation peripheral type PN junction and the SiGe structure 404 of area-type PN junction, form respectively peripheral type PN junction
402 and area-type PN junction 401；Proceed afterwards follow-up COMS processing step S106, S107 with
And S108, make grid the second side wall, carry out source and drain inject to form source-drain electrode, carry out pre-metal dielectric,
The making of through hole, metal plug and metal level, in the present embodiment, injects shape by the drain electrode of p-type doped source
Becoming the source-drain electrode of p-type, described p-type is doped to boron doping.Described selective epitaxial growth SiGe technique includes,
The region of SiGe structure to be formed is carried out back carving technology, then selective epitaxial growth SiGe structure.Tool
Body is in this enforcement, to the source drain region of COMS on silicon substrate and peripheral type PN junction and area-type PN
Tie region carries out back carving technology, is then based on Si " seed " and is epitaxially formed SiGe structure.
After form respectively peripheral type PN junction and area-type PN junction, carry out step S013, on-line measurement two
Plant the leakage current of PN junction and record data；Such as can be at the WAT measuring station after COMS metal level makes
During point, respectively the leakage current of described area-type PN junction and peripheral type PN junction is measured.
Carry out step S014 afterwards, be normalized calculating, calculate area-type PN junction normalization electricity respectively
Stream ILAPWith peripheral type PN junction normallized current ILEP；Then carry out step S015, calculate normallized current
Difference Δ IL, Δ IL=ILAP-ILEP.Wherein ILAPCharacterize the state of area-type PN junction, ILEPCharacterize
The state of peripheral type PN junction, the state at SiGe structure and STI interface, Δ IL characterize SiGe structure with
The state at STI interface.
Then perform step S016, carry out data and be analyzed: by ILAP、ILEPAnd Δ IL and critical field
Contrast, when PN junction has abnormal, ILAPAnd ILEPThe most abnormal；When SiGe structure and STI interface are abnormal
Time, ILAPNormally, ILEPAbnormal with Δ IL.Wherein, described critical field can be by online a large amount of ILAP、
ILEPAnd the formulation of Δ IL data obtains.The data of all like products generally can be utilized to draw out parameter curve
Table, customizes out rational scope.So can reflect SiGe structure and the STI interface performance of online product
State, it is not necessary to carrying out TEM section, to study interface the most normal.
Certainly, above-described embodiment is only knot and to the scheme in CMOS fabrication processing, this area skill
The monitoring method of the present invention can be tied according to the core concept of the present invention and arrive outside other selectivitys by art personnel
In epitaxial growth SiGe technique.
In sum, the monitoring method that the present invention provides, by formed the identical peripheral type PN junction of junction area and
Area-type PN junction, measures both leakage currents, obtains SiGe structure and STI by comparing and analysis
The state at interface.Adopt in such a way, can be directly by the interface of monitoring SiGe structure and STI
Leakage current monitors the state at the interface of SiGe structure and STI.Thus realize the real-time monitoring of product on line,
Carry out TEM section again without the generation of problem by the time and study interface the most normally, substantially increase product yield.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a monitoring method, for on-line monitoring SiGe structure and STI interface performance, described monitoring side
Method includes:
The domain of the area-type PN junction that design SiGe structure is formed with N-type trap；
Design multiple peripheral type PN junction parallel-connection structure, the junction area sum of the plurality of peripheral type PN junction and institute
The junction area stating area-type PN junction is identical；
On substrate, described peripheral type PN junction and area-type PN junction is formed in device manufacturing processes；
Peripheral type PN junction described in on-line measurement and the leakage current of area-type PN junction record；
It is normalized calculating, calculates area-type PN junction normallized current IL respectivelyAPWith multiple peripheral types
PN junction normallized current ILEP；
Calculate the difference Δ IL, Δ IL=IL of normallized currentAP-ILEP；
Carry out ILAP、ILEPAnd the data analysis of Δ IL, it is judged that SiGe structure and the interface performance of STI.
2. monitoring method as claimed in claim 1, it is characterised in that: carry out ILAP、ILEPAnd Δ IL
Data analysing method is: by ILAP、ILEPAnd Δ IL contrasts with critical field, when PN junction has abnormal, ILAP
And ILEPThe most abnormal；When SiGe structure and STI interface exception, ILAPNormally, ILEPAbnormal with Δ IL.
3. monitoring method as claimed in claim 1, it is characterised in that: at selective epitaxial growth SiGe
During technique forms COMS device, substrate forms above-mentioned two kind PN junction.
4. monitoring method as claimed in claim 3, it is characterised in that: on substrate, form described peripheral type
The junction area of PN junction includes with the step of described area-type PN junction:
Carry out shallow trench isolation to make, to form fleet plough groove isolation structure on substrate；
Carry out trap injection, form p-type trap or N-type trap, concurrently form peripheral type PN junction and area-type PN junction
N-type trap；
Form grid；
Carry out being lightly doped injection, form leakage light-dope structure；
Gate lateral wall makes grid the first side wall；
Carry out selective epitaxial growth SiGe technique, form heavily doped SiGe structure at source and drain areas,
Peripheral type PN junction and the SiGe of area-type PN junction is formed in the N-type trap of peripheral type PN junction and area-type PN junction
Structure, to form peripheral type PN junction and area-type PN junction；
Make grid the second side wall, carry out source and drain inject to form source-drain electrode, and carry out pre-metal dielectric,
The making step of through hole, metal plug and metal level.
5. monitoring method as claimed in claim 4, it is characterised in that: described grid is polysilicon material.
6. monitoring method as claimed in claim 4, it is characterised in that: injected by the drain electrode of p-type doped source
Forming the source-drain electrode of p-type, described p-type is doped to boron doping.
7. monitoring method as claimed in claim 4, it is characterised in that: described selective epitaxial growth SiGe
Technique includes, the region of SiGe structure to be formed is carried out back carving technology, then selective epitaxial growth SiGe
Structure.
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| CN103943531A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for monitoring auto-doping boron concentration in germanium-silicon process on line |
Citations (4)
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| CN86105604A (en) * | 1985-07-24 | 1987-02-11 | 海因茨·克鲁格 | The circuit structure that is used for testing integrated circuit components |
| US5486772A (en) * | 1994-06-30 | 1996-01-23 | Siliconix Incorporation | Reliability test method for semiconductor trench devices |
| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN102800594A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube |
-
2014
- 2014-03-24 CN CN201410109846.9A patent/CN103887202B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105604A (en) * | 1985-07-24 | 1987-02-11 | 海因茨·克鲁格 | The circuit structure that is used for testing integrated circuit components |
| US5486772A (en) * | 1994-06-30 | 1996-01-23 | Siliconix Incorporation | Reliability test method for semiconductor trench devices |
| CN101770967A (en) * | 2009-01-03 | 2010-07-07 | 上海芯豪微电子有限公司 | Test method, device and system of common substrate integrated circuit |
| CN102800594A (en) * | 2011-05-26 | 2012-11-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of PMOS (p-channel metal oxide semiconductor) tube |
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