CN115358170A - Contact resistance acquisition method and device, electronic equipment and storage medium - Google Patents
Contact resistance acquisition method and device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN115358170A CN115358170A CN202210989348.2A CN202210989348A CN115358170A CN 115358170 A CN115358170 A CN 115358170A CN 202210989348 A CN202210989348 A CN 202210989348A CN 115358170 A CN115358170 A CN 115358170A
- Authority
- CN
- China
- Prior art keywords
- transistor device
- contact
- determining
- length
- contact structures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
The disclosure provides a contact resistance acquisition method, a contact resistance acquisition device, an electronic device and a storage medium. The method includes applying to a model simulation of a transistor device, the transistor device including an active region and a gate overlying the active region and a plurality of contact structures electrically connected to the source or drain, the method including: determining the type of a transistor device, and determining the design parameters of the transistor device corresponding to the type according to the type of the transistor device; determining a contact resistance of the transistor device according to a design parameter of the transistor device, wherein the contact resistance is an equivalent resistance of the plurality of contact structures. According to the method, the resistance value of the contact resistor is calculated by adopting corresponding design parameters according to the types of different transistor devices, so that the electrical characteristics of the transistor devices are facilitated to be accurate, and the simulation precision and reliability of the transistor devices are improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for obtaining a contact resistance, an electronic device, and a storage medium.
Background
A large number of Metal-Oxide-Semiconductor Field-Effect transistors (Metal-Oxide-Semiconductor transistors) are used in a Dynamic Random Access Memory (DRAM). With the shrinking of DRAM technology nodes, various design rules are derived for the design of transistor devices, so that structures such as gates, sources, drains, etc. in transistors exhibit various layouts, and accordingly, the contact resistance of transistors also varies with the variation of the design rules.
When the transistor device is simulated, the calculation method or the empirical value of the contact resistance generated by the source electrode or the drain electrode is applied to the structural layout of the transistor under various currently derived design rules according to the calculation method or the empirical value of the contact resistance determined by the structural layout of the transistor under the previous single design rule.
However, the calculation accuracy of the contact resistance obtained by the above method is low, thereby reducing the simulation accuracy and reliability.
Disclosure of Invention
The disclosure provides a contact resistance obtaining method, a contact resistance obtaining device, an electronic device and a storage medium, which are used for improving the calculation accuracy of contact resistance and further improving the simulation accuracy and reliability.
According to some embodiments, the present disclosure provides a contact resistance obtaining method applied to model simulation of a transistor device, the transistor device including an active region, a gate electrode on the active region, and a plurality of contact structures electrically connected to the source electrode or the drain electrode; it is characterized by comprising: determining the type of the transistor device, and determining the design parameters of the transistor device according to the type of the transistor device; determining the contact resistance of the transistor device according to the design parameters of the transistor device; wherein the contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
In some embodiments, the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure.
In some embodiments, determining the type of transistor device includes: obtaining the channel type of a transistor device, and determining the type of the transistor device to comprise a P-type transistor device or an N-type transistor device according to the channel type of the transistor device; and/or obtaining the gate thickness of the transistor device, and determining the type of the transistor device to be a thick gate transistor device or a thin gate transistor device according to the gate thickness of the transistor device; the thickness of a grid electrode of the thick grid transistor device meets a first preset thickness range; the thin gate transistor device meets a second preset thickness range; and/or obtaining a grid end structure of the transistor device, and determining the type of the transistor device to be a hammerhead transistor device or a hammerhead-free transistor device according to the grid end structure of the transistor device.
In some embodiments, obtaining a gate end structure for a transistor device includes: obtaining the length of a grid electrode of a transistor device, and determining the end structure of the grid electrode of the transistor device according to the type of a channel of the transistor device, the thickness of the grid electrode of the transistor device and the length of the grid electrode of the transistor device; the grid end structure of the transistor device comprises a hammerhead type and a hammerhead-free type.
In some embodiments, determining a gate end structure of the transistor device based on a channel type of the transistor device, a gate thickness of the transistor device, and a gate length of the transistor device comprises: determining a preset threshold value of the gate length of the transistor device according to the channel type of the transistor device and the gate thickness of the transistor device; judging whether the length of a grid electrode of the transistor device is lower than a preset threshold value or not; if yes, the structure of the grid end part of the transistor device is in a hammerhead type; otherwise, the gate terminal structure of the transistor device is hammerless.
In some embodiments, the design parameters of the transistor device include: the length of the active region, the interval between two adjacent contact structures and the maximum length of the contact structures; a minimum length between the contact structure and an edge of the active region; determining a contact resistance of the transistor device based on design parameters of the transistor device, comprising: determining the number of contact structures according to design parameters of the transistor device; determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures; and acquiring the standard unit resistance of the contact structures, and determining the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures.
In some embodiments, determining the number of contact structures based on design parameters of the transistor device includes: determining the number of contact structures based on a first formula according to design parameters of the transistor device; wherein the first formula comprises: n = ceiling [ (W-2 × S + P)/Lmax ]; wherein N is the number of contact structures and is a positive integer; ceiling [ ] is a calculation rule of rounding up; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the interval between two adjacent contact structures; lmax is the maximum length of the contact structure.
In some embodiments, determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures includes: determining the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of the contact structures; wherein the second formula comprises: lg = (W-2 XS + P)/N-P; wherein Lg is the length of the contact structure; n is the number of contact structures and is a positive integer; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the spacing between two adjacent contact structures.
In some embodiments, determining the contact resistance of the transistor device based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures comprises: determining the contact resistance of the transistor device based on a third formula according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures; wherein the third formula comprises: rlicon = Rx × Lg/N; wherein, rsilicon is the contact resistance of the transistor device; rx is the standard unit resistance of the contact structure; lg is the length of the contact structure; n is the number of the contact structures and is a positive integer.
In some embodiments, obtaining a standard specific resistance of a contact structure comprises: determining a standard resistance and a standard length of the contact structure according to the type of the transistor device; and obtaining the standard unit resistance of the contact structure according to the standard resistance and the standard length of the contact structure.
According to some embodiments, a second aspect of the present disclosure provides a contact resistance obtaining apparatus applied to model simulation of a transistor device, the transistor device including an active region and a gate electrode on the active region and a plurality of contact structures electrically connected to a source electrode or a drain electrode; it is characterized by comprising: the first determining unit is used for determining the type of the transistor device and determining the design parameters of the transistor device according to the type of the transistor device; a second determination unit for determining a contact resistance of the transistor device according to a design parameter of the transistor device; wherein the contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
In some embodiments, the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure.
In some embodiments, the design parameters of the transistor device include: the length of the active region, the interval between two adjacent contact structures and the maximum length of the contact structures; a minimum length between the contact structure and an edge of the active region; the second determining unit is specifically used for determining the number of the contact structures according to the design parameters of the transistor device; the second determining unit is specifically used for determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures; the second determining unit is specifically further configured to obtain a standard unit resistance of the contact structures, and determine the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures, and the standard unit resistance of the contact structures.
According to some embodiments, a third aspect of the present disclosure provides an electronic device comprising: a processor, and a memory communicatively coupled to the processor; the memory stores computer execution instructions; the processor executes computer-executable instructions stored by the memory to implement the method of the first aspect.
According to some embodiments, a fourth aspect of the present disclosure provides a computer-readable storage medium having stored therein computer-executable instructions for implementing the method as in the first aspect when executed by a processor.
The embodiment of the disclosure provides a method, a device, an electronic device and a storage medium for obtaining a contact resistance, which are applied to model simulation of a transistor device, wherein the transistor device comprises an active area, a grid electrode positioned on the active area and a plurality of contact structures electrically connected with a source electrode or a drain electrode, and the method comprises the following steps: determining the type of the transistor device, and determining the design parameters of the transistor device according to the type of the transistor device; determining a contact resistance of the transistor device according to a design parameter of the transistor device, wherein the contact resistance is an equivalent resistance of the plurality of contact structures. In the embodiment of the disclosure, the resistance value of the contact resistor is calculated by adopting the corresponding design parameters according to the types of different transistor devices, so that the electrical characteristics of the transistor devices are more accurate, and the simulation precision and reliability of the transistor devices are improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a flowchart of a method for obtaining contact resistance according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a transistor device without a hammer head according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a transistor device with a hammer head according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a contact resistance obtaining apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.
Specific embodiments of the present disclosure have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the concepts of the disclosure to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure.
A large number of Metal-Oxide-Semiconductor Field-Effect transistors (Metal-Oxide-Semiconductor transistors) are used in a Dynamic Random Access Memory (DRAM). With the shrinking of DRAM technology nodes, various design rules are derived for the design of transistor devices, so that the gate, source, drain, contact structures, etc. in the transistor exhibit various layouts, and accordingly, the contact resistance of the transistor also varies with the variation of the design rules.
In the process of simulating the transistor device, the calculation mode of the contact resistance generated by the contact structure arranged on the source electrode or the drain electrode is to apply the calculation method or the empirical value of the contact resistance determined according to the layout of the transistor under the previous single design rule to the layout of the transistor under various currently derived design rules. However, the method of calculating the contact resistance based on a single design rule does not match the existing layout, and large errors are caused to device and circuit simulation.
Based on this, the contact resistance obtaining method, device, electronic device and storage medium provided by the embodiments of the present disclosure aim to solve the above technical problems in the prior art. And calculating the resistance value of the contact resistor by adopting corresponding design parameters according to different types of transistor devices so as to obtain accurate electrical characteristics of the device and reliable circuit simulation values.
The following describes the technical solutions of the present disclosure and how to solve the above technical problems in specific embodiments. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present disclosure will be described below with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for acquiring contact resistance according to an embodiment of the present disclosure. The method is applied to model simulation of the transistor device.
The execution subject of the method can be a contact resistance acquisition device, and also can be a model simulation device of a transistor device integrated with the contact resistance acquisition device. The apparatus may be implemented by a computer program, e.g., application software or the like; alternatively, the apparatus may also be implemented as a medium storing the relevant computer program, for example, a usb disk, a cloud disk, or the like; still alternatively, the apparatus may also be implemented by a physical apparatus, such as a computer, into which the associated computer program is integrated or installed. The following description will be given taking the actuator as a contact resistance obtaining device as an example.
As shown in fig. 1, the method may include the steps of:
s100, determining the type of a transistor device, and determining design parameters of the transistor device according to the type of the transistor device;
s200, determining the contact resistance of the transistor device according to the design parameters of the transistor device; wherein the contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
The transistor device includes an active region, a gate electrode on the active region, and a plurality of contact structures electrically connected to the source electrode or the drain electrode. Contact structures, such as wires connecting the source or drain, are provided to contact the resistor. The contact resistance affects the intrinsic characteristics of the transistor device, and the resistance value of the contact resistance affects the model simulation result of the transistor device.
In the layout of different types of transistor devices, there are differences in the feature sizes of the gate, the contact structure, and the distribution over the active area, which all affect the calculation of the contact resistance. In this embodiment, the resistance of the contact resistor is calculated according to the type of the transistor device by using corresponding design parameters, so as to obtain accurate electrical characteristics of the device and reliable circuit simulation values.
Fig. 2 is a schematic structural diagram of a transistor device without a hammer head according to an embodiment of the present disclosure. Fig. 3 is a schematic structural diagram of a transistor device with a hammer head according to an embodiment of the present disclosure. The design parameters of the transistor device are described below with reference to fig. 2 and 3.
As shown in fig. 2 and 3, the semiconductor device includes an active region, a gate electrode on the active region, and a plurality of contact structures symmetrically distributed on both sides of the gate electrode. Wherein the extension length of the grid electrode in the y direction is larger than the length of the active region in the y direction. The feature size of each contact structure is the same. In fig. 2 and 3, four contact structures are taken as an example, and two contact structures are symmetrically distributed on two sides of the gate.
Wherein the design parameters of the transistor device shown in fig. 2 and 3 include: a length L of the gate in the x direction (simply referred to as "gate length" in the present disclosure); a length W of the active region in the y direction (simply referred to as "length of active region" in the present disclosure); a length Lg of the contact structure in the y direction (simply referred to as "length of the contact structure" in the present disclosure), specifically Lg1 in fig. 2 or Lg2 in fig. 3; the interval P in the y direction between two adjacent contact structures; the minimum length S in the y-direction between the contact structure and the edge of the active region, in particular S1 in fig. 2 or S2 in fig. 3.
In addition, the design parameters of the transistor devices not shown in fig. 2 and 3 include: the maximum length Lmax of the contact structure. Lmax characterizes the upper limit on the length of the contact structure in the design rules for this type of transistor device. The design parameters of the transistor device not shown in fig. 2 and 3 also include: and (6) the thickness of the grid electrode. The grid electrode comprises a grid electrode metal layer and a grid electrode dielectric layer, and the thickness of the grid electrode is the characteristic dimension of the grid electrode dielectric layer in the direction perpendicular to the plane of the active region.
A description will be given below of a calculation process for calculating equivalent resistance values of a plurality of contact structures located on the same side of the gate electrode in the transistor device according to the above-described design parameters.
In some embodiments, the determining the contact resistance of the transistor device according to the design parameter of the transistor device in step S200 includes:
s210, determining the number of contact structures according to design parameters of a transistor device;
s220, determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures;
and S230, acquiring the standard unit resistance of the contact structures, and determining the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures.
It should be noted that the number of contact structures determined in step S210 refers to the number of contact structures located on the gate side, and the contact resistance of the transistor device determined in step S230 refers to the equivalent resistance of the contact structures located on the gate side. According to the symmetrical characteristic, the equivalent resistance of the contact structure positioned at the other side of the gate can be obtained.
In one possible embodiment, in step S210, determining the number of contact structures according to design parameters of the transistor device specifically includes: a table or a database is pre-established, and the corresponding relation between the design parameters and the number of the contact structures is determined; the number of contact structures is determined by looking up the index according to the design parameters of the transistor device.
In another possible embodiment, in step S210, determining the number of contact structures according to the design parameters of the transistor device includes:
determining the number of contact structures based on a first formula according to design parameters of the transistor device; wherein the first formula comprises:
N＝ceiling[(W-2×S+P)/Lmax]；
wherein N is the number of contact structures and is a positive integer; ceiling [ ] is a calculation rule of rounding up; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the interval between two adjacent contact structures; lmax is the maximum length of the contact structure.
Specifically, the length W of the active region minus the minimum length 2S between two contact structures and the edge of the active region is equal to the sum of the length of a first number (assumed to be a) of contact structures and the length of the first number minus one (i.e., a-1) of the spacing P between two adjacent contact structures. (W-2 XS + P) is then equal to the sum of the length of the first number (i.e., a) of contact structures and the length of the spacing P between the first number (i.e., a) of two adjacent contact structures. Lmax is the maximum length of the contact structure, (W-2 XS + P) divided by Lmax is an integer, the maximum number of contact structures that can be arranged on one side of the gate can be obtained.
Further, in some embodiments, in step S220, determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures includes:
determining the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of the contact structures; wherein the second formula comprises:
Lg＝(W-2×S+P)/N-P；
wherein Lg is the length of the contact structure; n is the number of contact structures and is a positive integer; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the spacing between two adjacent contact structures.
Specifically, the aforementioned known (W-2 XS + P) is then equal to the length of the first number (i.e., a) of contact structures and the length of the spacing P between the first number (i.e., a) of two adjacent contact structures. Since N is a rounded result, (W-2 XS + P)/N may not be exactly equal to Lmax; lg cannot be determined directly by subtracting P from Lmax.
Further, in some embodiments, in the step S230, determining the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures, and the standard unit resistance of the contact structures includes:
determining the contact resistance Rsilicon of the transistor device based on a third formula according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures; wherein the third formula comprises:
Rlicon＝Rx×Lg/N；
wherein, rsilicon is the contact resistance of the transistor device; rx is the standard unit resistance of the contact structure; lg is the length of the contact structure; n is the number of contact structures and is a positive integer.
Specifically, the resistance value of each contact structure is the same. The contact resistor Rsilicon is an equivalent resistance value of a plurality of contact structures which are arranged on the same side of the grid electrode and connected in parallel. Therefore, it can be understood that (Rx × Lg) is the resistance value of a single contact structure; (Rx Xlg/N) is the equivalent resistance of N contact structures connected in parallel.
Further, in some embodiments, in step S230, the obtaining the standard unit resistance of the contact structure specifically includes:
s231, determining a standard resistance Rs and a standard length Ls of a contact structure of the transistor device according to the type of the transistor device;
and S232, obtaining the standard unit resistance Rx of the contact structure according to the standard resistance Rs and the standard length Ls of the contact structure.
In the simulation program for implementing the above-described resistance calculation method for the contact structure, each design parameter related to each transistor device to be simulated may be directly used as an input. In a possible implementation, the technician inputs the specific values of each design parameter one by one before simulation. In another possible embodiment, the simulation program may obtain the specific value of each design parameter by reading the first file, where the specific value of each design parameter is directly recorded in the first file.
In this embodiment, through counting the design parameters in different design layouts, it is found that values of some design parameters are the same in various design layouts, and values of some design parameters are different in each design layout.
In some embodiments, the intervals P between two adjacent contact structures in the various design layouts have the same value. Optionally, P is set to be a fixed value in the simulation program, so that repetitive input is reduced, which is beneficial to saving manpower, or reducing the size of the first file.
In this embodiment, the values of the design parameters and the types of the transistors are found to have an association relationship by further performing statistics on the design parameters in different design layouts. Optionally, the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure. Wherein transistor devices can be classified according to channel type into P-type transistor devices (herein abbreviated as "PMOS") and N-type transistor devices (herein abbreviated as "NMOS"); transistors can be classified into thick gate transistor devices (thick MOS) and thin gate transistor devices (thin MOS) according to gate thickness; transistors can be classified into hammerhead type transistor devices (with hammerhead) and hammerhead type transistor devices (with hammerhead) depending on the gate end structure.
Specifically, the same design parameter has different values in PMOS and NMOS, and/or different values in thick MOS and thin MOS, and/or different values in hammerhead transistor device and hammerhead-free transistor device.
In some embodiments, the value of the design parameter may depend only on whether it is a hammerhead-type transistor device or a hammerhead-free-type transistor device. For example, no matter the transistor device is a thick gate transistor device or a thin gate transistor device, no matter the transistor device is a PMOS or an NMOS, for a hammerhead-free transistor device, the minimum length S between the contact structure and the edge of the active region has the same value, assuming that m1; for hammerhead transistor devices, the minimum length S between the contact structure and the edge of the active region has the same value, assumed to be m2, where m1 is not equal to m2.
Optionally, manually inputting before the simulation or recording the type of the transistor device in a first file as a hammerhead-free type transistor device or a hammerhead type transistor device; and calling the corresponding S value according to the identified type of the transistor device. If the value of S is a multi-bit decimal, the type of the input transistor device is more favorable for reducing the input error rate and also favorable for quickly checking the input error compared with the input specific numerical value.
In some embodiments, the value of the design parameter may depend on whether it is a hammerhead or hammerhead-less transistor device, and whether it is a thick gate or thin gate transistor device. For example, for thin gate transistor devices, whether hammerhead or hammerhead-less transistor devices, whether PMOS or NMOS, the minimum length S between the contact structure and the edge of the active region takes the same value, assuming m1. For a thick gate transistor device, if the thick gate transistor device is a hammerhead-free transistor device, whether the thick gate transistor device is a PMOS or NMOS, the minimum length S between the contact structure and the edge of the active region has the same value, and is assumed to be m2. For a thick gate transistor device, if the thick gate transistor device is a hammerhead transistor device, whether it is a PMOS or NMOS, the minimum length S between the contact structure and the edge of the active region has the same value, assuming m3. Wherein m1, m2 and m3 are different.
Optionally, before simulation, manually inputting or recording the type of the transistor device in a first file as a hammerhead-free transistor device or a hammerhead-type transistor device, and whether the transistor device is a thick gate transistor device or a thin gate transistor device; and calling the corresponding S value according to the identified type of the transistor device. If the value of S is a multi-bit decimal, the type of the input transistor device is more favorable for reducing the input error rate and also favorable for quickly checking the input error compared with the input specific numerical value.
In some embodiments, the determining the type of the transistor device in step S100 includes: acquiring the channel type of a transistor device, and determining the type of the transistor device to comprise a P-type transistor device or an N-type transistor device according to the channel type of the transistor device;
and/or the presence of a gas in the atmosphere,
obtaining the gate thickness of a transistor device, and determining the type of the transistor device to be a thick gate transistor device or a thin gate transistor device according to the gate thickness of the transistor device; the gate thickness of the thick gate transistor device meets a first preset thickness range; the thin gate transistor device meets a second preset thickness range;
and/or the presence of a gas in the atmosphere,
and obtaining a grid end structure of the transistor device, and determining the type of the transistor device to be a hammerhead transistor device or a hammerhead-free transistor device according to the grid end structure of the transistor device.
Wherein for determining whether the type of transistor device is a thick gate transistor device or a thin gate transistor device: one possible implementation is: the type of transistor device is manually entered prior to simulation or recorded directly in a first file.
Another possible implementation is: manually inputting before simulation or directly recording the gate thickness of the transistor device in a first file, and comparing the gate thickness with a preset thickness range to determine whether the transistor device is a thick gate transistor device or a thin gate transistor device.
For determining the type of transistor device as being either hammerhead type transistor device or hammerhead free type transistor device, one possible embodiment is: the type of transistor device is manually entered prior to simulation or recorded directly in a first file.
Another possible implementation is: obtaining the gate length of a transistor device, and determining the gate end structure of the transistor device according to the channel type of the transistor device, the gate thickness of the transistor device and the gate length of the transistor device; the grid end structure of the transistor device comprises a hammerhead type and a hammerhead-free type.
Further, in some embodiments, determining a gate end structure of the transistor device according to a channel type of the transistor device, a gate thickness of the transistor device, and a gate length of the transistor device specifically includes: establishing a table or a database in advance, and determining the corresponding relation among the channel type, the gate thickness, the gate length and the gate end structure of the transistor device; by looking up the index, the gate end structure is determined.
Further, in some embodiments, determining a gate end structure of the transistor device according to a channel type of the transistor device, a gate thickness of the transistor device, and a gate length of the transistor device specifically includes:
determining a preset threshold value of the gate length of the transistor device according to the channel type of the transistor device and the gate thickness of the transistor device; judging whether the length of a grid electrode of the transistor device is lower than a preset threshold value or not; if yes, the structure of the grid end part of the transistor device is in a hammerhead type; otherwise, the gate terminal structure of the transistor device is hammerless.
For example, for a thin-gate transistor device, whether the thin-gate transistor device is a PMOS or an NMOS, if the gate length L is smaller than the value a1, the gate end structure of the transistor device is determined to be a hammerhead type; otherwise, the hammer-free type is adopted. For a thick gate transistor device, if the thick gate transistor device is an NMOS, if the gate length L is smaller than a value a2, determining that the gate end structure of the transistor device is in a hammerhead type; otherwise, the hammer-free type is adopted. For a thick gate transistor device, if the thick gate transistor device is a PMOS, if the gate length L is smaller than a value a3, determining that the gate end structure of the transistor device is in a hammerhead type; otherwise, the hammer-free type is adopted. The numerical values a1, a2, and a3 may be the same or different.
In some embodiments, in the simulation program, the parameter type =1 is set to characterize the hammerless type; the parameter type =2 is set to characterize a hammerhead type. Further, other parameters can be set for representing PMOS and NMOS; other parameters may also be set for characterizing thick and thin gates.
The method comprises the following specific steps:
(1) A simulation file is received, the simulation file including the type of transistor device and a portion of the design parameters. For example, thin gate N-type transistor devices are characterized by Ntn, with a gate length L of 0.2 μm; the active region length W is 3.2 μm.
(2) Determining a gate end structure: type = f1 (W, L, device type). Wherein f1 is a function of the active region length W, the gate length L, and the type device type of the transistor device extracted from the design rule, the function f1 is not a continuous function, and type is a specific data point. The value of the device type can be set, and the type of the characteristic transistor device is PMOS or NMOS, thick gate or thin gate. For example, device type =1 is set, and a thin gate NMOS is characterized; setting device type =2, and representing a thin gate PMOS; setting device type =3, and representing a thick gate NMOS; device type =4 is set, and thick gate PMOS is characterized.
(3) Calculating the number of contact structures: n = (W-2S + P1)/Lmax; s = f2 (type, S, W, L, device type). Where Lmax is a fixed value in the design rule. f2 is the type of the end structure of the grid electrode, the length W of the active region, the length L of the grid electrode and the type device of the transistor device in the design rule; a function of the minimum length S between the contact structure and the edge of the active area, the function f2 not being a continuous function, S being a specific data point. Wherein N is an integer.
(4) Calculating the length of the contact structure: lg = (W-2 x S + P1)/N-P1.
(5) Calculating the equivalent resistance of a plurality of contact structures: rlicon = Rs/Ls × Lg/N.
The contact resistance obtaining method provided by the embodiment of the disclosure is applied to model simulation of a transistor device, the transistor device comprises an active region, a grid electrode positioned on the active region and a plurality of contact structures electrically connected with a source electrode or a drain electrode, and the method comprises the following steps: determining the type of a transistor device, and determining the design parameters of the transistor device corresponding to the type according to the type of the transistor device; determining a contact resistance of the transistor device according to a design parameter of the transistor device, wherein the contact resistance is an equivalent resistance of the plurality of contact structures. In the embodiment of the disclosure, the resistance value of the contact resistor is calculated by adopting corresponding design parameters according to the types of different transistor devices, so that the electrical characteristics of the transistor devices are more accurate, and the simulation precision and reliability of the transistor devices are improved.
The contents and effects of the apparatus, the electronic device, and the storage medium corresponding to the contact resistance obtaining method provided in the above embodiments can be referred to in the method section below.
Fig. 4 is a schematic structural diagram of a contact resistance obtaining apparatus according to an embodiment of the present disclosure. The contact resistance acquisition device is applied to model simulation of a transistor device, wherein the transistor device comprises an active region, a grid electrode and a plurality of contact structures, the grid electrode is located on the active region, and the contact structures are electrically connected with a source electrode or a drain electrode.
As shown in fig. 4, the contact resistance obtaining apparatus includes:
a first determining unit 10, configured to determine a type of a transistor device, and determine a design parameter of the transistor device according to the type of the transistor device;
a second determining unit 20, configured to determine a contact resistance of the transistor device according to a design parameter of the transistor device; wherein the contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
In some embodiments, the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure.
In some embodiments, the first determining unit 10 is specifically configured to obtain a channel type of a transistor device, and determine, according to the channel type of the transistor device, that the type of the transistor device includes a P-type transistor device or an N-type transistor device; and/or the first determining unit 10 is specifically configured to obtain a gate thickness of the transistor device, and determine, according to the gate thickness of the transistor device, that the type of the transistor device is a thick-gate transistor device or a thin-gate transistor device; the thickness of a grid electrode of the thick grid transistor device meets a first preset thickness range; the thin gate transistor device meets a second preset thickness range; and/or the first determining unit 10 is specifically configured to obtain a gate end structure of the transistor device, and determine, according to the gate end structure of the transistor device, that the type of the transistor device is a hammerhead transistor device or a hammerhead-free transistor device.
In some embodiments, the first determining unit 10 is specifically configured to obtain a gate length of a transistor device, and determine a gate end structure of the transistor device according to a channel type of the transistor device, a gate thickness of the transistor device, and the gate length of the transistor device; the grid end structure of the transistor device comprises a hammerhead type and a hammerhead-free type.
In some embodiments, the first determining unit 10 is specifically configured to determine a preset threshold of a gate length of the transistor device according to a channel type of the transistor device and a gate thickness of the transistor device; the first determining unit 10 is further configured to specifically determine whether a gate length of the transistor device is lower than a preset threshold; if yes, the structure of the grid end part of the transistor device is in a hammerhead type; otherwise, the gate terminal structure of the transistor device is hammerless.
In some embodiments, the design parameters of the transistor device include: the length of the active region, the interval between two adjacent contact structures and the maximum length of the contact structures; a minimum length between the contact structure and an edge of the active region; a second determining unit 20, specifically configured to determine the number of contact structures according to design parameters of the transistor device; the second determining unit 20 is further configured to determine the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures; the second determining unit 20 is further configured to obtain a standard unit resistance of the contact structures, and determine the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures, and the standard unit resistance of the contact structures.
In some embodiments, the second determining unit 20 is specifically configured to determine the number of contact structures based on a first formula according to design parameters of the transistor device; wherein the first formula comprises: n = ceiling [ (W-2 × S + P)/Lmax ]; wherein N is the number of contact structures and is a positive integer; ceiling [ ] is a calculation rule of rounding up; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the interval between two adjacent contact structures; lmax is the maximum length of the contact structure.
In some embodiments, the second determining unit 20 is specifically configured to determine the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of the contact structures; wherein the second formula comprises: lg = (W-2 × S + P)/N-P; wherein Lg is the length of a single contact structure; n is the number of the contact structures and is a positive integer; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the spacing between two adjacent contact structures.
In some embodiments, the second determining unit 20 is specifically configured to determine the contact resistance of the transistor device based on a third formula according to the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures; wherein the third formula comprises: r = Rx × Lg/N; wherein Rx is a standard unit resistance; lg is the length of the contact structure; n is the number of contact structures and is a positive integer.
In some embodiments, the second determining unit 20 is specifically configured to determine a standard resistance and a standard length of the contact structure according to a type of the transistor device; the second determining unit 20 is further configured to obtain a standard unit resistance of the contact structure according to the standard resistance and the standard length of the contact structure.
The contact resistance obtaining device provided by the embodiment of the disclosure is applied to a model simulation transistor device of a transistor device, and comprises an active region, a grid electrode positioned on the active region and a plurality of contact structures electrically connected with a source electrode or a drain electrode, wherein the contact resistance obtaining device comprises: a first determining unit 10, configured to determine a type of a transistor device, and determine a design parameter of the transistor device according to the type of the transistor device; a second determining unit 20, configured to determine a contact resistance of the transistor device according to a design parameter of the transistor device; wherein the contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures. In the embodiment of the disclosure, the resistance value of the contact resistor is calculated by adopting corresponding design parameters according to the types of different transistor devices, so that the electrical characteristics of the transistor devices are more accurate, and the simulation precision and reliability of the transistor devices are improved.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, and as shown in fig. 5, the electronic device includes:
a processor (processor) 291, the electronic device further including a memory (memory) 292; a Communication Interface 293 and bus 294 may also be included. The processor 291, the memory 292, and the communication interface 293 may communicate with each other through the bus 294. Communication interface 293 may be used for the transmission of information. The processor 291 may call logic instructions in the memory 292 to perform the methods of the foregoing embodiments.
Further, the logic instructions in the memory 292 may be implemented in software functional units and stored in a computer readable storage medium when sold or used as a stand-alone product.
The memory 292 is a computer-readable storage medium that can be used for storing software programs, computer-executable programs, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 291 executes the software programs, instructions and modules stored in the memory 292 to execute functional applications and data processing, i.e., to implement the methods in the above-described method embodiments.
The memory 292 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal device, and the like. Further, the memory 292 may include a high speed random access memory and may also include a non-volatile memory.
The present disclosure provides a computer-readable storage medium having stored therein computer-executable instructions for implementing the methods provided by the foregoing embodiments when executed by a processor.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (15)
1. A contact resistance obtaining method is applied to model simulation of a transistor device, wherein the transistor device comprises an active area, a grid electrode and a plurality of contact structures, the grid electrode is located on the active area, and the contact structures are electrically connected with a source electrode or a drain electrode; it is characterized by comprising the following steps:
determining the type of the transistor device, and determining design parameters of the transistor device according to the type of the transistor device;
determining a contact resistance of the transistor device according to a design parameter of the transistor device; wherein a contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
2. The method of claim 1, wherein the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure.
3. The method of claim 1, wherein the determining the type of the transistor device comprises:
obtaining the channel type of the transistor device, and determining that the type of the transistor device comprises a P-type transistor device or an N-type transistor device according to the channel type of the transistor device;
and/or the presence of a gas in the atmosphere,
obtaining the gate thickness of the transistor device, and determining the type of the transistor device to be a thick gate transistor device or a thin gate transistor device according to the gate thickness of the transistor device; the thickness of a grid electrode of the thick grid transistor device meets a first preset thickness range; the thin gate transistor device meets a second preset thickness range;
and/or the presence of a gas in the gas,
obtaining a gate end structure of the transistor device, and determining the type of the transistor device to be a hammerhead transistor device or a hammerhead-free transistor device according to the gate end structure of the transistor device.
4. The method of claim 3, wherein obtaining the gate end structure of the transistor device comprises:
obtaining the gate length of the transistor device, and determining the gate end structure of the transistor device according to the channel type of the transistor device, the gate thickness of the transistor device and the gate length of the transistor device; wherein the gate terminal structure of the transistor device comprises a hammerhead type and a hammerhead-free type.
5. The method of claim 4, wherein determining the gate end structure of the transistor device as a function of a channel type of the transistor device, a gate thickness of the transistor device, and a gate length of the transistor device comprises:
determining a preset threshold value of the gate length of the transistor device according to the channel type of the transistor device and the gate thickness of the transistor device;
judging whether the gate length of the transistor device is lower than the preset threshold value or not; if yes, the grid end structure of the transistor device is in a hammerhead type; otherwise, the gate end structure of the transistor device is hammerless.
6. The method of claim 1, wherein the design parameters of the transistor device comprise: the length of the active region, the interval between two adjacent contact structures and the maximum length of the contact structures; a minimum length between the contact structure and an edge of the active region;
the determining a contact resistance of the transistor device according to design parameters of the transistor device includes:
determining the number of the contact structures according to design parameters of the transistor device;
determining the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures;
and acquiring the standard unit resistance of the contact structures, and determining the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures.
7. The method of claim 6, wherein determining the number of contact structures according to design parameters of the transistor device comprises:
determining the number of the contact structures based on a first formula according to design parameters of the transistor device; wherein the first formula comprises:
N＝ceiling[(W-2×S+P)/Lmax]；
wherein N is the number of the contact structures and is a positive integer; ceiling [ ] is a calculation rule of rounding up; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the interval between two adjacent contact structures; lmax is the maximum length of the contact structure.
8. The method of claim 6, wherein determining the length of the contact structure according to the design parameters of the transistor device and the number of contact structures comprises:
determining the length of the contact structure based on a second formula according to the design parameters of the transistor device and the number of the contact structures; wherein the second formula comprises:
Lg＝(W-2×S+P)/N-P；
wherein Lg is the length of the contact structure; n is the number of the contact structures and is a positive integer; w is the length of the active region; s is the minimum length between the contact structure and the edge of the active region; p is the interval between two adjacent contact structures.
9. The method of claim 6, wherein determining the contact resistance of the transistor device based on the number of contact structures, the length of the contact structures, and the standard unit resistance of the contact structures comprises:
determining the contact resistance of the transistor device based on a third formula according to the number of the contact structures, the length of the contact structures and the standard unit resistance of the contact structures; wherein the third formula comprises:
Rlicon＝Rx×Lg/N；
wherein Rsilicon is the contact resistance of the transistor device; rx is the standard unit resistance of the contact structure; lg is the length of the contact structure; n is the number of the contact structures and is a positive integer.
10. The method of claim 6, wherein obtaining the standard specific resistance of the contact structure comprises:
determining a standard resistance and a standard length of the contact structure according to the type of the transistor device;
and obtaining the standard unit resistance of the contact structure according to the standard resistance and the standard length of the contact structure.
11. A contact resistance acquisition device is applied to model simulation of a transistor device, wherein the transistor device comprises an active region, a grid electrode and a plurality of contact structures, the grid electrode is positioned on the active region, and the contact structures are electrically connected with a source electrode or a drain electrode; it is characterized by comprising:
the first determining unit is used for determining the type of the transistor device and determining the design parameters of the transistor device according to the type of the transistor device;
a second determining unit, configured to determine a contact resistance of the transistor device according to a design parameter of the transistor device; wherein a contact resistance of the transistor device is an equivalent resistance of the plurality of contact structures.
12. The apparatus of claim 11, wherein the classification of the type of transistor device is determined by at least one of: channel type, gate thickness, gate end structure.
13. The apparatus of claim 11, wherein the design parameters of the transistor device comprise: the length of the active region, the interval between two adjacent contact structures and the maximum length of the contact structures; a minimum length between the contact structure and an edge of the active region;
the second determining unit is specifically configured to determine the number of the contact structures according to design parameters of the transistor device;
the second determining unit is specifically configured to determine the length of the contact structure according to the design parameters of the transistor device and the number of the contact structures;
the second determining unit is specifically further configured to obtain a standard unit resistance of the contact structure corresponding to the type of the transistor device, and determine the contact resistance of the transistor device according to the number of the contact structures, the length of the contact structure, and the standard unit resistance of the contact structure.
14. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored by the memory to implement the method of any of claims 1-10.
15. A computer-readable storage medium having computer-executable instructions stored thereon, which when executed by a processor, perform the method of any one of claims 1-10.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210989348.2A CN115358170A (en) | 2022-08-17 | 2022-08-17 | Contact resistance acquisition method and device, electronic equipment and storage medium |
| PCT/CN2022/123954 WO2024036721A1 (en) | 2022-08-17 | 2022-10-09 | Contact resistance acquisition method and apparatus, electronic device, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210989348.2A CN115358170A (en) | 2022-08-17 | 2022-08-17 | Contact resistance acquisition method and device, electronic equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115358170A true CN115358170A (en) | 2022-11-18 |
Family
ID=84001784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210989348.2A Pending CN115358170A (en) | 2022-08-17 | 2022-08-17 | Contact resistance acquisition method and device, electronic equipment and storage medium |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115358170A (en) |
| WO (1) | WO2024036721A1 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102693959B (en) * | 2011-03-25 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Grid resistor test structure for MOS transistor |
| US8458642B2 (en) * | 2011-03-28 | 2013-06-04 | International Business Machines Corporation | Method, a program storage device and a computer system for modeling the total contact resistance of a semiconductor device having a multi-finger gate structure |
| CN104156526A (en) * | 2014-08-11 | 2014-11-19 | 中国科学院微电子研究所 | Method for obtaining coplane-type thin film transistor contact resistance |
| US10627442B2 (en) * | 2017-12-07 | 2020-04-21 | Nanya Technology Corporation | Method for estimating resistances of a source contact and a drain contact of a MOS transistor |
| CN109637944B (en) * | 2018-10-31 | 2020-10-30 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor structure and method for measuring channel resistance and contact resistance |
| US10846451B1 (en) * | 2019-07-11 | 2020-11-24 | Cobham Colorado Springs Inc. | Methods of modelling irregular shaped transistor devices in circuit simulation |
| CN114384322B (en) * | 2020-10-16 | 2023-07-18 | 长鑫存储技术有限公司 | Method for measuring contact resistance of transistor test device and computer readable medium |
-
2022
- 2022-08-17 CN CN202210989348.2A patent/CN115358170A/en active Pending
- 2022-10-09 WO PCT/CN2022/123954 patent/WO2024036721A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024036721A1 (en) | 2024-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080021689A1 (en) | Method for designing semiconductor integrated circuit and method of circuit simulation | |
| US7089513B2 (en) | Integrated circuit design for signal integrity, avoiding well proximity effects | |
| US8356271B2 (en) | Layout testing method and wafer manufacturing method | |
| US20070089077A1 (en) | System and method for integrated circuit timing analysis | |
| US8275584B2 (en) | Unified model for process variations in integrated circuits | |
| US10747916B2 (en) | Parameter generation for modeling of process-induced semiconductor device variation | |
| KR20090077692A (en) | Semiconductor-device manufacturing method, semiconductor-device manufacturing program and semiconductor-device manufacturing system | |
| US20120123745A1 (en) | Adaptive Content-aware Aging Simulations | |
| JP2009526276A (en) | Method and apparatus for inserting a filling mold into a design layout | |
| US10467374B2 (en) | System and method for calculating cell edge leakage | |
| CN113392617B (en) | Semiconductor integrated circuit design method and device | |
| CN106599336B (en) | Semiconductor process simulation device and method and computing device | |
| US8448110B2 (en) | Method to reduce delay variation by sensitivity cancellation | |
| CN115358170A (en) | Contact resistance acquisition method and device, electronic equipment and storage medium | |
| CN111104769B (en) | MOSFET BISM4 model parameter extraction method | |
| US8275596B2 (en) | Method for robust statistical semiconductor device modeling | |
| US6766274B2 (en) | Determining the failure rate of an integrated circuit | |
| CN114384322A (en) | Method for measuring contact resistance of transistor test device and computer readable medium | |
| JP3735560B2 (en) | Method for evaluating semiconductor integrated circuit | |
| US20020007478A1 (en) | Routing definition to optimize layout design of standard cells | |
| CN114417581A (en) | Simulation method and simulation system based on SPICE model | |
| CN114676570A (en) | Simulation model determining method, chip classifying method and related equipment | |
| CN113449422A (en) | Method, device, equipment and storage medium for processing test data | |
| US20230010293A1 (en) | Semiconductor integrated circuit design method and apparatus | |
| US20140068535A1 (en) | System and method for configuring a transistor device using rx tuck |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |