CN114417581A - Simulation method and simulation system based on SPICE model - Google Patents

Simulation method and simulation system based on SPICE model Download PDF

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CN114417581A
CN114417581A CN202111676439.2A CN202111676439A CN114417581A CN 114417581 A CN114417581 A CN 114417581A CN 202111676439 A CN202111676439 A CN 202111676439A CN 114417581 A CN114417581 A CN 114417581A
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simulation
electrical
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lde
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曾健忠
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Shenzhen Sirius Semiconductor Co ltd
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Abstract

The invention belongs to the technical field of semiconductor simulation, and mainly provides a simulation method and a simulation system based on an SPICE model, which are used for establishing a device framework of a simulation device and simulating an electrical curve of the simulation device; defining parameters of a wafer acceptance test of the simulation device, and carrying out an electrical test on the simulation device according to the electrical curve to obtain first electrical parameters; obtaining electrical simulation data of the wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test; performing neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture; and writing the obtained neural network-like weighting parameters and the neural network-like framework into the model card, so that the simulation of the device is realized by the model card based on the SPICE model, and the problem of large test workload caused by the fact that the current LDE simulation requires a user to write a function into the model card can be avoided.

Description

Simulation method and simulation system based on SPICE model
Technical Field
The invention belongs to the technical field of semiconductor simulation, and particularly relates to a simulation method and a simulation system based on an SPICE model.
Background
Layout Dependent Effect (LDE) is an important phenomenon affecting devices, since the stress and electric field around the device directly affect the device performance. Model card (model card) of Simulation Circuit Simulator (SPICE) must describe LDE phenomenon precisely to be accurate S2S (SPICE to Silicon).
In the existing LDE simulation of the model card of SPICE, various large LDE effects which affect the electrical effect are usually drawn and then put into SPICE test patterns, however, the operation can cause the area of the LDE test to account for over 50% of the test area related to SPICE, which leads to over 50% of the test resources, not only increases the test workload, but also seriously squeezes the test time of other projects.
Disclosure of Invention
The invention aims to provide a simulation method and a simulation system based on an SPICE model, and aims to solve the problem that the existing LDE test occupies too much test resources.
The embodiment of the application also provides a simulation method based on the SPICE model, and the simulation method comprises the following steps:
establishing a device framework of the simulation device, and simulating an electrical curve of the simulation device;
defining parameters of a wafer acceptance test of the simulation device, and carrying out an electrical test on the simulation device according to the electrical curve to obtain first electrical parameters;
obtaining electrical simulation data of a wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test;
performing neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture;
and writing the obtained neural network-like weighting parameters and the neural network-like framework into a model card.
In one embodiment, the performing neural network training based on the LDE input parameters and the electrical variation parameters includes:
taking LDE input parameters as input data of the neural network training;
and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
In one embodiment, the LDE input parameters include source drain region size parameters, and the first electrical parameters include threshold voltage, on-state current, and leakage current;
the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
In one embodiment, the defining the parameter of the wafer acceptance test of the simulation device and electrically testing the simulation device according to the electrical characteristic to obtain the first electrical parameter includes:
and adopting TCAD simulation software to obtain an IV curve of the device based on the defined wafer acceptance test simulation, and carrying out electrical test on the simulation device to obtain a first electrical parameter.
In one embodiment, the electrical curve includes an IV curve and a CV curve.
In one embodiment, the device architecture for creating an emulated device includes:
and establishing a device architecture of the simulation device by adopting TCAD simulation software, and simulating an IV curve and a CV curve of the simulation device.
A second aspect of the embodiments of the present application further provides a simulation system based on an SPICE model, where the simulation system includes:
the model establishing module is used for establishing a device framework of the simulation device and simulating an electrical curve of the simulation device;
the test simulation module is used for defining parameters of the wafer acceptance test of the simulation device and electrically testing the simulation device according to the electrical curve to obtain first electrical parameters;
the test comparison module is used for obtaining electrical simulation data of the wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test;
the training module is used for carrying out neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture;
and the model import module is used for writing the obtained neural network-like weighting parameters and the neural network-like framework into the model card.
In one embodiment, the training module is specifically configured to:
taking LDE input parameters as input data of the neural network training;
and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
In one embodiment, the LDE input parameters include source drain region size parameters, and the first electrical parameters include threshold voltage, on-state current, and leakage current;
the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
In one embodiment, the test simulation module is specifically configured to:
and adopting TCAD simulation software to obtain an IV curve of the device based on the defined wafer acceptance test simulation, and carrying out electrical test on the simulation device to obtain a first electrical parameter.
The embodiment of the application provides a simulation method and a simulation system based on an SPICE model, a device framework of a simulation device is established, and an electrical curve of the simulation device is simulated; defining parameters of a wafer acceptance test of the simulation device, and carrying out an electrical test on the simulation device according to the electrical curve to obtain first electrical parameters; obtaining electrical simulation data of the wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test; performing neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture; and writing the obtained neural network-like weighting parameters and the neural network-like framework into the model card, so that the simulation of the device is realized by the model card based on the SPICE model, and the problem of large test workload caused by the fact that the current LDE simulation requires a user to write a function into the model card can be avoided.
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Fig. 1 is a schematic flow chart of a simulation method according to an embodiment of the present application;
2a, 2b, and 2c are schematic diagrams of a plurality of structures of a simulation device according to an embodiment of the present application;
FIG. 3 is a graph illustrating VT and Ion from an IV curve according to an embodiment of the present application;
fig. 4a and 4b are schematic diagrams illustrating the result of neural network training provided by an embodiment of the present application;
fig. 5 is a schematic diagram of a simulation system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the present application further provides a simulation method based on the SPICE model, and as shown in fig. 1, the simulation method includes steps S10 to S60.
In step S10, a device architecture of the simulation device is established and an electrical curve thereof is simulated.
In the present embodiment, by establishing a device architecture to be simulated and simulating the electrical curve thereof, a Wafer Acceptance Test (WAT) result is obtained by a subsequent WAT definition.
In one embodiment, the electrical curve includes at least an IV curve and a CV curve.
In this embodiment, the IV curve refers to a voltage-current characteristic curve of the device, and the CV curve represents a capacitance-voltage relationship curve of the device.
In one embodiment, in step S10, a device architecture of the simulation device may be created by using TCAD simulation software, and an IV curve and a CV curve of the simulation device may be simulated.
The TCAD is Technology Computer aid Design, which refers to semiconductor process simulation and device simulation tools, and may be Athena and Atlas software available from Silvaco, or TSupperm and Medici available from Synopsys, Inc.
In step S20, parameters of a wafer acceptance test of the simulation device are defined, and the simulation device is electrically tested according to the electrical curve to obtain a first electrical parameter.
In this embodiment, the parameters are defined by a Wafer Acceptance Test (WAT), and the simulated device is electrically tested according to the electrical curve to obtain a first electrical parameter as a WAT result.
In one embodiment, the parameters defined by the Wafer Acceptance Test (WAT) may include an SA value of the LOD, and the electrical curve of the simulated device may be changed by adjusting the SA value, and at this time, the WAT result obtained by the electrical test may also completely correspond to the SA value.
For example, fig. 2a, 2b, and 2c show a 4 Fin MOS device, and referring to fig. 2a, the MOS device has a plurality of fins 110, which can implement a plurality of control channels for MOS transistors, and a source 112 and a drain 113 are respectively disposed between adjacent polysilicon gates 111.
Fig. 2a, fig. 2b and fig. 2c are schematic structural diagrams of the case where SA ═ 0.1um, SA ═ 0.6um and SA ═ 0.8um, respectively, which define their Diffusion Lengths (LODs), and the WAT results are obtained by performing an electrical test on the simulation device by defining their parameters to obtain first electrical parameters.
LOD is an abbreviation of Length of Diffusion, and is a device electrical characteristic variation effect caused by a variation in the STI (Shallow Trench Isolation) distance between a gate and a Shallow Trench in the direction of a channel extension line of a MOS transistor, and the LOD stress effect mainly affects the saturated source-drain current (Idsat) and the threshold voltage (Vth) of the device. This effect can be described by the parameters SA and SB, where SA is the distance from the gate of the MOS transistor to one edge of the active region, and SB is the distance from the gate of the MOS transistor to the other edge of the active region, as shown in fig. 2 a.
The threshold voltage of a short channel MOSFET increases from a linear region to a saturation region due to a drain-induced barrier lowering (DIBL) effect caused by the drainThe step-down will more seriously refer to this effect as the drain causing the barrier to drop. Referring to FIG. 3, the IV curve of the device is obtained by TCAD simulation, and the horizontal axis is the grid-source voltage VGSThe vertical axis is the source-drain current IDSAccording to the SA value of LOD defined by WAT, each device with SA value has an IV curve corresponding to the SA value, and the drain-source voltage V is caused by DIBL effect introduced by drain terminalDSThe threshold voltage of the device is greatly influenced, for example, the drain-source voltage VDSCurve diagram at VDD, and drain-source voltage VDSCurve diagram at 0.05V, based on the IV curve, it can be seen that V is obtainedDSWhen the difference is different, the threshold voltage vt (sat) or vt (iin) obtained by the electrical test is different from the on-state current Ion.
In step S30, electrical simulation data of the acceptance test of the wafer is obtained through simulation, and the electrical simulation data is compared with the first electrical parameter to obtain an LDE input parameter and an electrical variation parameter of the acceptance test of the wafer.
In this embodiment, the electrical simulation data (e.g., WAT data) of the wafer acceptance test is obtained by simulation, and the electrical simulation data is compared with the first electrical parameter to obtain the LDE input parameter and the electrical variation parameter of the wafer acceptance test, for example, when SA as the LDE input parameter is varied, the corresponding WAT test parameter is also varied correspondingly.
In one embodiment, the IV curve of the device may be obtained by performing a TCAD simulation software based on a defined wafer acceptance test simulation, and performing an electrical test on the simulated device to obtain the first electrical parameter.
In step S40, a neural network training is performed based on the LDE input parameters and the electrical variation parameters to obtain a neural network weighting parameter and a neural network architecture.
In one embodiment, specifically, the LDE input parameters may be used as input data for the neural network-like training; and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
In specific application, each data information collected on the chip is used as input and output to carry out neural network training to obtain the neural network weighting parameters and the neural network architecture. The electrical variation parameter of the wafer acceptance test may be an LDE input parameter (e.g., SA parameter) and a variation of the electrical property of the output data device WAT, for example, if the input SA is 0.1um, the corresponding variation of the WAT electrical parameter is used as the training output data, the variation of the WAT electrical parameter includes a threshold voltage variation (Δ VT), an on-current variation (Ion), a leakage current variation, and the like, each input SA corresponds to a set of variation of the WAT electrical parameter, and a plurality of SA values correspond to a plurality of sets of variation of the WAT electrical parameter.
In this embodiment, a function suitable for fitting the LDE phenomenon can be found by introducing a strong computational power of a Neural Network (NN), and finally, by writing a training result of the NN into the model card, a time for a user to think about the function and try and error can be replaced, thereby saving a large amount of labor cost.
In one embodiment, a large number of LDE input parameters (for example, parameters SA) are used as input data for training the neural network, electrical variation parameters of a wafer acceptance test are used as output data for training the neural network, and fitting calculation is performed through a large number of input data and output data, so that neural network weighting parameters and a neural network architecture are obtained, a fitting function is formed, and a large number of manpower and material resources are prevented from searching for a proper LDE function.
In a specific application, the neural network training has a three-layer structure: the device comprises an input layer, a hidden layer and an output layer, wherein variables are input to the neural network at the input layer, and are calculated and output at the hidden layer and the output layer. At the hidden layer of a neural network, there are "neurons" that rely on activation functions to perform operations.
In a specific application embodiment, taking a back propagation algorithm as an example, in the back propagation algorithm, an error function is obtained by forward calculation, and a backward derivative gradient is decreased. Assuming that K groups of LDE input parameters and electrical property change parameters are adopted as training data, the self-defined error function minimization is realized through continuous training, the error function can be a sum of squares function, specifically, some self variables of the neural network are initialized, then the initialized variables are substituted into the neural network, and all training data are added to obtain an initial error function value, then the self variables of the neural network are continuously updated, so that the error function of the neural network is reduced under the updated self variables, for example, the gradient is continuously reduced through a Newton method or a least square method until the error function is reduced to a preset range, and the neural network-like training is completed.
In step S50, the obtained neural network-like weighting parameters and the neural network-like framework are written into the model card.
Layout Dependent Effect (LDE) is an important phenomenon affecting devices, because the device performance is directly affected by the stress and electric field around the device, and the LDE phenomenon must be accurately described in model card (model card) of Simulation Circuit Simulator (SPICE) to achieve accurate S2S (SPICE to Silicon).
In the traditional simulation method, a user is usually required to write a corresponding LDE function into a model card of SPICE for verification, a large amount of manpower and material resources are consumed for searching a proper LDE function, in the application, neural network-like training is carried out through LDE input parameters and electrical property change parameters, obtained neural network-like weighting parameters and the neural network-like framework are written into the model card and used as the LDE function to carry out simulation processing on a simulation device, and a large amount of test resources and labor cost can be saved.
In one embodiment, the LDE input parameters include source drain region size parameters, and the first electrical parameters include threshold voltage, on-state current, and leakage current;
the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
Referring to FIG. 4, the electrical change Δ Vt due to the Y-axis, LDEIin(VT variation/Ion variation), SA (input function of LOD function) on the X-axis, Si (median) representing the collected data, and Ori solid lineThe final is the result of the conventional LDE process, and the user usually performs fitting optimization through a polynomial function. The dotted line impro is a neural network training result, and it can be seen in combination with fig. 4 that the neural network training result is superior to the conventional process, and the execution method includes performing input and output training on each piece of data collected on the chip to obtain a neural network weighting parameter and a neural network architecture, and writing the neural network weighting parameter and the neural network architecture into a model card to obtain a fitted LDE function.
An embodiment of the present application further provides a simulation system based on the SPICE model, as shown in fig. 5, the simulation system includes: the system comprises a model building module 610, a test simulation module 620, a test comparison module 630, a training module 640 and a model importing module 650.
The model building module 610 is used for building a device architecture of the simulation device and simulating an electrical curve thereof.
In the present embodiment, the model building module 610 builds a device structure of the device to be simulated, and simulates an electrical curve thereof, and a Wafer Acceptance Test (WAT) result is obtained through a subsequent WAT definition.
In the present embodiment, the electrical curve at least includes an IV curve and a CV curve. The IV curve refers to the current-voltage characteristic curve of the device, and the CV curve represents the capacitance-voltage relation curve of the device.
The test simulation module 620 is configured to define parameters of a wafer acceptance test of the simulation device, and perform an electrical test on the simulation device according to the electrical curve to obtain a first electrical parameter.
In this embodiment, a Wafer Acceptance Test (WAT) parameter is defined by the test simulation module 620, and the simulated device is electrically tested according to the electrical curve to obtain a first electrical parameter as a WAT result.
The test comparison module 630 is configured to obtain electrical simulation data of the wafer acceptance test through simulation, and compare the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical variation parameter of the wafer acceptance test.
In this embodiment, the electrical simulation data (e.g., WAT data) of the wafer acceptance test is obtained by the simulation of the test comparison module 630, and the electrical simulation data is compared with the first electrical parameter to obtain the LDE input parameter and the electrical variation parameter of the wafer acceptance test. The electrical variation parameter may be a variation of LDE input parameters (e.g., SA) and output data device WAT electrical characteristics.
The training module 640 is configured to perform a neural network training based on the LDE input parameter and the electrical property variation parameter, so as to obtain a neural network weighting parameter and a neural network architecture.
The training module 640 takes the LDE input parameters as input data for the neural network training; and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
In specific application, each data information collected on the chip is used as input and output to carry out neural network training to obtain the neural network weighting parameters and the neural network architecture.
In this embodiment, a function suitable for fitting the LDE phenomenon can be found by introducing a strong computational power of a Neural Network (NN), and finally, by writing a training result of the NN into the model card, a time for a user to think about the function and try and error can be replaced, thereby saving a large amount of labor cost.
The model import module 650 is configured to write the obtained neural network-like weighting parameters and neural network-like framework into the model card.
In the traditional simulation method, a user is usually required to write a corresponding LDE function into a model card of SPICE for verification, a large amount of manpower and material resources are consumed for searching a proper LDE function, in the application, neural network-like training is carried out through LDE input parameters and electrical variation parameters, the obtained neural network-like weighting parameters and the obtained neural network-like framework are written into the model card through a model import module 650 and serve as the LDE function to carry out simulation processing on a simulation device, and a large amount of test resources and labor cost can be saved.
In one embodiment, the training module 640 is specifically configured to: taking LDE input parameters as input data of the neural network training; and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
In specific application, each data information collected on the chip is used as input and output to carry out neural network training to obtain the neural network weighting parameters and the neural network architecture. The method has the advantages that a proper function can be found out by introducing strong calculation power of Neural Network (NN) to fit the LDE phenomenon, and finally, the training result of the NN is written into the model card, so that the time for a user to think about the function and try for mistakes can be replaced, and a large amount of labor cost is saved.
In one embodiment, the LDE input parameters include source drain region size parameters, and the first electrical parameters include threshold voltage, on-state current, and leakage current; the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
In one embodiment, the test simulation module 620 is specifically configured to: and adopting TCAD simulation software to obtain an IV curve of the device based on the defined wafer acceptance test simulation, and carrying out electrical test on the simulation device to obtain a first electrical parameter.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules, so as to perform all or part of the functions described above. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, a module or a unit may be divided into only one logical function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the embodiments described above can be realized by a computer program, which can be stored in a computer readable storage medium and can realize the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A simulation method based on SPICE model is characterized in that the simulation method comprises the following steps:
establishing a device framework of the simulation device, and simulating an electrical curve of the simulation device;
defining parameters of a wafer acceptance test of the simulation device, and carrying out an electrical test on the simulation device according to the electrical curve to obtain first electrical parameters;
obtaining electrical simulation data of a wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test;
performing neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture;
and writing the obtained neural network-like weighting parameters and the neural network-like framework into a model card.
2. The simulation method of claim 1, wherein the performing neural network-like training based on the LDE input parameters and the electrical variation parameters comprises:
taking LDE input parameters as input data of the neural network training;
and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
3. The simulation method of claim 2, wherein the LDE input parameters comprise source drain region dimension parameters, and the first electrical parameters comprise threshold voltage, on-state current, and leakage current;
the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
4. The simulation method of claim 1, wherein the defining parameters for wafer acceptance testing of the simulated device and electrically testing the simulated device according to the electrical characteristic to obtain first electrical parameters comprises:
and adopting TCAD simulation software to obtain an IV curve of the device based on the defined wafer acceptance test simulation, and carrying out electrical test on the simulation device to obtain a first electrical parameter.
5. The simulation method of claim 1, wherein the electrical curve comprises an IV curve and a CV curve.
6. The simulation method of claim 5, wherein the building a device architecture of a simulated device comprises:
and establishing a device architecture of the simulation device by adopting TCAD simulation software, and simulating an IV curve and a CV curve of the simulation device.
7. A simulation system based on SPICE model, the simulation system comprising:
the model establishing module is used for establishing a device framework of the simulation device and simulating an electrical curve of the simulation device;
the test simulation module is used for defining parameters of the wafer acceptance test of the simulation device and electrically testing the simulation device according to the electrical curve to obtain first electrical parameters;
the test comparison module is used for obtaining electrical simulation data of the wafer acceptance test through simulation, and comparing the electrical simulation data with the first electrical parameter to obtain an LDE input parameter and an electrical change parameter of the wafer acceptance test;
the training module is used for carrying out neural network training based on the LDE input parameters and the electrical property change parameters to obtain neural network weighting parameters and a neural network architecture;
and the model import module is used for writing the obtained neural network-like weighting parameters and the neural network-like framework into the model card.
8. The simulation system of claim 7, wherein the training module is specifically configured to:
taking LDE input parameters as input data of the neural network training;
and taking the electrical variation parameters of the wafer acceptance test as the output data of the neural network training.
9. The simulation system of claim 7, wherein the LDE input parameters comprise source drain region dimension parameters, and the first electrical parameters comprise threshold voltage, on-state current, and leakage current;
the wafer acceptance test has the electrical change parameters of delta VT/delta Ion, wherein delta VT is the threshold voltage variation, and delta Ion is the on-current variation.
10. The simulation method of claim 1, wherein the test simulation module is specifically configured to:
and adopting TCAD simulation software to obtain an IV curve of the device based on the defined wafer acceptance test simulation, and carrying out electrical test on the simulation device to obtain a first electrical parameter.
CN202111676439.2A 2021-12-31 2021-12-31 Simulation method and simulation system based on SPICE model Pending CN114417581A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114970431A (en) * 2022-06-29 2022-08-30 上海集成电路装备材料产业创新中心有限公司 Method and device for training MOS (Metal oxide semiconductor) tube parameter estimation model
CN114970431B (en) * 2022-06-29 2024-04-02 上海集成电路装备材料产业创新中心有限公司 Training method and device for MOS tube parameter estimation model

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