CN112861297B - MOS transistor feature extraction method, device, medium and electronic equipment - Google Patents
MOS transistor feature extraction method, device, medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the invention provides a method, a device, a medium and electronic equipment for extracting MOS transistor characteristics, and relates to the technical field of semiconductor device testing, wherein a first doped region of an MOS transistor is electrically connected with a first lead-out bonding pad through a wire, and the method for extracting characteristics comprises the following steps: obtaining the wiring resistance of the lead; acquiring a diffusion resistance of a first doped region of the MOS transistor; obtaining a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance; and adding the equivalent resistance coefficient of the first doping region into a pre-established MOS transistor model to perform simulation calculation. According to the technical scheme, the equivalent resistance coefficient of the first doping area is obtained according to the wiring resistance and the diffusion resistance, and is added into the MOS transistor model to simulate the parasitic resistance of the MOS transistor, so that a more accurate simulation result can be obtained.
Description
Technical Field
The invention relates to the technical field of semiconductor device testing, in particular to a method and a device for extracting MOS transistor characteristics, a computer readable storage medium and electronic equipment.
Background
With the rapid development of Semiconductor device manufacturing technology, a large number of MOS transistors (Metal Oxide Semiconductor Field Effect transistors) are used in Semiconductor integrated circuits.
The design of a semiconductor integrated circuit requires accurate acquisition of the current-voltage characteristic of each MOS transistor. And the user calculates the parameters of the performance, the power consumption and the like of the whole circuit according to the current-voltage characteristics of the single MOS transistor. Therefore, it is very important to accurately reflect the voltage-current characteristics of the MOS transistor in the simulation model building process.
In a semiconductor process, testkey refers to a test unit that is disposed at a wafer-fixing location in a wafer process for monitoring the process or for extracting characteristics of components.
When a simulation model is established, the design tesktkey needs to use a large number of sizes, and in order to save area, the MOS transistor needs to be connected in common gate and common source. In the circuit shown in fig. 1, the sources S1 to S4 of the four MOS transistors, i.e., the first MOS transistor MOS1, the second MOS transistor MOS2, the third MOS transistor MOS3 and the fourth MOS transistor MOS4, are all connected to the pad7, and the gates G1 to G4 are all connected to the pad 6. It can be seen that the source terminal of the MOS transistor MOS1 is longer, resulting in a larger parasitic resistance at the source terminal of the MOS transistor MOS1, and the parasitic resistance at the source terminal of each of the MOS transistors MOS1, MOS2, MOS3, and MOS4 are different. The BSIM (Berkeley Short-channel IGFET Model) in the current simulation design cannot consider these parasitic effects one by one.
How to obtain more accurate voltage-current characteristics of the MOS transistor on the basis of considering these parasitic effects is a technical problem that needs to be solved at present.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present invention and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
Embodiments of the present invention provide a method and an apparatus for extracting MOS transistor characteristics, a computer-readable storage medium, and an electronic device, so as to obtain accurate MOS transistor voltage-current characteristics at least to a certain extent.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.
According to a first aspect of the embodiments of the present invention, there is provided a method for extracting a feature of a MOS transistor, in which a first doped region of the MOS transistor is electrically connected to a first lead-out pad through a wire, the method including: obtaining the wiring resistance of the lead; acquiring a diffusion resistance of a first doped region of the MOS transistor; obtaining a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance; and adding the equivalent resistance coefficient of the first doping region into a pre-established MOS transistor model to perform simulation calculation.
In some embodiments, obtaining the wiring resistance of the wire comprises: acquiring the length and the width of the lead; acquiring the square resistance of the lead; and obtaining the wiring resistance according to the length of the lead, the width of the lead and the square resistance of the lead.
In some embodiments, obtaining the diffusion resistance of the first doped region of the MOS transistor comprises: acquiring the distance from the center of a first doped region of the MOS transistor to the edge of a grid electrode of the MOS transistor; acquiring the width of the MOS transistor and the square resistance of the first doped region; and acquiring the diffusion resistance according to the distance, the width of the MOS transistor and the square resistance of the first doped region.
In some embodiments, the first doped region is a source electrode, the MOS transistors include a first MOS transistor and a second MOS transistor, and the source electrode of the first MOS transistor and the source electrode of the second MOS transistor are both electrically connected to the first lead-out pad; and the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor are electrically connected with the second lead-out bonding pad.
In some embodiments, the second doped region of the MOS transistor is a drain, and after adding the equivalent resistivity of the first doped region to the pre-established MOS transistor model, the method further comprises: applying a gate voltage, a source voltage, a drain voltage to the MOS transistor; obtaining the drain current of the MOS transistor; and acquiring the voltage-current characteristics of the MOS transistor according to the drain current and the transistor model.
In some embodiments, the first doped region equivalent resistivity is a multiple of a sum of the wiring resistance and the diffusion resistance and the first doped region sheet resistance.
According to a second aspect of the embodiments of the present invention, there is provided a MOS transistor simulation apparatus, in which a first doped region of a MOS transistor is electrically connected to a first lead-out pad through a wire, including: a wiring resistance acquisition unit for acquiring a wiring resistance of the wire; the diffusion resistance acquisition unit is used for acquiring the diffusion resistance of the first doped region of the MOS transistor; a first doping region equivalent resistance coefficient obtaining unit, configured to obtain a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance, where the first doping region equivalent resistance coefficient is a multiple of a sum of the wiring resistance and the diffusion resistance and a square resistance of the first doping region; and the modeling unit is used for adding the equivalent resistance coefficient of the first doping area into a pre-established MOS transistor model so as to perform simulation calculation.
In some embodiments, the wiring resistance obtaining unit is further configured to: a first obtaining subunit, configured to obtain a length and a width of the wire; the second acquisition subunit is used for acquiring the square resistance of the lead; a wiring resistance obtaining subunit configured to obtain the wiring resistance according to the length of the wire, the width of the wire, and the sheet resistance of the wire; the diffusion resistance obtaining unit is further configured to: the third acquiring subunit is used for acquiring the distance from the center of the first doped region of the MOS transistor to the edge of the grid of the MOS transistor; the fourth obtaining subunit is used for obtaining the width of the MOS transistor and the square resistance of the first doping area; and the diffusion resistance obtaining subunit is used for obtaining the diffusion resistance according to the distance, the width of the MOS transistor and the square resistance of the first doping area.
In some embodiments, the first doped region is a source electrode, the MOS transistors include a first MOS transistor and a second MOS transistor, and the source electrode of the first MOS transistor and the source electrode of the second MOS transistor are both electrically connected to the first lead-out pad; and the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor are electrically connected with the second lead-out bonding pad.
In some embodiments, the second doped region of the MOS transistor is a drain, and the apparatus further includes a simulation unit configured to: applying a gate voltage, a source voltage, a drain voltage to the MOS transistor; obtaining the drain current of the MOS transistor; and acquiring the voltage-current characteristics of the MOS transistor according to the drain current and the transistor model.
In some embodiments, the first doped region equivalent resistivity is a multiple of a sum of the wiring resistance and the diffusion resistance and the first doped region sheet resistance.
According to a third aspect of embodiments of the present invention, there is provided a computer-readable storage medium on which a computer program is stored, the program, when executed by a processor, implementing the MOS transistor feature extraction method according to the first aspect of embodiments of the present invention.
According to a fourth aspect of embodiments of the present invention, there is provided an electronic apparatus, including: one or more processors; a storage device, configured to store one or more programs, which when executed by the one or more processors, cause the one or more processors to implement the MOS transistor feature extraction method according to the first aspect of the embodiment of the present invention.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
in the technical solutions provided in some embodiments of the present invention, a first doping region equivalent resistance coefficient is obtained according to a wiring resistance and a diffusion resistance, and the first doping region equivalent resistance coefficient is added to an MOS transistor model to simulate a parasitic resistance of an MOS transistor, that is, an influence caused by a parasitic resistance voltage division effect is added to a simulation model in a simulation process, so as to obtain a simulation curve closer to an actually measured MOS transistor gate voltage-drain current test curve.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram schematically showing a connection circuit of a MOS transistor in the related art;
fig. 2 schematically shows a flow chart of a MOS transistor feature extraction method according to the invention;
fig. 3 schematically shows a schematic structural view of a MOS transistor manufacturing layout according to the invention.
FIG. 4 schematically illustrates a block diagram of a MOS transistor emulation device in accordance with the present invention;
FIG. 5 schematically illustrates a block diagram of a computer system suitable for use with an electronic device that implements an embodiment of the invention.
Detailed Description
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. The exemplary embodiments, however, may be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the module of the icon is turned upside down, the component described as "upper" will become the component "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/parts; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
In the related art, in order to save area when designing the tesktkey, it is often necessary to connect MOS transistors in common gate and/or common source. The wire between the source end of the MOS transistor and the first lead-out bonding pad has certain parasitic resistance, and the lengths of the wires between the source ends of different MOS transistors and the first lead-out bonding pad are different, so that the parasitic resistance of the source end of each MOS transistor is different. The difference in parasitic resistance causes the voltage actually applied to the source terminal to be inconsistent with the voltage applied to the pad. The existing feature extraction method does not consider the influence of the parasitic resistance in the simulation process, so that the current-voltage characteristic of the obtained transistor has deviation from the actual current-voltage characteristic.
In order to solve the above problems, embodiments of the present invention provide a method and an apparatus for extracting MOS transistor characteristics, a computer-readable storage medium, and an electronic device, so as to add relevant parameters of a parasitic resistor into a simulation model to obtain more accurate voltage-current characteristics of an MOS transistor.
Fig. 2 schematically shows a MOS transistor feature extraction method according to an embodiment of the present invention. As shown in fig. 2, the MOS transistor feature extraction method provided by the exemplary embodiment of the present disclosure includes:
in step S201, the wiring resistance of the wire is acquired.
In step S202, the diffusion resistance of the first doped region of the MOS transistor is obtained.
Step S203, obtaining the equivalent resistivity of the first doped region of the MOS transistor according to the wiring resistance and the diffusion resistance.
Step S204, adding the equivalent resistance coefficient of the first doping area into a pre-established MOS transistor model to perform simulation calculation.
In the technical scheme of the embodiment of the invention, the influence of the diffusion resistance and the wiring resistance of the lead between the source end of different MOS transistors and the first lead-out pad on the parasitic resistance is considered, the sizes of the wiring resistance and the diffusion resistance of different MOS transistors are calculated, the equivalent resistance coefficient of the first doped region is obtained according to the wiring resistance and the diffusion resistance and is added into the simulation model, and therefore, the more accurate voltage-current characteristic of the MOS transistor can be obtained in the simulation process.
As shown in fig. 1, the MOS transistor has a gate, a first doped region and a second doped region, the first doped region may be a source, the second doped region may be a drain, the MOS transistor includes a first MOS transistor MOS1 and a second MOS transistor MOS2, a third MOS transistor MOS3 and a fourth MOS transistor MOS4, and the source of the first MOS transistor MOS1, the source of the second MOS transistor MOS2, the source of the third MOS transistor MOS3 and the source of the fourth MOS transistor MOS4 are electrically connected to the first lead-out pad 7. The gate of the first MOS transistor MOS1 and the gate of the second MOS transistor MOS2 are both electrically connected to the second lead pad 6.
In step S201, it is necessary to acquire the length and width of the wire, and acquire the sheet resistance of the wire, and acquire the wiring resistance according to the length, width, and sheet resistance of the wire.
Taking the MOS1 shown in fig. 1 as an example, the length of the wire from the source S1 of the MOS1 to the first lead pad7 is Lmetal, the wire width is Wmetal, and the sheet resistance of the wire is Rshmetal. At this time, the calculation formula of the wiring resistance Rrouting of the wire is: rrouting ═ Rshmetal @/Wmetal.
In step S202, it is necessary to obtain a distance from the center of the source of the MOS transistor to the edge of the gate of the MOS transistor, and obtain the width of the MOS transistor and the sheet resistance of the source, and obtain the diffusion resistance according to the distance, the width, and the sheet resistance of the source.
In the embodiment of the invention, as shown in fig. 3, a schematic diagram of a MOS transistor manufacturing layout structure is shown. As shown in fig. 3, the length and width of a MOS transistor are generally defined by the gate length L and the width W of the active region of the MOS transistor. It should be noted that the shape in fig. 3 is only schematic and used to illustrate the length and width of the transistor, and the actual shape of the gate may be different from that in fig. 3, which is not limited by the present invention and should be understood by those skilled in the art.
Taking MOS1 as an example as shown in fig. 1, MOS1 has a length L and a width W. The distance from the center of the source of MOS1 to the edge of the gate of MOS1 is DMCG and the square resistance of the source of MOS1 is Rshsource. At this time, the calculation formula of the diffusion resistance Rsource is: Rsource-Rsource DMCG/W.
According to the relation between the resistance and the resistivity, under the condition that the length L of the grid electrode is not changed, the resistance between the drain region and the source region of the MOS transistor is inversely proportional to the width W of the active region, namely the larger the width W of the active region is, the smaller the channel resistance is. Thus, the drain current is proportional to the ratio of the active region width W to the gate length L. When the same gate voltage is applied, the drain current increases as the active region width W increases when the channel length L is constant.
In step S203, first, according to the formula: rtotal, which is the sum of the wiring resistance and the diffusion resistance, is calculated. And calculating the equivalent resistivity NRS _ NEW (square number) of the first doping region according to a formula NRS _ NEW (Rshmetal/Lmeter/Wmetal + Rshmource DM CG/W)/Rshmouce. The first doped region equivalent resistivity NRS _ NEW is a multiple of the sum of the wiring resistance and the diffusion resistance and the first doped region sheet resistance.
Before step S204, a MOS transistor model also needs to be established. In step S204, the first doped region equivalent resistivity NRS _ NEW is added to the MOS transistor model.
After step S204, a gate voltage, a source voltage, a drain voltage may be applied to the MOS transistor; and acquiring the drain current of the MOS transistor, and acquiring the voltage-current characteristic of the MOS transistor according to the drain current and the transistor model.
Taking the MOS transistor shown in fig. 1 as an example, four different MOS transistors may obtain different first doping region equivalent resistance coefficients NRS _ NEW, and after the different first doping region equivalent resistance coefficients NRS _ NEW are added to corresponding MOS transistor models, a more accurate voltage-current characteristic curve of the MOS transistor may be obtained in simulation calculation.
When the MOS transistor model, namely the simulation model, is subjected to simulation calculation, the voltage applied to the MOS transistor by the test system is unchanged, and the simulated value of the drain current obtained through calculation is larger than the measured value. In order to better fit the simulation curve with the actually measured curve, the equivalent resistance coefficient NRS _ NEW of the first doping region is added into the simulation model, which is equivalent to adding the compensation resistor into the simulation model, and due to the voltage division effect of the compensation, the grid voltage applied to the MOS transistor model is close to or equal to the voltage applied to the grid of the MOS transistor during the actually measured process, so that the simulated drain current is basically equal to the actually measured drain current, and the fitting degree of the simulation curve and the actually measured curve is greatly improved.
In the method for extracting the characteristics of the MOS transistor, disclosed by the embodiment of the invention, the equivalent resistance coefficient of a first doping area is obtained according to the wiring resistance and the diffusion resistance, and is added into the MOS transistor model to simulate the parasitic resistance of the MOS transistor, namely, the influence caused by the voltage division effect of the parasitic resistance is added into the simulation model in the simulation process, so that a simulation curve which is closer to an actually measured MOS transistor grid voltage-drain current test curve is obtained.
Embodiments of the apparatus of the present invention will be described below, which can be used to perform the MOS transistor feature extraction method of the present invention. The first doped region of the MOS transistor is electrically connected with the first lead-out bonding pad through a wire. Referring to fig. 4, a MOS transistor simulation apparatus 300 provided by the embodiment of the present invention may include:
a wiring resistance acquisition unit 301 for acquiring the wiring resistance of the wire.
A diffusion resistance obtaining unit 302, configured to obtain a diffusion resistance of a first doped region of the MOS transistor.
A first doped region equivalent resistivity obtaining unit 303, configured to obtain a first doped region equivalent resistivity of the MOS transistor according to the wiring resistance and the diffusion resistance.
And the modeling unit 304 is configured to add the first doping region equivalent resistance coefficient to a pre-established MOS transistor model to perform simulation calculation.
In the technical scheme of the embodiment of the invention, the influence of the diffusion resistance and the wiring resistance of the lead between the source end of different MOS transistors and the first lead-out pad on the parasitic resistance is considered, the sizes of the wiring resistance and the diffusion resistance of different MOS transistors are calculated, the equivalent resistance coefficient of the first doped region is obtained according to the wiring resistance and the diffusion resistance and is added into the simulation model, and therefore, the more accurate voltage-current characteristic of the MOS transistor can be obtained in the simulation process.
In the embodiment of the present invention, the first doped region may be a source electrode, the MOS transistors include a first MOS transistor and a second MOS transistor, and the source electrode of the first MOS transistor and the source electrode of the second MOS transistor are both electrically connected to the first lead pad. And the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor are electrically connected with the second lead-out bonding pad.
The equivalent resistance coefficient of the first doping area is a multiple of the sum of the wiring resistance and the diffusion resistance and the square resistance of the first doping area.
The wiring resistance obtaining unit 302 includes:
and the first acquisition subunit is used for acquiring the length and the width of the wire.
And the second acquisition subunit is used for acquiring the square resistance of the wire. And a wiring resistance obtaining subunit for obtaining the wiring resistance according to the length, the width and the square resistance of the conducting wire.
The diffusion resistance acquiring unit 303 includes:
and the third acquiring subunit is used for acquiring the distance from the center of the first doped region of the MOS transistor to the edge of the grid electrode of the MOS transistor.
And the fourth obtaining subunit is used for obtaining the width of the MOS transistor and the square resistance of the first doping area.
And the diffusion resistance obtaining subunit is used for obtaining the diffusion resistance according to the distance, the width and the square resistance of the first doping area.
The modeling unit 308 is further configured to build a MOS transistor model before adding the first doped region equivalent resistivity to the pre-built MOS transistor model.
The MOS transistor simulation device provided by the embodiment of the invention further comprises a simulation unit, wherein the simulation unit is used for applying grid voltage, source voltage and drain voltage to the MOS transistor to obtain drain current of the MOS transistor and obtaining the voltage-current characteristic of the MOS transistor according to the drain current and the transistor model.
For details which are not disclosed in the embodiments of the apparatus of the present invention, please refer to the above-described embodiment of the method for extracting the MOS transistor feature of the present invention for the details which are not disclosed in the embodiments of the apparatus of the present invention.
In the MOS transistor simulation apparatus according to the embodiment of the present invention, the equivalent resistance coefficient of the first doped region is obtained according to the wiring resistance and the diffusion resistance, and the equivalent resistance coefficient of the first doped region is added to the MOS transistor model to simulate the parasitic resistance of the MOS transistor, that is, the influence caused by the voltage dividing effect of the parasitic resistance is added to the simulation model in the simulation process, so as to obtain a simulation curve closer to the actually measured MOS transistor gate voltage-drain current test curve.
Referring now to FIG. 5, a block diagram of a computer system 400 suitable for use in implementing an electronic device of an embodiment of the invention is shown. The computer system 400 of the electronic device shown in fig. 5 is only an example, and should not bring any limitation to the function and the scope of use of the embodiments of the present invention.
As shown in fig. 5, the computer system 400 includes a Central Processing Unit (CPU)401 that can perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)402 or a program loaded from a storage section 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data necessary for system operation are also stored. The CPU 401, ROM 402, and RAM 403 are connected to each other via a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
The following components are connected to the I/O interface 405: an input section 406 including a keyboard, a mouse, and the like; an output section 407 including a display device such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker; a storage section 408 including a hard disk and the like; and a communication section 409 including a network interface card such as a LAN card, a modem, or the like. The communication section 409 performs communication processing via a network such as the internet. A driver 410 is also connected to the I/O interface 405 as needed. A removable medium 411 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 410 as necessary, so that a computer program read out therefrom is mounted into the storage section 408 as necessary.
In particular, according to an embodiment of the present invention, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the invention include a computer program product comprising a computer program embodied on a computer-readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 409, and/or installed from the removable medium 411. The above-described functions defined in the system of the present application are executed when the computer program is executed by a Central Processing Unit (CPU) 401.
It should be noted that the computer readable medium shown in the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present invention, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present invention, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.
As another aspect, the present invention also provides a computer-readable medium, which may be contained in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to implement the MOS transistor feature extraction method as described in the above embodiments.
For example, the electronic device may implement the following as shown in fig. 2: step S201, obtaining the wiring resistance of the lead; step S202, acquiring a diffusion resistance of a source electrode of the MOS transistor; step S203, obtaining a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance; and step S204, adding the equivalent resistance coefficient of the first doping area into a pre-established MOS transistor model to perform simulation calculation.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the invention. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiment of the present invention can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiment of the present invention.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (10)
1. A method for extracting MOS transistor features, wherein a first doped region of the MOS transistor is electrically connected with a first lead-out bonding pad through a wire, the method comprising the following steps:
obtaining the wiring resistance of the lead;
acquiring a diffusion resistance of a first doped region of the MOS transistor;
obtaining a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance;
adding the equivalent resistance coefficient of the first doped region into a pre-established MOS transistor model to perform simulation calculation;
obtaining the diffusion resistance of the first doped region of the MOS transistor comprises:
acquiring the distance from the center of a first doped region of the MOS transistor to the edge of a grid electrode of the MOS transistor;
acquiring the width of the MOS transistor and the square resistance of the first doped region;
obtaining the diffusion resistance according to the distance, the width of the MOS transistor and the square resistance of the first doping area;
the equivalent resistivity of the first doped region is a multiple of the square resistance of the first doped region and the sum of the wiring resistance and the diffusion resistance.
2. The method of claim 1, wherein obtaining the wiring resistance of the wire comprises:
acquiring the length and the width of the lead;
acquiring the square resistance of the lead;
and obtaining the wiring resistance according to the length of the lead, the width of the lead and the square resistance of the lead.
3. The method of claim 1, wherein the first doped region is a source, the MOS transistors comprise a first MOS transistor and a second MOS transistor, the source of the first MOS transistor and the source of the second MOS transistor are both electrically connected to the first extraction pad; and the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor are electrically connected with the second lead-out bonding pad.
4. The method of claim 3, wherein the second doped region of the MOS transistor is a drain, and wherein after adding the first doped region equivalent resistivity to a pre-established MOS transistor model, the method further comprises:
applying a gate voltage, a source voltage, a drain voltage to the MOS transistor;
obtaining the drain current of the MOS transistor;
and acquiring the voltage-current characteristics of the MOS transistor according to the drain current and the transistor model.
5. An MOS transistor emulation device, a first doped region of the MOS transistor electrically connected to a first extraction pad by a wire, comprising:
a wiring resistance acquisition unit for acquiring a wiring resistance of the wire;
the diffusion resistance acquisition unit is used for acquiring the diffusion resistance of the first doped region of the MOS transistor;
a first doping region equivalent resistance coefficient obtaining unit, configured to obtain a first doping region equivalent resistance coefficient of the MOS transistor according to the wiring resistance and the diffusion resistance, where the first doping region equivalent resistance coefficient is a multiple of a sum of the wiring resistance and the diffusion resistance and a square resistance of the first doping region;
the modeling unit is used for adding the equivalent resistance coefficient of the first doping area into a pre-established MOS transistor model so as to perform simulation calculation;
the diffusion resistance obtaining unit is further configured to:
the third acquiring subunit is used for acquiring the distance from the center of the first doped region of the MOS transistor to the edge of the grid of the MOS transistor;
the fourth obtaining subunit is used for obtaining the width of the MOS transistor and the square resistance of the first doping area;
the diffusion resistance obtaining subunit is used for obtaining the diffusion resistance according to the distance, the width of the MOS transistor and the square resistance of the first doping area;
the equivalent resistivity of the first doped region is a multiple of the square resistance of the first doped region and the sum of the wiring resistance and the diffusion resistance.
6. The apparatus of claim 5, wherein the routing resistance obtaining unit is further configured to:
a first acquiring subunit, configured to acquire a length and a width of the wire;
the second acquisition subunit is used for acquiring the square resistance of the lead;
and the wiring resistance obtaining subunit is used for obtaining the wiring resistance according to the length of the conducting wire, the width of the conducting wire and the square resistance of the conducting wire.
7. The apparatus of claim 5, wherein the first doped region is a source, wherein the MOS transistors comprise a first MOS transistor and a second MOS transistor, and wherein the source of the first MOS transistor and the source of the second MOS transistor are both electrically connected to the first extraction pad; and the grid electrode of the first MOS transistor and the grid electrode of the second MOS transistor are electrically connected with the second lead-out bonding pad.
8. The apparatus of claim 7, wherein the second doped region of the MOS transistor is a drain, the apparatus further comprising an emulation unit configured to:
applying a gate voltage, a source voltage, a drain voltage to the MOS transistor;
obtaining the drain current of the MOS transistor;
and acquiring the voltage-current characteristics of the MOS transistor according to the drain current and the transistor model.
9. A computer-readable storage medium on which a computer program is stored, the program, when executed by a processor, implementing the MOS transistor feature extraction method according to any one of claims 1 to 4.
10. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs that, when executed by the one or more processors, cause the one or more processors to implement the MOS transistor feature extraction method of any one of claims 1 to 4.
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