CN105551969A - Current regulative diode structure and forming method thereof - Google Patents
Current regulative diode structure and forming method thereof Download PDFInfo
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- CN105551969A CN105551969A CN201610082486.7A CN201610082486A CN105551969A CN 105551969 A CN105551969 A CN 105551969A CN 201610082486 A CN201610082486 A CN 201610082486A CN 105551969 A CN105551969 A CN 105551969A
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- 239000000203 mixture Substances 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 19
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- 238000002347 injection Methods 0.000 description 8
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- 238000005468 ion implantation Methods 0.000 description 5
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- 238000004528 spin coating Methods 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
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- 238000012940 design transfer Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
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Abstract
The invention provides a current regulative diode structure and a forming method thereof. A P type emitter region is added in an N type epitaxial layer; an N type source region, a P type gate region, the N type epitaxial layer and an N type drain region form a current regulative diode; and a P type substrate, the N type epitaxial layer and the P type emitter region form a PNP triode. According to the current regulative diode structure and the forming method thereof, the current in the unit area is greatly improved, and temperature stability and uniformity of the device are better.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of current regulator diode structure and forming method thereof.
Background technology
Current regulator diode is the two ends constant current device that a kind of silicon materials manufacture.Current regulator diode is by polarity access circuit loop, and the conducting of forward constant current, oppositely ends, and exports constant current, and application is simple.At present, current regulator diode is widely used in the electronic circuits such as alternating current-direct current amplifier, D.C. regulated power supply, waveform generator and protective circuit.
Traditional current regulator diode adopts planar channeling junction field effect transistor (JunctionField-EffectTransistor usually, JFET) structure, JFET is the P district that making two is highly doped on same N shape semiconductor, the electrode drawn is called grid G, and form highly doped N district, the electrode drawn is called drain D, source S, and current regulator diode is by forming constant-current characteristics by the grid G of JFET and source S short circuit.Concrete, as shown in Figure 1, current regulator diode comprises: P type substrate 10, N-type epitaxy layer 11, P-type grid electrode district 12a, N-type source region 12b, N-type drain region 12c, P type isolation 12d and front electrode 13, wherein, P-type grid electrode district 12a, N-type source region 12b are connected by front electrode 13, and P type isolation 12d penetrates N-type epitaxy layer 11 and is connected with P type substrate 10.But inventor finds, there are the following problems for traditional current regulator diode:
The constant current size of one, the traditional current regulator diode junction depth to N-type epitaxy layer 110 thickness, N-type epitaxy layer 110 resistivity and P-type grid electrode district 121 is very sensitive, and cause final constant current value uniformity very poor, rate of finished products is lower;
Two, the current capacity of planar channeling JFET structure depends primarily on channel width, and channel width limits by front electrode figure, and the channel width of unit are is less, and then causes unit area current less, and cost is higher;
Three, conventional current regulator diode has very large negative temperature coefficient, and high-temperature constant fluidity can not be good.
Summary of the invention
The object of the invention is to the problem of the constant current value lack of homogeneity solving existing current regulator diode.
Another object of the present invention is to solve the problem that the unit area current of existing current regulator diode is less.
Another object of the present invention is to solve the problem that the high-temperature constant fluidity of existing current regulator diode can not be good.
For solving the problems of the technologies described above, the invention provides a kind of current regulator diode structure, comprising:
P type substrate;
Be formed at the N-type epitaxy layer on described P type substrate front;
Be formed at the P-type grid electrode district in described N-type epitaxy layer, N-type source region, N-type drain region, P type emitter region and the isolation of P type; And
Be formed at the front electrode on described P-type grid electrode district, N-type source region and P type emitter region;
Wherein, described P type substrate, N-type epitaxy layer and P type emitter region composition PNP triode, described N-type source region, P-type grid electrode district, N-type epitaxy layer, N-type drain region composition current regulator diode.
Optionally, in described current regulator diode structure, the doping content that described P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type are isolated is greater than the doping content of described N-type epitaxy layer.
Optionally, in described current regulator diode structure, described P-type grid electrode district, P type emitter region, the isolation of P type and P type substrate are the heavy doping of P type, and described N-type source region and N-type drain region are N-type heavy doping.
Optionally, in described current regulator diode structure, the degree of depth in described N-type source region and N-type drain region is less than the degree of depth of described P-type grid electrode district and P type emitter region.
Optionally, in described current regulator diode structure, described P type isolation penetrates described N-type epitaxy layer and is connected with described P type substrate.
Optionally, in described current regulator diode structure, also comprise the backplate be formed on the described P type substrate back side.
Optionally, in described current regulator diode structure, described P type emitter region and P-type grid electrode district diffuse to form simultaneously.
Optionally, in described current regulator diode structure, described P type emitter region is strip structure, and described N-type drain region is loop configuration, and described N-type drain region surrounds described P type emitter region.Described current regulator diode structure comprises Liang Ge P-type grid electrode district and two N-type source regions, described Liang Ge P-type grid electrode district and described two N-type source regions are strip structure, and described Liang Ge P-type grid electrode district is positioned at the both sides in described N-type drain region, described two N-type source regions are positioned at the both sides in described Liang Ge P-type grid electrode district.Described P type is isolated into loop configuration, and described N-type source region is surrounded in the isolation of described P type.
Optionally, in described current regulator diode structure, described P type substrate is as the collector electrode of described PNP triode, and described N-type epitaxy layer is as the base stage of described PNP triode, and described P type emitter region is as the emitter of described PNP triode.
Optionally, in described current regulator diode structure, the base current of described PNP triode, behind P type emitter region, flows through N-type drain region, N-type epitaxy layer, P-type grid electrode district, N-type source region successively, flows out from the back side of P type substrate finally by being isolated by P type; The collector current of described PNP triode, behind P type emitter region, flows through N-type epitaxy layer and flows out from the back side of P type substrate.
The present invention also provides a kind of formation method of current regulator diode structure, comprising:
One P type substrate is provided;
Described P type substrate front forms N-type epitaxy layer;
P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and the isolation of P type is formed in described N-type epitaxy layer; And
Described P-type grid electrode district, N-type source region and P type emitter region form front electrode;
Wherein, described P type substrate, N-type epitaxy layer and P type emitter region composition PNP triode, described N-type source region, P-type grid electrode district, N-type epitaxy layer, N-type drain region composition current regulator diode.
Optionally, in the formation method of described current regulator diode structure, formed in described N-type epitaxy layer P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type isolation step comprise:
The isolation of described P type is formed in described N-type epitaxy layer;
Described P-type grid electrode district and P type emitter region is formed in described N-type epitaxy layer;
Described N-type source region and N-type drain region is formed in described N-type epitaxy layer.
Optionally, in the formation method of described current regulator diode structure, described P type emitter region and P-type grid electrode district diffuse to form simultaneously.
Optionally, in the formation method of described current regulator diode structure, the doping content that described P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type are isolated is greater than the doping content of described N-type epitaxy layer.
Optionally, in the formation method of described current regulator diode structure, described P-type grid electrode district, P type emitter region, the isolation of P type and P type substrate are the heavy doping of P type, and described N-type source region and N-type drain region are N-type heavy doping.
Optionally, in the formation method of described current regulator diode structure, the degree of depth in described N-type source region and N-type drain region is less than the degree of depth of described P-type grid electrode district and P type emitter region.
Optionally, in the formation method of described current regulator diode structure, described P type isolation penetrates described N-type epitaxy layer and is connected with described P type substrate.
Optionally, in the formation method of described current regulator diode structure, the step that described P-type grid electrode district, N-type source region and P type emitter region are formed front electrode comprises:
Described N-type epitaxy layer forms insulating barrier;
In described insulating barrier, fairlead is formed by photoetching and etching technics;
Front metal layer is formed by sputtering technology;
Described front electrode is formed by photoetching and the graphical described front metal layer of etching technics.
Optionally, in the formation method of described current regulator diode structure, after described P-type grid electrode district, N-type source region and P type emitter region form front electrode, also comprise: on the back side of described P type substrate, form backplate.
Optionally, in the formation method of described current regulator diode structure, described P type emitter region is strip structure, and described N-type drain region is loop configuration, and described N-type drain region surrounds described P type emitter region.Described current regulator diode structure comprises Liang Ge P-type grid electrode district and two N-type source regions, described Liang Ge P-type grid electrode district and described two N-type source regions are strip structure, and described Liang Ge P-type grid electrode district is positioned at the both sides in described N-type drain region, described two N-type source regions are positioned at the both sides in described Liang Ge P-type grid electrode district.Described P type is isolated into loop configuration, and described N-type source region is surrounded in the isolation of described P type.
Optionally, in the formation method of described current regulator diode structure, described P type substrate is as the collector electrode of described PNP triode, and described N-type epitaxy layer is as the base stage of described PNP triode, and described P type emitter region is as the emitter of described PNP triode.
Optionally, in the formation method of described current regulator diode structure, the base current of described PNP triode, behind P type emitter region, flows through N-type drain region, N-type epitaxy layer, P-type grid electrode district, N-type source region successively, flows out from the back side of P type substrate finally by being isolated by P type; The collector current of described PNP triode, behind P type emitter region, flows through N-type epitaxy layer and flows out from the back side of P type substrate.
In current regulator diode structure provided by the invention, P type emitter region is set up in N-type epitaxy layer, N-type source region, P-type grid electrode district, N-type epitaxy layer, N-type drain region composition current regulator diode, P type substrate, N-type epitaxy layer and P type emitter region composition PNP triode, thus, the constant current of current regulator diode exports after PNP triode Current amplifier, and unit area current significantly improves.In addition, PNP triode multiplication factor β has positive temperature coefficient, and current regulator diode constant current is negative temperature coefficient, and so, the temperature stability of device is better.In addition, when the junction depth of PNP triode and current regulator diode fluctuates in the same way and changes, the constant current Id inverse variation direction of PNP triode multiplication factor β and current regulator diode, the total output current of whole device is more stable, and uniformity is better.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of traditional current regulator diode structure;
Fig. 2 is the cross-sectional view of the current regulator diode structure of one embodiment of the invention;
Fig. 3 is the schematic equivalent circuit of the current regulator diode structure of one embodiment of the invention;
Fig. 4 a ~ 4e is the cross-sectional view in the current regulator diode structure-forming process of one embodiment of the invention;
Fig. 5 is the plan structure schematic diagram of the current regulator diode structure of one embodiment of the invention;
Fig. 6 is the plan structure schematic diagram of the current regulator diode structure of another embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the current regulator diode structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 2, the application provides a kind of current regulator diode structure, comprising: P type substrate 100; Be formed at the N-type epitaxy layer 110 on described P type substrate 100 front; Be formed at the P-type grid electrode district 121 in described N-type epitaxy layer 110, N-type source region 122, N-type drain region 123, P type emitter region 124 and P type isolation 125; Be formed at the front electrode 130 on described P-type grid electrode district 121, N-type source region 122 and P type emitter region 124.
Wherein, the doping content of described P-type grid electrode district 121, N-type source region 122, N-type drain region 123, P type emitter region 124 and P type isolation 125 is greater than the doping content of described N-type epitaxy layer 110, described P-type grid electrode district 121, N-type source region 122 are connected by described front electrode 130, and described P type isolation 125 penetrates described N-type epitaxy layer 110 and is connected with described P type substrate 100.
The equivalent circuit structure of described current regulator diode structure as shown in Figure 3, shown in composition graphs 2, described P type substrate 100, N-type epitaxy layer 110 and P type emitter region 124 form PNP triode, wherein, P type substrate 100 is as the collector electrode of longitudinal P NP triode, N-type epitaxy layer 110 is as the base stage of PNP triode, and P type emitter region 124 is as the emitter of PNP triode.Described N-type source region 122, P-type grid electrode district 121, N-type epitaxy layer 110, N-type drain region 123 form current regulator diode.The base current of PNP triode is behind P type emitter region 124, flow through N-type drain region 123, N-type epitaxy layer 110, P-type grid electrode district 121, N-type source region 122 successively, flow out from the back side of P type substrate 100 finally by isolating 125 by P type, the base current size of PNP triode is determined by the constant current Id of current regulator diode; The collector current of PNP triode, behind P type emitter region 124, flows through N-type epitaxy layer 110 and flows out from the back side of P type substrate 100, and this collector current size equals the β of base current doubly, and namely the β of the constant current Id of current regulator diode doubly.
The present invention is by setting up P type emitter region 124, thus form PNP triode, the constant current Id of current regulator diode exports after PNP triode Current amplifier β times, the total current I that whole device architecture finally exports equals (the 1+ β) of the constant current Id of current regulator diode doubly, unit area current significantly improves, and cost is lower.In addition, PNP triode multiplication factor β has positive temperature coefficient, and current regulator diode constant current Id is negative temperature coefficient, and so, the temperature stability of device architecture of the present invention is relatively good.In addition, when the junction depth of PNP triode and current regulator diode fluctuates in the same way and changes, the constant current Id inverse variation direction of PNP triode multiplication factor β and current regulator diode, whole device total current I is more stable, and (width of N-type epitaxy layer 110 is less, resistivity is higher, the electric current of current regulator diode is less, PNP triode multiplication factor β is then larger, so can offset part fluctuation), its uniformity is better.Especially the P type emitter region 124 of PNP triode adopts same process with the P-type grid electrode district 121 of JFET structure, diffuses to form simultaneously, is more conducive to the stability improving the total current I that whole device finally exports.
In preferred version, described P-type grid electrode district 121, P type emitter region 124, P type isolation 125 are P type heavy doping (P+), described N-type source region 122, N-type drain region 123 are N-type heavy doping (N+), and described P type substrate is also P type heavy doping (P+).
Further, described current regulator diode structure also comprises the backplate 150 be formed on P type substrate 100 back side, and described backplate 150 is such as formed by the material such as gold, silver, aluminium.
Fig. 5 is the plan structure schematic diagram of the current regulator diode structure of one embodiment of the invention.In order to the structure of clearer PNP triode and current regulator diode, in Fig. 5, do not indicate front electrode 130.In the present embodiment, as shown in Figure 5, P type emitter region 124 is strip structure, and N-type drain region 123 is loop configuration, and N-type drain region 123 surrounds P type emitter region 124; P-type grid electrode district 121 and N-type source region 122 are strip structure, and Liang Ge P-type grid electrode district 121 is respectively in the both sides in N-type drain region 123, and two N-type source regions 122 are respectively in the both sides in Liang Ge P-type grid electrode district 121; P type isolation 125 is loop configuration, and it surrounds described two N-type source regions 122.Be to be understood that and be, above arrangement mode is only illustrate not in order to limit current regulator diode structure of the present invention, such as, as shown in Figure 6, in an alternative embodiment of the invention, described P type emitter region 124 also can be " work " character form structure, to increase the emitter region girth of PNP triode, improve PNP triode current capacity, accordingly, described N-type drain region 123 is the loop configuration of indent, to ensure the spacing in N-type drain region 123 and P type emitter region 124.Meanwhile, the quantity of described P type emitter region 124 can be one also can be multiple, if a chip comprises multiple P type emitter region can increase current capacity accordingly.In a word, the present invention does not limit quantity and the shape of P type emitter region 124.
The forming process of current regulator diode structure of the present invention is introduced in detail below in conjunction with Fig. 4 a to Fig. 4 e.
As shown in fig. 4 a, first, a P type substrate 100 is provided.The material of described P type substrate 100 can be the one in silicon, germanium or germanium silicon compound, organic compound semiconductor material.Described P type substrate 100 can select 5 inches, 6 inches, 8 inches and more large-sized silicon wafers.The resistivity of described P type substrate 100 is preferably less than 0.02 Ω cm.
As shown in Figure 4 b, then, described P type substrate 100 front forms N-type epitaxy layer 110.In described P type substrate 100, N-type epitaxy layer 110 is formed by epitaxial growth technology.The thickness of described N-type epitaxy layer 110 is such as 2 μm ~ 6 μm.
As illustrated in fig. 4 c, then, form P type isolation 125 in described N-type epitaxy layer 110, described P type isolation 125 penetrates described N-type epitaxy layer 110 and is connected with described P type substrate 100.
As a nonrestrictive example, the concrete steps forming described P type isolation 125 comprise: first, N-type epitaxy layer 110 forms silicon oxide layer, spin coating photoresist layer on silicon oxide layer; Exposure imaging is carried out to this photoresist layer, photoresist layer is formed P type isolation pattern of windows; Be mask again with photoresist layer, by P type isolation window design transfer on silicon oxide layer, under making N-type epitaxy layer 110 be exposed to this P type isolation window; Then carry out P type ion implantation to N-type epitaxy layer 110 part of this exposure, Implantation Energy is such as 50 ~ 70Kev, preferably 60Kev, and implantation dosage is such as 1E14 ~ 1E16 ㎝
-2, the P type ion of injection is such as boron ion; After injection completes, remove photoresist layer and silicon oxide layer; Finally, at nitrogen (N
2) carry out annealing process under atmosphere, annealing temperature is such as 1150 DEG C ~ 1250 DEG C, and annealing time is such as 30 ~ 240 minutes, forms described P type isolation 125.Above-mentioned photoresist layer, the film-forming process of silicon oxide layer and thermal anneal process are all the technique that industry generally adopts, and just do not repeat herein.
As shown in figure 4d, then, in described N-type epitaxy layer 110, form P-type grid electrode district 121 and P type emitter region 124 simultaneously.The degree of depth of described P-type grid electrode district 121 and P type emitter region 124 is less than the thickness of N-type epitaxy layer 110.
As a nonrestrictive example, the concrete steps forming described P type isolation 125 and P-type grid electrode district 121 comprise: first, N-type epitaxy layer 110 forms silicon oxide layer, spin coating photoresist layer on silicon oxide layer; Exposure imaging is carried out to this photoresist layer, photoresist layer is formed P type emitter window pattern; Be mask again with photoresist layer, by P type emitter window design transfer on silicon oxide layer, under making N-type epitaxy layer 110 be exposed to this P type emitter window; Then carry out P type ion implantation to N-type epitaxy layer 110 part of this exposure, Implantation Energy is such as 50 ~ 70Kev, preferably 60Kev, and implantation dosage is such as 1E14 ~ 5E15 ㎝
-2, the P type ion of injection is such as boron ion; After injection completes, remove photoresist layer and silicon oxide layer; Then, again in N-type epitaxy layer 110, form silicon oxide layer, and on silicon oxide layer spin coating photoresist layer; Then exposure imaging is carried out to this photoresist layer, photoresist layer is formed P-type grid electrode district pattern of windows; Be mask again with photoresist layer, P-type grid electrode district pattern of windows is transferred on silicon oxide layer, under making N-type epitaxy layer 110 be exposed to this P-type grid electrode district window; Carry out P type ion implantation to N-type epitaxy layer 110 part of this exposure, Implantation Energy is such as 50 ~ 70Kev, preferably 60Kev, and implantation dosage is such as 1E13 ~ 5E14 ㎝
-2, the P type ion of injection is such as boron ion; After injection completes, remove photoresist layer and silicon oxide layer; Finally, at nitrogen (N
2) carry out annealing process under atmosphere, annealing temperature is such as 1000 DEG C ~ 1100 DEG C, and annealing time is such as 30 ~ 180 minutes, forms described P-type grid electrode district 121 and P type emitter region 124 simultaneously.Be understandable that, aforementioned p-type isolation 125 and P-type grid electrode district 121 can adopt identical ion implantation technology condition and is formationed of simultaneously annealing, also but adopt different ion implanting conditions, formation of annealing respectively.But should be understood that the P type emitter region 124 of PNP triode adopts same process with the P-type grid electrode district 121 of JFET structure, diffuses to form simultaneously, be more conducive to the stability improving total output current that whole device finally exports.
As shown in fig 4e, form N-type source region 122, N-type drain region 123 in described N-type epitaxy layer 110, the degree of depth in described N-type source region 122, N-type drain region 123 is less than the degree of depth of P-type grid electrode district 121, P type emitter region 124.
As a nonrestrictive example, form described N-type source region 122, the concrete steps in N-type drain region 123 comprise: first, N-type epitaxy layer 110 forms silicon oxide layer, spin coating photoresist layer on silicon oxide layer; Exposure imaging is carried out to this photoresist layer, photoresist layer is formed N-type source region, N-type drain region pattern of windows; Be mask again with photoresist layer, N-type source region, N-type drain region pattern of windows are transferred on silicon oxide layer, under making N-type epitaxy layer 110 be exposed to this N-type source region, N-type drain region window; Then carry out N-type ion implantation to N-type epitaxy layer 110 part of this exposure, Implantation Energy is such as 140 ~ 160Kev, preferably 150Kev, and implantation dosage is such as 5E14 ~ 2E16 ㎝
-2, the N-type ion of injection is such as phosphonium ion; After injection completes, remove photoresist layer and silicon oxide layer; Finally, at nitrogen (N
2) carry out annealing process under atmosphere, annealing temperature is such as 850 DEG C ~ 1050 DEG C, and annealing time is such as 30 ~ 60 minutes, forms described N-type source region 122, N-type drain region 123 simultaneously.
Then, shown in figure 2, described N-type epitaxy layer 110 forms insulating barrier 140, and in described insulating barrier 140, form fairlead by photoetching and etching technics, then form front metal layer by sputtering technology, then form front electrode 130 by photoetching and the graphical described front metal layer of etching technics, described P-type grid electrode district 121, N-type source region 122 are connected by described front electrode 130, finally, the back side of P type substrate 100 forms backplate 150.The material of described insulating barrier 140 is such as silicon dioxide, and the material of described front electrode 130 and backplate 150 is such as gold, silver, aluminium etc., does not limit at this.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (26)
1. a current regulator diode structure, is characterized in that, comprising:
P type substrate;
Be formed at the N-type epitaxy layer on described P type substrate front;
Be formed at the P-type grid electrode district in described N-type epitaxy layer, N-type source region, N-type drain region, P type emitter region and the isolation of P type; And
Be formed at the front electrode on described P-type grid electrode district, N-type source region and P type emitter region;
Wherein, described P type substrate, N-type epitaxy layer and P type emitter region composition PNP triode, described N-type source region, P-type grid electrode district, N-type epitaxy layer, N-type drain region composition current regulator diode.
2. current regulator diode structure as claimed in claim 1, is characterized in that, the doping content that described P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type are isolated is greater than the doping content of described N-type epitaxy layer.
3. current regulator diode structure as claimed in claim 2, is characterized in that, described P-type grid electrode district, P type emitter region, the isolation of P type and P type substrate are the heavy doping of P type, and described N-type source region and N-type drain region are N-type heavy doping.
4. current regulator diode structure as claimed in claim 1, it is characterized in that, the degree of depth in described N-type source region and N-type drain region is less than the degree of depth of described P-type grid electrode district and P type emitter region.
5. current regulator diode structure as claimed in claim 1, is characterized in that, described P type isolation penetrates described N-type epitaxy layer and is connected with described P type substrate.
6. current regulator diode structure as claimed in claim 1, is characterized in that, also comprise the backplate be formed on the described P type substrate back side.
7. current regulator diode structure as claimed in claim 1, it is characterized in that, described P type emitter region and P-type grid electrode district diffuse to form simultaneously.
8. the current regulator diode structure according to any one of claim 1 to 7, is characterized in that, described P type emitter region is strip structure, and described N-type drain region is loop configuration, and described N-type drain region surrounds described P type emitter region.
9. the current regulator diode structure according to any one of claim 1 to 7, it is characterized in that, described current regulator diode structure comprises Liang Ge P-type grid electrode district and two N-type source regions, described Liang Ge P-type grid electrode district and described two N-type source regions are strip structure, and described Liang Ge P-type grid electrode district is positioned at the both sides in described N-type drain region, described two N-type source regions are positioned at the both sides in described Liang Ge P-type grid electrode district.
10. the current regulator diode structure according to any one of claim 1 to 7, is characterized in that, described P type is isolated into loop configuration, and described N-type source region is surrounded in the isolation of described P type.
11. current regulator diode structures according to any one of claim 1 to 7, it is characterized in that, described P type substrate is as the collector electrode of described PNP triode, and described N-type epitaxy layer is as the base stage of described PNP triode, and described P type emitter region is as the emitter of described PNP triode.
12. current regulator diode structures as claimed in claim 11, it is characterized in that, the base current of described PNP triode, behind P type emitter region, flows through N-type drain region, N-type epitaxy layer, P-type grid electrode district, N-type source region successively, flows out from the back side of P type substrate finally by being isolated by P type; The collector current of described PNP triode, behind P type emitter region, flows through N-type epitaxy layer and flows out from the back side of P type substrate.
The formation method of 13. 1 kinds of current regulator diode structures, is characterized in that, comprising:
One P type substrate is provided;
Described P type substrate front forms N-type epitaxy layer;
P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and the isolation of P type is formed in described N-type epitaxy layer; And
Described P-type grid electrode district, N-type source region and P type emitter region form front electrode;
Wherein, described P type substrate, N-type epitaxy layer and P type emitter region composition PNP triode, described N-type source region, P-type grid electrode district, N-type epitaxy layer, N-type drain region composition current regulator diode.
The formation method of 14. current regulator diode structures as claimed in claim 13, is characterized in that, formed in described N-type epitaxy layer P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type isolation step comprise:
The isolation of described P type is formed in described N-type epitaxy layer;
Described P-type grid electrode district and P type emitter region is formed in described N-type epitaxy layer;
Described N-type source region and N-type drain region is formed in described N-type epitaxy layer.
The formation method of 15. current regulator diode structures as claimed in claim 14, it is characterized in that, described P type emitter region and P-type grid electrode district diffuse to form simultaneously.
The formation method of 16. current regulator diode structures as claimed in claim 13, is characterized in that, the doping content that described P-type grid electrode district, N-type source region, N-type drain region, P type emitter region and P type are isolated is greater than the doping content of described N-type epitaxy layer.
The formation method of 17. current regulator diode structures as claimed in claim 16, is characterized in that, described P-type grid electrode district, P type emitter region, the isolation of P type and P type substrate are the heavy doping of P type, and described N-type source region and N-type drain region are N-type heavy doping.
The formation method of 18. current regulator diode structures as claimed in claim 13, is characterized in that, the degree of depth in described N-type source region and N-type drain region is less than the degree of depth of described P-type grid electrode district and P type emitter region.
The formation method of 19. current regulator diode structures as claimed in claim 13, is characterized in that, described P type isolation penetrates described N-type epitaxy layer and is connected with described P type substrate.
The formation method of 20. current regulator diode structures as claimed in claim 13, is characterized in that, the step that described P-type grid electrode district, N-type source region and P type emitter region are formed front electrode comprises:
Described N-type epitaxy layer forms insulating barrier;
In described insulating barrier, fairlead is formed by photoetching and etching technics;
Front metal layer is formed by sputtering technology;
Described front electrode is formed by photoetching and the graphical described front metal layer of etching technics.
The formation method of 21. current regulator diode structures as claimed in claim 13, is characterized in that, after described P-type grid electrode district, N-type source region and P type emitter region form front electrode, also comprises:
The back side of described P type substrate forms backplate.
The formation method of 22. current regulator diode structures according to any one of claim 13 to 21, it is characterized in that, described P type emitter region is strip structure, and described N-type drain region is loop configuration, and described N-type drain region surrounds described P type emitter region.
The formation method of 23. current regulator diode structures according to any one of claim 13 to 21, it is characterized in that, described current regulator diode structure comprises Liang Ge P-type grid electrode district and two N-type source regions, described Liang Ge P-type grid electrode district and described two N-type source regions are strip structure, and described Liang Ge P-type grid electrode district is positioned at the both sides in described N-type drain region, described two N-type source regions are positioned at the both sides in described Liang Ge P-type grid electrode district.
The formation method of 24. current regulator diode structures according to any one of claim 13 to 21, it is characterized in that, described P type is isolated into loop configuration, and described N-type source region is surrounded in the isolation of described P type.
The formation method of 25. current regulator diode structures according to any one of claim 13 to 21, it is characterized in that, described P type substrate is as the collector electrode of described PNP triode, described N-type epitaxy layer is as the base stage of described PNP triode, and described P type emitter region is as the emitter of described PNP triode.
The formation method of 26. current regulator diode structures as claimed in claim 25, it is characterized in that, the base current of described PNP triode, behind P type emitter region, flows through N-type drain region, N-type epitaxy layer, P-type grid electrode district, N-type source region successively, flows out from the back side of P type substrate finally by being isolated by P type; The collector current of described PNP triode, behind P type emitter region, flows through N-type epitaxy layer and flows out from the back side of P type substrate.
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| CN107293598A (en) * | 2016-11-25 | 2017-10-24 | 扬州国宇电子有限公司 | A kind of low QRR plane fast recovery diode chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224139A (en) * | 2002-01-30 | 2003-08-08 | Sony Corp | Semiconductor device and its manufacturing method |
| US6696706B1 (en) * | 2002-10-22 | 2004-02-24 | Lovoltech, Inc. | Structure and method for a junction field effect transistor with reduced gate capacitance |
| CN1716562A (en) * | 2004-06-14 | 2006-01-04 | 海力士半导体有限公司 | Method for manufacturing cell transistor |
| CN205542795U (en) * | 2016-02-05 | 2016-08-31 | 杭州士兰集成电路有限公司 | Current regulator diode structure |
-
2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003224139A (en) * | 2002-01-30 | 2003-08-08 | Sony Corp | Semiconductor device and its manufacturing method |
| US6696706B1 (en) * | 2002-10-22 | 2004-02-24 | Lovoltech, Inc. | Structure and method for a junction field effect transistor with reduced gate capacitance |
| CN1716562A (en) * | 2004-06-14 | 2006-01-04 | 海力士半导体有限公司 | Method for manufacturing cell transistor |
| CN205542795U (en) * | 2016-02-05 | 2016-08-31 | 杭州士兰集成电路有限公司 | Current regulator diode structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293598A (en) * | 2016-11-25 | 2017-10-24 | 扬州国宇电子有限公司 | A kind of low QRR plane fast recovery diode chip |
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